2 * arch/ppc64/kernel/pSeries_iommu.c
4 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
40 #include <asm/ppcdebug.h>
41 #include <asm/iommu.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/abs_addr.h>
45 #include <asm/plpar_wrappers.h>
46 #include <asm/pSeries_reconfig.h>
47 #include <asm/systemcfg.h>
48 #include <asm/firmware.h>
54 extern int is_python(struct device_node *);
56 static void tce_build_pSeries(struct iommu_table *tbl, long index,
57 long npages, unsigned long uaddr,
58 enum dma_data_direction direction)
64 t.te_rdwr = 1; // Read allowed
66 if (direction != DMA_TO_DEVICE)
69 tp = ((union tce_entry *)tbl->it_base) + index;
72 /* can't move this out since we might cross LMB boundary */
73 t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
75 tp->te_word = t.te_word;
83 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
89 tp = ((union tce_entry *)tbl->it_base) + index;
92 tp->te_word = t.te_word;
99 static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
100 long npages, unsigned long uaddr,
101 enum dma_data_direction direction)
107 tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
109 if (direction != DMA_TO_DEVICE)
113 rc = plpar_tce_put((u64)tbl->it_index,
117 if (rc && printk_ratelimit()) {
118 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
119 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
120 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
121 printk("\ttce val = 0x%lx\n", tce.te_word );
122 show_stack(current, (unsigned long *)__get_SP());
130 static DEFINE_PER_CPU(void *, tce_page) = NULL;
132 static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
133 long npages, unsigned long uaddr,
134 enum dma_data_direction direction)
137 union tce_entry tce, *tcep;
141 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
144 tcep = __get_cpu_var(tce_page);
146 /* This is safe to do since interrupts are off when we're called
147 * from iommu_alloc{,_sg}()
150 tcep = (void *)__get_free_page(GFP_ATOMIC);
151 /* If allocation fails, fall back to the loop implementation */
153 return tce_build_pSeriesLP(tbl, tcenum, npages,
155 __get_cpu_var(tce_page) = tcep;
159 tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
161 if (direction != DMA_TO_DEVICE)
164 /* We can map max one pageful of TCEs at a time */
167 * Set up the page with TCE data, looping through and setting
170 limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry));
172 for (l = 0; l < limit; l++) {
177 rc = plpar_tce_put_indirect((u64)tbl->it_index,
179 (u64)virt_to_abs(tcep),
184 } while (npages > 0 && !rc);
186 if (rc && printk_ratelimit()) {
187 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
188 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
189 printk("\tnpages = 0x%lx\n", (u64)npages);
190 printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);
191 show_stack(current, (unsigned long *)__get_SP());
195 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
203 rc = plpar_tce_put((u64)tbl->it_index,
207 if (rc && printk_ratelimit()) {
208 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
209 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
210 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
211 printk("\ttce val = 0x%lx\n", tce.te_word );
212 show_stack(current, (unsigned long *)__get_SP());
220 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
227 rc = plpar_tce_stuff((u64)tbl->it_index,
232 if (rc && printk_ratelimit()) {
233 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
234 printk("\trc = %ld\n", rc);
235 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
236 printk("\tnpages = 0x%lx\n", (u64)npages);
237 printk("\ttce val = 0x%lx\n", tce.te_word );
238 show_stack(current, (unsigned long *)__get_SP());
242 static void iommu_table_setparms(struct pci_controller *phb,
243 struct device_node *dn,
244 struct iommu_table *tbl)
246 struct device_node *node;
247 unsigned long *basep;
250 node = (struct device_node *)phb->arch_data;
252 basep = (unsigned long *)get_property(node, "linux,tce-base", NULL);
253 sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL);
254 if (basep == NULL || sizep == NULL) {
255 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
256 "missing tce entries !\n", dn->full_name);
260 tbl->it_base = (unsigned long)__va(*basep);
261 memset((void *)tbl->it_base, 0, *sizep);
263 tbl->it_busno = phb->bus->number;
265 /* Units of tce entries */
266 tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT;
268 /* Test if we are going over 2GB of DMA space */
269 if (phb->dma_window_base_cur + phb->dma_window_size > (1L << 31))
270 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
272 phb->dma_window_base_cur += phb->dma_window_size;
274 /* Set the tce table size - measured in entries */
275 tbl->it_size = phb->dma_window_size >> PAGE_SHIFT;
278 tbl->it_blocksize = 16;
279 tbl->it_type = TCE_PCI;
283 * iommu_table_setparms_lpar
285 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
287 * ToDo: properly interpret the ibm,dma-window property. The definition is:
288 * logical-bus-number (1 word)
289 * phys-address (#address-cells words)
290 * size (#cell-size words)
292 * Currently we hard code these sizes (more or less).
294 static void iommu_table_setparms_lpar(struct pci_controller *phb,
295 struct device_node *dn,
296 struct iommu_table *tbl,
297 unsigned int *dma_window)
299 tbl->it_busno = PCI_DN(dn)->bussubno;
301 /* TODO: Parse field size properties properly. */
302 tbl->it_size = (((unsigned long)dma_window[4] << 32) |
303 (unsigned long)dma_window[5]) >> PAGE_SHIFT;
304 tbl->it_offset = (((unsigned long)dma_window[2] << 32) |
305 (unsigned long)dma_window[3]) >> PAGE_SHIFT;
307 tbl->it_index = dma_window[0];
308 tbl->it_blocksize = 16;
309 tbl->it_type = TCE_PCI;
312 static void iommu_bus_setup_pSeries(struct pci_bus *bus)
314 struct device_node *dn, *pdn;
316 struct iommu_table *tbl;
318 DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);
320 /* For each (root) bus, we carve up the available DMA space in 256MB
321 * pieces. Since each piece is used by one (sub) bus/device, that would
322 * give a maximum of 7 devices per PHB. In most cases, this is plenty.
324 * The exception is on Python PHBs (pre-POWER4). Here we don't have EADS
325 * bridges below the PHB to allocate the sectioned tables to, so instead
326 * we allocate a 1GB table at the PHB level.
329 dn = pci_bus_to_OF_node(bus);
335 unsigned int *iohole;
337 DBG("Python root bus %s\n", bus->name);
339 iohole = (unsigned int *)get_property(dn, "io-hole", 0);
342 /* On first bus we need to leave room for the
343 * ISA address space. Just skip the first 256MB
344 * alltogether. This leaves 768MB for the window.
346 DBG("PHB has io-hole, reserving 256MB\n");
347 pci->phb->dma_window_size = 3 << 28;
348 pci->phb->dma_window_base_cur = 1 << 28;
350 /* 1GB window by default */
351 pci->phb->dma_window_size = 1 << 30;
352 pci->phb->dma_window_base_cur = 0;
355 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
357 iommu_table_setparms(pci->phb, dn, tbl);
358 pci->iommu_table = iommu_init_table(tbl);
360 /* Do a 128MB table at root. This is used for the IDE
361 * controller on some SMP-mode POWER4 machines. It
362 * doesn't hurt to allocate it on other machines
363 * -- it'll just be unused since new tables are
364 * allocated on the EADS level.
366 * Allocate at offset 128MB to avoid having to deal
367 * with ISA holes; 128MB table for IDE is plenty.
369 pci->phb->dma_window_size = 1 << 27;
370 pci->phb->dma_window_base_cur = 1 << 27;
372 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
374 iommu_table_setparms(pci->phb, dn, tbl);
375 pci->iommu_table = iommu_init_table(tbl);
377 /* All child buses have 256MB tables */
378 pci->phb->dma_window_size = 1 << 28;
381 pdn = pci_bus_to_OF_node(bus->parent);
383 if (!bus->parent->self && !is_python(pdn)) {
384 struct iommu_table *tbl;
385 /* First child and not python means this is the EADS
386 * level. Allocate new table for this slot with 256MB
390 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
392 iommu_table_setparms(pci->phb, dn, tbl);
394 pci->iommu_table = iommu_init_table(tbl);
396 /* Lower than first child or under python, use parent table */
397 pci->iommu_table = PCI_DN(pdn)->iommu_table;
403 static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus)
405 struct iommu_table *tbl;
406 struct device_node *dn, *pdn;
408 unsigned int *dma_window = NULL;
410 DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self);
412 dn = pci_bus_to_OF_node(bus);
414 /* Find nearest ibm,dma-window, walking up the device tree */
415 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
416 dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL);
417 if (dma_window != NULL)
421 if (dma_window == NULL) {
422 DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name);
427 if (!ppci->iommu_table) {
428 /* Bussubno hasn't been copied yet.
429 * Do it now because iommu_table_setparms_lpar needs it.
432 ppci->bussubno = bus->number;
434 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
437 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
439 ppci->iommu_table = iommu_init_table(tbl);
443 PCI_DN(dn)->iommu_table = ppci->iommu_table;
447 static void iommu_dev_setup_pSeries(struct pci_dev *dev)
449 struct device_node *dn, *mydn;
451 DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, dev->pretty_name);
452 /* Now copy the iommu_table ptr from the bus device down to the
453 * pci device_node. This means get_iommu_table() won't need to search
454 * up the device tree to find it.
456 mydn = dn = pci_device_to_OF_node(dev);
458 while (dn && dn->data && PCI_DN(dn)->iommu_table == NULL)
461 if (dn && dn->data) {
462 PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table;
464 DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, dev->pretty_name);
468 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
471 struct device_node *np = node;
472 struct pci_dn *pci = np->data;
475 case PSERIES_RECONFIG_REMOVE:
476 if (pci->iommu_table &&
477 get_property(np, "ibm,dma-window", NULL))
478 iommu_free_table(np);
487 static struct notifier_block iommu_reconfig_nb = {
488 .notifier_call = iommu_reconfig_notifier,
491 static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
493 struct device_node *pdn, *dn;
494 struct iommu_table *tbl;
495 int *dma_window = NULL;
498 DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, dev->pretty_name);
500 /* dev setup for LPAR is a little tricky, since the device tree might
501 * contain the dma-window properties per-device and not neccesarily
502 * for the bus. So we need to search upwards in the tree until we
503 * either hit a dma-window property, OR find a parent with a table
506 dn = pci_device_to_OF_node(dev);
508 for (pdn = dn; pdn && pdn->data && !PCI_DN(pdn)->iommu_table;
510 dma_window = (unsigned int *)
511 get_property(pdn, "ibm,dma-window", NULL);
516 /* Check for parent == NULL so we don't try to setup the empty EADS
517 * slots on POWER4 machines.
519 if (dma_window == NULL || pdn->parent == NULL) {
520 /* Fall back to regular (non-LPAR) dev setup */
521 DBG("No dma window for device, falling back to regular setup\n");
522 iommu_dev_setup_pSeries(dev);
525 DBG("Found DMA window, allocating table\n");
529 if (!pci->iommu_table) {
530 /* iommu_table_setparms_lpar needs bussubno. */
531 pci->bussubno = pci->phb->bus->number;
533 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
536 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
538 pci->iommu_table = iommu_init_table(tbl);
542 PCI_DN(dn)->iommu_table = pci->iommu_table;
545 static void iommu_bus_setup_null(struct pci_bus *b) { }
546 static void iommu_dev_setup_null(struct pci_dev *d) { }
548 /* These are called very early. */
549 void iommu_init_early_pSeries(void)
551 if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
552 /* Direct I/O, IOMMU off */
553 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
554 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
555 pci_direct_iommu_init();
560 if (systemcfg->platform & PLATFORM_LPAR) {
561 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
562 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
563 ppc_md.tce_free = tce_freemulti_pSeriesLP;
565 ppc_md.tce_build = tce_build_pSeriesLP;
566 ppc_md.tce_free = tce_free_pSeriesLP;
568 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP;
569 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP;
571 ppc_md.tce_build = tce_build_pSeries;
572 ppc_md.tce_free = tce_free_pSeries;
573 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries;
574 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries;
578 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);