3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
5 * Copyright 2000-2001 MontaVista Software Inc.
6 * Completed implementation.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Frank Rowand <frank_rowand@mvista.com>
9 * Debbie Chu <debbie_chu@mvista.com>
10 * Further modifications by Armin Kuster
12 * Module name: ppc4xx_setup.c
16 #include <linux/init.h>
17 #include <linux/smp.h>
18 #include <linux/threads.h>
19 #include <linux/spinlock.h>
20 #include <linux/reboot.h>
21 #include <linux/param.h>
22 #include <linux/string.h>
23 #include <linux/initrd.h>
24 #include <linux/pci.h>
25 #include <linux/rtc.h>
26 #include <linux/console.h>
27 #include <linux/serial_reg.h>
28 #include <linux/seq_file.h>
30 #include <asm/system.h>
31 #include <asm/processor.h>
32 #include <asm/machdep.h>
35 #include <asm/ibm4xx.h>
38 #include <asm/ppc4xx_pic.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/bootinfo.h>
42 #include <syslib/gen550.h>
44 /* Function Prototypes */
45 extern void abort(void);
46 extern void ppc4xx_find_bridges(void);
48 /* Global Variables */
52 ppc4xx_setup_arch(void)
54 #if !defined(CONFIG_BDI_SWITCH)
56 * The Abatron BDI JTAG debugger does not tolerate others
57 * mucking with the debug registers.
59 mtspr(SPRN_DBCR0, (DBCR0_IDM));
60 mtspr(SPRN_DBSR, 0xffffffff);
63 /* Setup PCI host bridges */
65 ppc4xx_find_bridges();
70 * This routine pretty-prints the platform's internal CPU clock
71 * frequencies into the buffer for usage in /proc/cpuinfo.
75 ppc4xx_show_percpuinfo(struct seq_file *m, int i)
77 seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000);
83 * This routine pretty-prints the platform's internal bus clock
84 * frequencies into the buffer for usage in /proc/cpuinfo.
87 ppc4xx_show_cpuinfo(struct seq_file *m)
91 seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME);
92 seq_printf(m, "plb bus clock\t: %ldMHz\n",
93 (long) bip->bi_busfreq / 1000000);
95 seq_printf(m, "pci bus clock\t: %dMHz\n",
96 bip->bi_pci_busfreq / 1000000);
103 * Return the virtual address representing the top of physical RAM.
105 static unsigned long __init
106 ppc4xx_find_end_of_memory(void)
108 return ((unsigned long) __res.bi_memsize);
114 io_block_mapping(PPC4xx_ONB_IO_VADDR,
115 PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
117 io_block_mapping(PPC4xx_PCI_IO_VADDR,
118 PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO);
119 io_block_mapping(PPC4xx_PCI_CFG_VADDR,
120 PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO);
121 io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
122 PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
127 ppc4xx_init_IRQ(void)
133 ppc4xx_restart(char *cmd)
140 ppc4xx_power_off(void)
142 printk("System Halted\n");
150 printk("System Halted\n");
156 * This routine retrieves the internal processor frequency from the board
157 * information structure, sets up the kernel timer decrementer based on
158 * that value, enables the 4xx programmable interval timer (PIT) and sets
159 * it up for auto-reload.
162 ppc4xx_calibrate_decr(void)
167 #if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE)
168 /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
169 mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
171 freq = bip->bi_tbfreq;
172 tb_ticks_per_jiffy = freq / HZ;
173 tb_to_us = mulhwu_scale_factor(freq, 1000000);
175 /* Set the time base to zero.
176 ** At 200 Mhz, time base will rollover in ~2925 years.
182 /* Clear any pending timer interrupts */
184 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
185 mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
187 /* Set the PIT reload value and just let it run. */
188 mtspr(SPRN_PIT, tb_ticks_per_jiffy);
195 * r3 - Optional pointer to a board information structure.
196 * r4 - Optional pointer to the physical starting address of the init RAM
198 * r5 - Optional pointer to the physical ending address of the init RAM
200 * r6 - Optional pointer to the physical starting address of any kernel
201 * command-line parameters.
202 * r7 - Optional pointer to the physical ending address of any kernel
203 * command-line parameters.
206 ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
207 unsigned long r6, unsigned long r7)
209 parse_bootinfo(find_bootinfo());
212 * If we were passed in a board information, copy it into the
213 * residual data area.
216 __res = *(bd_t *)(r3 + KERNELBASE);
218 #if defined(CONFIG_BLK_DEV_INITRD)
220 * If the init RAM disk has been configured in, and there's a valid
221 * starting address for it, set it up.
224 initrd_start = r4 + KERNELBASE;
225 initrd_end = r5 + KERNELBASE;
227 #endif /* CONFIG_BLK_DEV_INITRD */
229 /* Copy the kernel command line arguments to a safe place. */
232 *(char *) (r7 + KERNELBASE) = 0;
233 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
236 /* Initialize machine-dependent vectors */
238 ppc_md.setup_arch = ppc4xx_setup_arch;
239 ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo;
240 ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo;
241 ppc_md.init_IRQ = ppc4xx_init_IRQ;
243 ppc_md.restart = ppc4xx_restart;
244 ppc_md.power_off = ppc4xx_power_off;
245 ppc_md.halt = ppc4xx_halt;
247 ppc_md.calibrate_decr = ppc4xx_calibrate_decr;
249 ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
250 ppc_md.setup_io_mappings = ppc4xx_map_io;
252 #ifdef CONFIG_SERIAL_TEXT_DEBUG
253 ppc_md.progress = gen550_progress;
257 /* Called from machine_check_exception */
258 void platform_machine_check(struct pt_regs *regs)
260 #if defined(DCRN_PLB0_BEAR)
261 printk("PLB0: BEAR= 0x%08x ACR= 0x%08x BESR= 0x%08x\n",
262 mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR),
263 mfdcr(DCRN_PLB0_BESR));
265 #if defined(DCRN_POB0_BEAR)
266 printk("PLB0 to OPB: BEAR= 0x%08x BESR0= 0x%08x BESR1= 0x%08x\n",
267 mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0),
268 mfdcr(DCRN_POB0_BESR1));