2 * Common routines for the Marvell/Galileo Discovery line of host bridges
3 * (gt64260, mv64360, mv64460, ...).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/string.h>
19 #include <linux/spinlock.h>
20 #include <linux/mv643xx.h>
21 #include <linux/platform_device.h>
23 #include <asm/byteorder.h>
26 #include <asm/uaccess.h>
27 #include <asm/machdep.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/delay.h>
30 #include <asm/mv64x60.h>
33 u8 mv64x60_pci_exclude_bridge = 1;
34 DEFINE_SPINLOCK(mv64x60_lock);
36 static phys_addr_t mv64x60_bridge_pbase;
37 static void __iomem *mv64x60_bridge_vbase;
38 static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
39 static u32 mv64x60_bridge_rev;
40 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
41 static struct pci_controller sysfs_hose_a;
44 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
45 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
46 static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
47 u32 window, u32 base);
48 static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
49 struct pci_controller *hose, u32 bus, u32 base);
50 static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
51 static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
52 static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
53 static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
54 static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
55 static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
56 struct mv64x60_setup_info *si);
57 static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
58 struct mv64x60_setup_info *si);
59 static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
60 struct mv64x60_setup_info *si);
62 static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
63 static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
64 static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
65 u32 window, u32 base);
66 static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
67 struct pci_controller *hose, u32 bus, u32 base);
68 static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
69 static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
70 static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
71 static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
72 static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
73 static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
74 struct mv64x60_setup_info *si);
75 static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
76 struct mv64x60_setup_info *si,
77 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
78 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
79 static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
80 struct mv64x60_setup_info *si);
81 static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
82 struct mv64x60_setup_info *si);
86 * Define tables that have the chip-specific info for each type of
87 * Marvell bridge chip.
89 static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
90 .translate_size = gt64260_translate_size,
91 .untranslate_size = gt64260_untranslate_size,
92 .set_pci2mem_window = gt64260_set_pci2mem_window,
93 .set_pci2regs_window = gt64260_set_pci2regs_window,
94 .is_enabled_32bit = gt64260_is_enabled_32bit,
95 .enable_window_32bit = gt64260_enable_window_32bit,
96 .disable_window_32bit = gt64260_disable_window_32bit,
97 .enable_window_64bit = gt64260_enable_window_64bit,
98 .disable_window_64bit = gt64260_disable_window_64bit,
99 .disable_all_windows = gt64260_disable_all_windows,
100 .chip_specific_init = gt64260a_chip_specific_init,
101 .window_tab_32bit = gt64260_32bit_windows,
102 .window_tab_64bit = gt64260_64bit_windows,
105 static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
106 .translate_size = gt64260_translate_size,
107 .untranslate_size = gt64260_untranslate_size,
108 .set_pci2mem_window = gt64260_set_pci2mem_window,
109 .set_pci2regs_window = gt64260_set_pci2regs_window,
110 .is_enabled_32bit = gt64260_is_enabled_32bit,
111 .enable_window_32bit = gt64260_enable_window_32bit,
112 .disable_window_32bit = gt64260_disable_window_32bit,
113 .enable_window_64bit = gt64260_enable_window_64bit,
114 .disable_window_64bit = gt64260_disable_window_64bit,
115 .disable_all_windows = gt64260_disable_all_windows,
116 .chip_specific_init = gt64260b_chip_specific_init,
117 .window_tab_32bit = gt64260_32bit_windows,
118 .window_tab_64bit = gt64260_64bit_windows,
121 static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
122 .translate_size = mv64360_translate_size,
123 .untranslate_size = mv64360_untranslate_size,
124 .set_pci2mem_window = mv64360_set_pci2mem_window,
125 .set_pci2regs_window = mv64360_set_pci2regs_window,
126 .is_enabled_32bit = mv64360_is_enabled_32bit,
127 .enable_window_32bit = mv64360_enable_window_32bit,
128 .disable_window_32bit = mv64360_disable_window_32bit,
129 .enable_window_64bit = mv64360_enable_window_64bit,
130 .disable_window_64bit = mv64360_disable_window_64bit,
131 .disable_all_windows = mv64360_disable_all_windows,
132 .config_io2mem_windows = mv64360_config_io2mem_windows,
133 .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
134 .chip_specific_init = mv64360_chip_specific_init,
135 .window_tab_32bit = mv64360_32bit_windows,
136 .window_tab_64bit = mv64360_64bit_windows,
139 static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
140 .translate_size = mv64360_translate_size,
141 .untranslate_size = mv64360_untranslate_size,
142 .set_pci2mem_window = mv64360_set_pci2mem_window,
143 .set_pci2regs_window = mv64360_set_pci2regs_window,
144 .is_enabled_32bit = mv64360_is_enabled_32bit,
145 .enable_window_32bit = mv64360_enable_window_32bit,
146 .disable_window_32bit = mv64360_disable_window_32bit,
147 .enable_window_64bit = mv64360_enable_window_64bit,
148 .disable_window_64bit = mv64360_disable_window_64bit,
149 .disable_all_windows = mv64360_disable_all_windows,
150 .config_io2mem_windows = mv64360_config_io2mem_windows,
151 .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
152 .chip_specific_init = mv64460_chip_specific_init,
153 .window_tab_32bit = mv64360_32bit_windows,
154 .window_tab_64bit = mv64360_64bit_windows,
158 *****************************************************************************
160 * Platform Device Definitions
162 *****************************************************************************
164 #ifdef CONFIG_SERIAL_MPSC
165 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
166 .mrr_val = 0x3ffffe38,
173 static struct resource mv64x60_mpsc_shared_resources[] = {
174 /* Do not change the order of the IORESOURCE_MEM resources */
176 .name = "mpsc routing base",
177 .start = MV64x60_MPSC_ROUTING_OFFSET,
178 .end = MV64x60_MPSC_ROUTING_OFFSET +
179 MPSC_ROUTING_REG_BLOCK_SIZE - 1,
180 .flags = IORESOURCE_MEM,
183 .name = "sdma intr base",
184 .start = MV64x60_SDMA_INTR_OFFSET,
185 .end = MV64x60_SDMA_INTR_OFFSET +
186 MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
187 .flags = IORESOURCE_MEM,
191 static struct platform_device mpsc_shared_device = { /* Shared device */
192 .name = MPSC_SHARED_NAME,
194 .num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
195 .resource = mv64x60_mpsc_shared_resources,
197 .platform_data = &mv64x60_mpsc_shared_pdata,
201 static struct mpsc_pdata mv64x60_mpsc0_pdata = {
205 .default_baud = 9600,
207 .default_parity = 'n',
209 .chr_1_val = 0x00000000,
210 .chr_2_val = 0x00000000,
211 .chr_10_val = 0x00000003,
215 .brg_clk_src = 8, /* Default to TCLK */
216 .brg_clk_freq = 100000000, /* Default to 100 MHz */
219 static struct resource mv64x60_mpsc0_resources[] = {
220 /* Do not change the order of the IORESOURCE_MEM resources */
222 .name = "mpsc 0 base",
223 .start = MV64x60_MPSC_0_OFFSET,
224 .end = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
225 .flags = IORESOURCE_MEM,
228 .name = "sdma 0 base",
229 .start = MV64x60_SDMA_0_OFFSET,
230 .end = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
231 .flags = IORESOURCE_MEM,
234 .name = "brg 0 base",
235 .start = MV64x60_BRG_0_OFFSET,
236 .end = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
237 .flags = IORESOURCE_MEM,
240 .name = "sdma 0 irq",
241 .start = MV64x60_IRQ_SDMA_0,
242 .end = MV64x60_IRQ_SDMA_0,
243 .flags = IORESOURCE_IRQ,
247 static struct platform_device mpsc0_device = {
248 .name = MPSC_CTLR_NAME,
250 .num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources),
251 .resource = mv64x60_mpsc0_resources,
253 .platform_data = &mv64x60_mpsc0_pdata,
257 static struct mpsc_pdata mv64x60_mpsc1_pdata = {
261 .default_baud = 9600,
263 .default_parity = 'n',
265 .chr_1_val = 0x00000000,
266 .chr_1_val = 0x00000000,
267 .chr_2_val = 0x00000000,
268 .chr_10_val = 0x00000003,
272 .brg_clk_src = 8, /* Default to TCLK */
273 .brg_clk_freq = 100000000, /* Default to 100 MHz */
276 static struct resource mv64x60_mpsc1_resources[] = {
277 /* Do not change the order of the IORESOURCE_MEM resources */
279 .name = "mpsc 1 base",
280 .start = MV64x60_MPSC_1_OFFSET,
281 .end = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
282 .flags = IORESOURCE_MEM,
285 .name = "sdma 1 base",
286 .start = MV64x60_SDMA_1_OFFSET,
287 .end = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
288 .flags = IORESOURCE_MEM,
291 .name = "brg 1 base",
292 .start = MV64x60_BRG_1_OFFSET,
293 .end = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
294 .flags = IORESOURCE_MEM,
297 .name = "sdma 1 irq",
298 .start = MV64360_IRQ_SDMA_1,
299 .end = MV64360_IRQ_SDMA_1,
300 .flags = IORESOURCE_IRQ,
304 static struct platform_device mpsc1_device = {
305 .name = MPSC_CTLR_NAME,
307 .num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources),
308 .resource = mv64x60_mpsc1_resources,
310 .platform_data = &mv64x60_mpsc1_pdata,
315 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
316 static struct resource mv64x60_eth_shared_resources[] = {
318 .name = "ethernet shared base",
319 .start = MV643XX_ETH_SHARED_REGS,
320 .end = MV643XX_ETH_SHARED_REGS +
321 MV643XX_ETH_SHARED_REGS_SIZE - 1,
322 .flags = IORESOURCE_MEM,
326 static struct platform_device mv64x60_eth_shared_device = {
327 .name = MV643XX_ETH_SHARED_NAME,
329 .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources),
330 .resource = mv64x60_eth_shared_resources,
333 #ifdef CONFIG_MV643XX_ETH_0
334 static struct resource mv64x60_eth0_resources[] = {
337 .start = MV64x60_IRQ_ETH_0,
338 .end = MV64x60_IRQ_ETH_0,
339 .flags = IORESOURCE_IRQ,
343 static struct mv643xx_eth_platform_data eth0_pd = {
347 static struct platform_device eth0_device = {
348 .name = MV643XX_ETH_NAME,
350 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
351 .resource = mv64x60_eth0_resources,
353 .platform_data = ð0_pd,
358 #ifdef CONFIG_MV643XX_ETH_1
359 static struct resource mv64x60_eth1_resources[] = {
362 .start = MV64x60_IRQ_ETH_1,
363 .end = MV64x60_IRQ_ETH_1,
364 .flags = IORESOURCE_IRQ,
368 static struct mv643xx_eth_platform_data eth1_pd = {
372 static struct platform_device eth1_device = {
373 .name = MV643XX_ETH_NAME,
375 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
376 .resource = mv64x60_eth1_resources,
378 .platform_data = ð1_pd,
383 #ifdef CONFIG_MV643XX_ETH_2
384 static struct resource mv64x60_eth2_resources[] = {
387 .start = MV64x60_IRQ_ETH_2,
388 .end = MV64x60_IRQ_ETH_2,
389 .flags = IORESOURCE_IRQ,
393 static struct mv643xx_eth_platform_data eth2_pd = {
397 static struct platform_device eth2_device = {
398 .name = MV643XX_ETH_NAME,
400 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
401 .resource = mv64x60_eth2_resources,
403 .platform_data = ð2_pd,
409 #ifdef CONFIG_I2C_MV64XXX
410 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
413 .timeout = 1000, /* Default timeout of 1 second */
417 static struct resource mv64xxx_i2c_resources[] = {
418 /* Do not change the order of the IORESOURCE_MEM resources */
420 .name = "mv64xxx i2c base",
421 .start = MV64XXX_I2C_OFFSET,
422 .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
423 .flags = IORESOURCE_MEM,
426 .name = "mv64xxx i2c irq",
427 .start = MV64x60_IRQ_I2C,
428 .end = MV64x60_IRQ_I2C,
429 .flags = IORESOURCE_IRQ,
433 static struct platform_device i2c_device = {
434 .name = MV64XXX_I2C_CTLR_NAME,
436 .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources),
437 .resource = mv64xxx_i2c_resources,
439 .platform_data = &mv64xxx_i2c_pdata,
444 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
445 static struct mv64xxx_pdata mv64xxx_pdata = {
449 static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
450 .name = MV64XXX_DEV_NAME,
453 .platform_data = &mv64xxx_pdata,
458 static struct platform_device *mv64x60_pd_devs[] __initdata = {
459 #ifdef CONFIG_SERIAL_MPSC
464 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
465 &mv64x60_eth_shared_device,
467 #ifdef CONFIG_MV643XX_ETH_0
470 #ifdef CONFIG_MV643XX_ETH_1
473 #ifdef CONFIG_MV643XX_ETH_2
476 #ifdef CONFIG_I2C_MV64XXX
479 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
485 *****************************************************************************
487 * Bridge Initialization Routines
489 *****************************************************************************
494 * Initialize the bridge based on setting passed in via 'si'. The bridge
495 * handle, 'bh', will be set so that it can be used to make subsequent
496 * calls to routines in this file.
499 mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
501 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
504 ppc_md.progress("mv64x60 initialization", 0x0);
506 spin_lock_init(&mv64x60_lock);
507 mv64x60_early_init(bh, si);
509 if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
513 ppc_md.progress("mv64x60_init: Can't determine chip",0);
517 bh->ci->disable_all_windows(bh, si);
518 mv64x60_get_mem_windows(bh, mem_windows);
519 mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
521 if (bh->ci->config_io2mem_windows)
522 bh->ci->config_io2mem_windows(bh, si, mem_windows);
523 if (bh->ci->set_mpsc2regs_window)
524 bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
526 if (si->pci_1.enable_bus) {
527 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
528 si->pci_1.pci_io.size);
529 isa_io_base = bh->io_base_b;
532 if (si->pci_0.enable_bus) {
533 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
534 si->pci_0.pci_io.size);
535 isa_io_base = bh->io_base_a;
537 mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
538 MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
539 mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
540 mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
542 mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
543 mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
545 bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
549 if (si->pci_1.enable_bus) {
550 mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
551 MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
552 mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
553 mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
555 mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
556 mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
558 bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
562 bh->ci->chip_specific_init(bh, si);
563 mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
569 * mv64x60_early_init()
571 * Do some bridge work that must take place before we start messing with
572 * the bridge for real.
575 mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
577 struct pci_controller hose_a, hose_b;
579 memset(bh, 0, sizeof(*bh));
581 bh->p_base = si->phys_reg_base;
582 bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
584 mv64x60_bridge_pbase = bh->p_base;
585 mv64x60_bridge_vbase = bh->v_base;
587 /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
588 bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
589 MV64x60_PCIMODE_MASK;
590 bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
591 MV64x60_PCIMODE_MASK;
593 /* Need temporary hose structs to call mv64x60_set_bus() */
594 memset(&hose_a, 0, sizeof(hose_a));
595 memset(&hose_b, 0, sizeof(hose_b));
596 setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
597 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
598 setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
599 bh->v_base + MV64x60_PCI1_CONFIG_DATA);
600 bh->hose_a = &hose_a;
601 bh->hose_b = &hose_b;
603 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
604 /* Save a copy of hose_a for sysfs functions -- hack */
605 memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a));
608 mv64x60_set_bus(bh, 0, 0);
609 mv64x60_set_bus(bh, 1, 0);
614 /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
615 mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
616 mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
618 /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
619 mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
620 mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
622 mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
623 mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
627 *****************************************************************************
629 * Window Config Routines
631 *****************************************************************************
634 * mv64x60_get_32bit_window()
636 * Determine the base address and size of a 32-bit window on the bridge.
639 mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
640 u32 *base, u32 *size)
642 u32 val, base_reg, size_reg, base_bits, size_bits;
643 u32 (*get_from_field)(u32 val, u32 num_bits);
645 base_reg = bh->ci->window_tab_32bit[window].base_reg;
648 size_reg = bh->ci->window_tab_32bit[window].size_reg;
649 base_bits = bh->ci->window_tab_32bit[window].base_bits;
650 size_bits = bh->ci->window_tab_32bit[window].size_bits;
651 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
653 val = mv64x60_read(bh, base_reg);
654 *base = get_from_field(val, base_bits);
657 val = mv64x60_read(bh, size_reg);
658 val = get_from_field(val, size_bits);
659 *size = bh->ci->untranslate_size(*base, val, size_bits);
667 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
668 window, *base, *size);
672 * mv64x60_set_32bit_window()
674 * Set the base address and size of a 32-bit window on the bridge.
677 mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
678 u32 base, u32 size, u32 other_bits)
680 u32 val, base_reg, size_reg, base_bits, size_bits;
681 u32 (*map_to_field)(u32 val, u32 num_bits);
683 pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
684 window, base, size, other_bits);
686 base_reg = bh->ci->window_tab_32bit[window].base_reg;
689 size_reg = bh->ci->window_tab_32bit[window].size_reg;
690 base_bits = bh->ci->window_tab_32bit[window].base_bits;
691 size_bits = bh->ci->window_tab_32bit[window].size_bits;
692 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
694 val = map_to_field(base, base_bits) | other_bits;
695 mv64x60_write(bh, base_reg, val);
698 val = bh->ci->translate_size(base, size, size_bits);
699 val = map_to_field(val, size_bits);
700 mv64x60_write(bh, size_reg, val);
703 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
708 * mv64x60_get_64bit_window()
710 * Determine the base address and size of a 64-bit window on the bridge.
713 mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
714 u32 *base_hi, u32 *base_lo, u32 *size)
716 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
717 u32 (*get_from_field)(u32 val, u32 num_bits);
719 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
721 if (base_lo_reg != 0) {
722 size_reg = bh->ci->window_tab_64bit[window].size_reg;
723 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
724 size_bits = bh->ci->window_tab_64bit[window].size_bits;
725 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
727 *base_hi = mv64x60_read(bh,
728 bh->ci->window_tab_64bit[window].base_hi_reg);
730 val = mv64x60_read(bh, base_lo_reg);
731 *base_lo = get_from_field(val, base_lo_bits);
734 val = mv64x60_read(bh, size_reg);
735 val = get_from_field(val, size_bits);
736 *size = bh->ci->untranslate_size(*base_lo, val,
746 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
747 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
751 * mv64x60_set_64bit_window()
753 * Set the base address and size of a 64-bit window on the bridge.
756 mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
757 u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
759 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
760 u32 (*map_to_field)(u32 val, u32 num_bits);
762 pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
763 "size: 0x%x, other: 0x%x\n",
764 window, base_hi, base_lo, size, other_bits);
766 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
768 if (base_lo_reg != 0) {
769 size_reg = bh->ci->window_tab_64bit[window].size_reg;
770 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
771 size_bits = bh->ci->window_tab_64bit[window].size_bits;
772 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
774 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
777 val = map_to_field(base_lo, base_lo_bits) | other_bits;
778 mv64x60_write(bh, base_lo_reg, val);
781 val = bh->ci->translate_size(base_lo, size, size_bits);
782 val = map_to_field(val, size_bits);
783 mv64x60_write(bh, size_reg, val);
786 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
793 * Take the high-order 'num_bits' of 'val' & mask off low bits.
796 mv64x60_mask(u32 val, u32 num_bits)
798 return val & (0xffffffff << (32 - num_bits));
802 * mv64x60_shift_left()
804 * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
807 mv64x60_shift_left(u32 val, u32 num_bits)
809 return val << (32 - num_bits);
813 * mv64x60_shift_right()
815 * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
818 mv64x60_shift_right(u32 val, u32 num_bits)
820 return val >> (32 - num_bits);
824 *****************************************************************************
826 * Chip Identification Routines
828 *****************************************************************************
833 * Determine the type of bridge chip we have.
836 mv64x60_get_type(struct mv64x60_handle *bh)
838 struct pci_controller hose;
842 memset(&hose, 0, sizeof(hose));
843 setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
844 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
846 save_exclude = mv64x60_pci_exclude_bridge;
847 mv64x60_pci_exclude_bridge = 0;
848 /* Sanity check of bridge's Vendor ID */
849 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
851 if (val != PCI_VENDOR_ID_MARVELL) {
852 mv64x60_pci_exclude_bridge = save_exclude;
856 /* Get the revision of the chip */
857 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
859 bh->rev = (u32)(val & 0xff);
861 /* Figure out the type of Marvell bridge it is */
862 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
863 mv64x60_pci_exclude_bridge = save_exclude;
866 case PCI_DEVICE_ID_MARVELL_GT64260:
869 bh->type = MV64x60_TYPE_GT64260A;
873 printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
875 /* Assume its similar to a 'B' rev and fallthru */
877 bh->type = MV64x60_TYPE_GT64260B;
882 case PCI_DEVICE_ID_MARVELL_MV64360:
883 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
884 bh->type = MV64x60_TYPE_MV64360;
887 case PCI_DEVICE_ID_MARVELL_MV64460:
888 bh->type = MV64x60_TYPE_MV64460;
892 printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
896 /* Hang onto bridge type & rev for PIC code */
897 mv64x60_bridge_type = bh->type;
898 mv64x60_bridge_rev = bh->rev;
904 * mv64x60_setup_for_chip()
906 * Set 'bh' to use the proper set of routine for the bridge chip that we have.
909 mv64x60_setup_for_chip(struct mv64x60_handle *bh)
913 /* Set up chip-specific info based on the chip/bridge type */
915 case MV64x60_TYPE_GT64260A:
916 bh->ci = >64260a_ci;
919 case MV64x60_TYPE_GT64260B:
920 bh->ci = >64260b_ci;
923 case MV64x60_TYPE_MV64360:
924 bh->ci = &mv64360_ci;
927 case MV64x60_TYPE_MV64460:
928 bh->ci = &mv64460_ci;
931 case MV64x60_TYPE_INVALID:
934 ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
935 printk(KERN_ERR "mv64x60: Unsupported bridge\n");
943 * mv64x60_get_bridge_vbase()
945 * Return the virtual address of the bridge's registers.
948 mv64x60_get_bridge_vbase(void)
950 return mv64x60_bridge_vbase;
954 * mv64x60_get_bridge_type()
956 * Return the type of bridge on the platform.
959 mv64x60_get_bridge_type(void)
961 return mv64x60_bridge_type;
965 * mv64x60_get_bridge_rev()
967 * Return the revision of the bridge on the platform.
970 mv64x60_get_bridge_rev(void)
972 return mv64x60_bridge_rev;
976 *****************************************************************************
978 * System Memory Window Related Routines
980 *****************************************************************************
983 * mv64x60_get_mem_size()
985 * Calculate the amount of memory that the memory controller is set up for.
986 * This should only be used by board-specific code if there is no other
987 * way to determine the amount of memory in the system.
990 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
992 struct mv64x60_handle bh;
993 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
996 memset(&bh, 0, sizeof(bh));
999 bh.v_base = (void *)bridge_base;
1001 if (!mv64x60_setup_for_chip(&bh)) {
1002 mv64x60_get_mem_windows(&bh, mem_windows);
1003 rc = mv64x60_calc_mem_size(&bh, mem_windows);
1010 * mv64x60_get_mem_windows()
1012 * Get the values in the memory controller & return in the 'mem_windows' array.
1015 mv64x60_get_mem_windows(struct mv64x60_handle *bh,
1016 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1020 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1021 if (bh->ci->is_enabled_32bit(bh, win))
1022 mv64x60_get_32bit_window(bh, win,
1023 &mem_windows[i][0], &mem_windows[i][1]);
1025 mem_windows[i][0] = 0;
1026 mem_windows[i][1] = 0;
1031 * mv64x60_calc_mem_size()
1033 * Using the memory controller register values in 'mem_windows', determine
1034 * how much memory it is set up for.
1037 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
1038 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1042 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
1043 total += mem_windows[i][1];
1049 *****************************************************************************
1051 * CPU->System MEM, PCI Config Routines
1053 *****************************************************************************
1056 * mv64x60_config_cpu2mem_windows()
1058 * Configure CPU->Memory windows on the bridge.
1060 static u32 prot_tab[] __initdata = {
1061 MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1062 MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
1065 static u32 cpu_snoop_tab[] __initdata = {
1066 MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1067 MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
1071 mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1072 struct mv64x60_setup_info *si,
1073 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1077 /* Set CPU protection & snoop windows */
1078 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1079 if (bh->ci->is_enabled_32bit(bh, win)) {
1080 mv64x60_set_32bit_window(bh, prot_tab[i],
1081 mem_windows[i][0], mem_windows[i][1],
1082 si->cpu_prot_options[i]);
1083 bh->ci->enable_window_32bit(bh, prot_tab[i]);
1085 if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
1087 mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
1088 mem_windows[i][0], mem_windows[i][1],
1089 si->cpu_snoop_options[i]);
1090 bh->ci->enable_window_32bit(bh,
1098 * mv64x60_config_cpu2pci_windows()
1100 * Configure the CPU->PCI windows for one of the PCI buses.
1102 static u32 win_tab[2][4] __initdata = {
1103 { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
1104 MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
1105 { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
1106 MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
1109 static u32 remap_tab[2][4] __initdata = {
1110 { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1111 MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
1112 { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1113 MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
1117 mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1118 struct mv64x60_pci_info *pi, u32 bus)
1122 if (pi->pci_io.size > 0) {
1123 mv64x60_set_32bit_window(bh, win_tab[bus][0],
1124 pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
1125 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1126 pi->pci_io.pci_base_lo, 0, 0);
1127 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1128 } else /* Actually, the window should already be disabled */
1129 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1132 if (pi->pci_mem[i].size > 0) {
1133 mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
1134 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1135 pi->pci_mem[i].swap);
1136 mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
1137 pi->pci_mem[i].pci_base_hi,
1138 pi->pci_mem[i].pci_base_lo, 0, 0);
1139 bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1140 } else /* Actually, the window should already be disabled */
1141 bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1145 *****************************************************************************
1147 * PCI->System MEM Config Routines
1149 *****************************************************************************
1152 * mv64x60_config_pci2mem_windows()
1154 * Configure the PCI->Memory windows on the bridge.
1156 static u32 pci_acc_tab[2][4] __initdata = {
1157 { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1158 MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
1159 { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1160 MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
1163 static u32 pci_snoop_tab[2][4] __initdata = {
1164 { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
1165 MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
1166 { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
1167 MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
1170 static u32 pci_size_tab[2][4] __initdata = {
1171 { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1172 MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
1173 { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1174 MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
1178 mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1179 struct pci_controller *hose, struct mv64x60_pci_info *pi,
1180 u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1185 * Set the access control, snoop, BAR size, and window base addresses.
1186 * PCI->MEM windows base addresses will match exactly what the
1187 * CPU->MEM windows are.
1189 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1190 if (bh->ci->is_enabled_32bit(bh, win)) {
1191 mv64x60_set_64bit_window(bh,
1192 pci_acc_tab[bus][i], 0,
1193 mem_windows[i][0], mem_windows[i][1],
1194 pi->acc_cntl_options[i]);
1195 bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
1197 if (bh->ci->window_tab_64bit[
1198 pci_snoop_tab[bus][i]].base_lo_reg != 0) {
1200 mv64x60_set_64bit_window(bh,
1201 pci_snoop_tab[bus][i], 0,
1202 mem_windows[i][0], mem_windows[i][1],
1203 pi->snoop_options[i]);
1204 bh->ci->enable_window_64bit(bh,
1205 pci_snoop_tab[bus][i]);
1208 bh->ci->set_pci2mem_window(hose, bus, i,
1210 mv64x60_write(bh, pci_size_tab[bus][i],
1211 mv64x60_mask(mem_windows[i][1] - 1, 20));
1213 /* Enable the window */
1214 mv64x60_clr_bits(bh, ((bus == 0) ?
1215 MV64x60_PCI0_BAR_ENABLE :
1216 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1221 *****************************************************************************
1223 * Hose & Resource Alloc/Init Routines
1225 *****************************************************************************
1228 * mv64x60_alloc_hoses()
1230 * Allocate the PCI hose structures for the bridge's PCI buses.
1233 mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1234 struct pci_controller **hose)
1236 *hose = pcibios_alloc_controller();
1237 setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1238 bh->v_base + cfg_data);
1242 * mv64x60_config_resources()
1244 * Calculate the offsets, etc. for the hose structures to reflect all of
1245 * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1248 mv64x60_config_resources(struct pci_controller *hose,
1249 struct mv64x60_pci_info *pi, u32 io_base)
1252 /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1253 static char s[2][4][64];
1255 if (pi->pci_io.size != 0) {
1256 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
1258 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
1259 io_base - isa_io_base + pi->pci_io.size - 1,
1260 IORESOURCE_IO, s[hose->index][0]);
1261 hose->io_space.start = pi->pci_io.pci_base_lo;
1262 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
1263 hose->io_base_phys = pi->pci_io.cpu_base;
1264 hose->io_base_virt = (void *)isa_io_base;
1268 if (pi->pci_mem[i].size != 0) {
1269 sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
1271 pci_init_resource(&hose->mem_resources[i],
1272 pi->pci_mem[i].cpu_base,
1273 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
1274 IORESOURCE_MEM, s[hose->index][i+1]);
1277 hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
1278 pi->pci_mem[0].size - 1;
1279 hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1280 pi->pci_mem[0].pci_base_lo;
1284 * mv64x60_config_pci_params()
1286 * Configure a hose's PCI config space parameters.
1289 mv64x60_config_pci_params(struct pci_controller *hose,
1290 struct mv64x60_pci_info *pi)
1296 devfn = PCI_DEVFN(0,0);
1298 save_exclude = mv64x60_pci_exclude_bridge;
1299 mv64x60_pci_exclude_bridge = 0;
1301 /* Set class code to indicate host bridge */
1302 u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
1303 early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
1305 /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1306 early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
1307 u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
1308 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
1309 u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1310 early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
1312 /* Set latency timer, cache line size, clear BIST */
1313 u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2);
1314 early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1316 mv64x60_pci_exclude_bridge = save_exclude;
1320 *****************************************************************************
1322 * PCI Related Routine
1324 *****************************************************************************
1329 * Set the bus number for the hose directly under the bridge.
1332 mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1334 struct pci_controller *hose;
1335 u32 pci_mode, p2p_cfg, pci_cfg_offset, val;
1339 pci_mode = bh->pci_mode_a;
1340 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1341 pci_cfg_offset = 0x64;
1344 pci_mode = bh->pci_mode_b;
1345 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1346 pci_cfg_offset = 0xe4;
1351 val = mv64x60_read(bh, p2p_cfg);
1353 if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
1354 val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1355 val |= (child_bus << 16) | 0xff;
1356 mv64x60_write(bh, p2p_cfg, val);
1357 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1358 } else { /* PCI-X */
1360 * Need to use the current bus/dev number (that's in the
1361 * P2P CONFIG reg) to access the bridge's pci config space.
1363 save_exclude = mv64x60_pci_exclude_bridge;
1364 mv64x60_pci_exclude_bridge = 0;
1365 early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
1366 PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
1367 pci_cfg_offset, child_bus << 8);
1368 mv64x60_pci_exclude_bridge = save_exclude;
1373 * mv64x60_pci_exclude_device()
1375 * This routine is used to make the bridge not appear when the
1376 * PCI subsystem is accessing PCI devices (in PCI config space).
1379 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
1381 struct pci_controller *hose;
1383 hose = pci_bus_to_hose(bus);
1385 /* Skip slot 0 on both hoses */
1386 if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
1387 (hose->first_busno == bus))
1389 return PCIBIOS_DEVICE_NOT_FOUND;
1391 return PCIBIOS_SUCCESSFUL;
1392 } /* mv64x60_pci_exclude_device() */
1395 *****************************************************************************
1397 * Platform Device Routines
1399 *****************************************************************************
1403 * mv64x60_pd_fixup()
1405 * Need to add the base addr of where the bridge's regs are mapped in the
1406 * physical addr space so drivers can ioremap() them.
1409 mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1415 for (i=0; i<entries; i++) {
1418 while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
1421 r->start += bh->p_base;
1422 r->end += bh->p_base;
1431 * Add the mv64x60 platform devices to the list of platform devices.
1434 mv64x60_add_pds(void)
1436 return platform_add_devices(mv64x60_pd_devs,
1437 ARRAY_SIZE(mv64x60_pd_devs));
1439 arch_initcall(mv64x60_add_pds);
1442 *****************************************************************************
1444 * GT64260-Specific Routines
1446 *****************************************************************************
1449 * gt64260_translate_size()
1451 * On the GT64260, the size register is really the "top" address of the window.
1454 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
1456 return base + mv64x60_mask(size - 1, num_bits);
1460 * gt64260_untranslate_size()
1462 * Translate the top address of a window into a window size.
1465 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
1468 size = size - base + (1 << (32 - num_bits));
1476 * gt64260_set_pci2mem_window()
1478 * The PCI->MEM window registers are actually in PCI config space so need
1479 * to set them by setting the correct config space BARs.
1481 static u32 gt64260_reg_addrs[2][4] __initdata = {
1482 { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1486 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1491 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1494 save_exclude = mv64x60_pci_exclude_bridge;
1495 mv64x60_pci_exclude_bridge = 0;
1496 early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1497 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1498 mv64x60_pci_exclude_bridge = save_exclude;
1502 * gt64260_set_pci2regs_window()
1504 * Set where the bridge's registers appear in PCI MEM space.
1506 static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
1509 gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1510 struct pci_controller *hose, u32 bus, u32 base)
1514 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1517 save_exclude = mv64x60_pci_exclude_bridge;
1518 mv64x60_pci_exclude_bridge = 0;
1519 early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1521 mv64x60_pci_exclude_bridge = save_exclude;
1525 * gt64260_is_enabled_32bit()
1527 * On a GT64260, a window is enabled iff its top address is >= to its base
1531 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1535 if ((gt64260_32bit_windows[window].base_reg != 0) &&
1536 (gt64260_32bit_windows[window].size_reg != 0) &&
1537 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
1538 ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
1539 (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
1540 ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
1548 * gt64260_enable_window_32bit()
1550 * On the GT64260, a window is enabled iff the top address is >= to the base
1551 * address of the window. Since the window has already been configured by
1552 * the time this routine is called, we have nothing to do here.
1555 gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1557 pr_debug("enable 32bit window: %d\n", window);
1561 * gt64260_disable_window_32bit()
1563 * On a GT64260, you disable a window by setting its top address to be less
1564 * than its base address.
1567 gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1569 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1570 window, gt64260_32bit_windows[window].base_reg,
1571 gt64260_32bit_windows[window].size_reg);
1573 if ((gt64260_32bit_windows[window].base_reg != 0) &&
1574 (gt64260_32bit_windows[window].size_reg != 0)) {
1576 /* To disable, make bottom reg higher than top reg */
1577 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1578 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1583 * gt64260_enable_window_64bit()
1585 * On the GT64260, a window is enabled iff the top address is >= to the base
1586 * address of the window. Since the window has already been configured by
1587 * the time this routine is called, we have nothing to do here.
1590 gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1592 pr_debug("enable 64bit window: %d\n", window);
1596 * gt64260_disable_window_64bit()
1598 * On a GT64260, you disable a window by setting its top address to be less
1599 * than its base address.
1602 gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1604 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1605 window, gt64260_64bit_windows[window].base_lo_reg,
1606 gt64260_64bit_windows[window].size_reg);
1608 if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
1609 (gt64260_64bit_windows[window].size_reg != 0)) {
1611 /* To disable, make bottom reg higher than top reg */
1612 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
1614 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1615 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1620 * gt64260_disable_all_windows()
1622 * The GT64260 has several windows that aren't represented in the table of
1623 * windows at the top of this file. This routine turns all of them off
1624 * except for the memory controller windows, of course.
1627 gt64260_disable_all_windows(struct mv64x60_handle *bh,
1628 struct mv64x60_setup_info *si)
1632 /* Disable 32bit windows (don't disable cpu->mem windows) */
1633 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
1635 preserve = si->window_preserve_mask_32_lo & (1 << i);
1637 preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
1640 gt64260_disable_window_32bit(bh, i);
1643 /* Disable 64bit windows */
1644 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
1645 if (!(si->window_preserve_mask_64 & (1<<i)))
1646 gt64260_disable_window_64bit(bh, i);
1648 /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1649 mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
1650 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
1651 mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
1652 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
1653 mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
1654 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
1655 mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
1656 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
1658 /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1659 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
1660 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
1661 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
1662 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
1663 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
1664 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
1665 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
1666 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
1667 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
1668 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
1669 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
1670 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
1672 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
1673 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
1674 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
1675 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
1676 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
1677 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
1678 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
1679 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
1680 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
1681 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
1682 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
1683 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
1685 /* Disable all PCI-><whatever> windows */
1686 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
1687 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
1690 * Some firmwares enable a bunch of intr sources
1691 * for the PCI INT output pins.
1693 mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
1694 mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
1695 mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
1696 mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
1697 mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
1698 mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
1699 mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
1700 mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1701 mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1702 mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1706 * gt64260a_chip_specific_init()
1708 * Implement errata workarounds for the GT64260A.
1711 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1712 struct mv64x60_setup_info *si)
1714 #ifdef CONFIG_SERIAL_MPSC
1717 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1722 if (si->pci_0.enable_bus)
1723 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1724 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1726 if (si->pci_1.enable_bus)
1727 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1728 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1731 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1732 * be set if you are using cache coherency.
1734 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1735 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1736 if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1737 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1739 save_exclude = mv64x60_pci_exclude_bridge;
1740 mv64x60_pci_exclude_bridge = 0;
1741 if (si->pci_0.enable_bus) {
1742 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1744 val |= PCI_COMMAND_INVALIDATE;
1745 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1749 if (si->pci_1.enable_bus) {
1750 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1752 val |= PCI_COMMAND_INVALIDATE;
1753 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1756 mv64x60_pci_exclude_bridge = save_exclude;
1759 /* Disable buffer/descriptor snooping */
1760 mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1761 mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1763 #ifdef CONFIG_SERIAL_MPSC
1764 mv64x60_mpsc0_pdata.mirror_regs = 1;
1765 mv64x60_mpsc0_pdata.cache_mgmt = 1;
1766 mv64x60_mpsc1_pdata.mirror_regs = 1;
1767 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1769 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1771 r->start = MV64x60_IRQ_SDMA_0;
1772 r->end = MV64x60_IRQ_SDMA_0;
1778 * gt64260b_chip_specific_init()
1780 * Implement errata workarounds for the GT64260B.
1783 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1784 struct mv64x60_setup_info *si)
1786 #ifdef CONFIG_SERIAL_MPSC
1789 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1794 if (si->pci_0.enable_bus)
1795 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1796 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1798 if (si->pci_1.enable_bus)
1799 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1800 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1803 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1804 * be set if you are using cache coherency.
1806 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1807 mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
1809 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1810 if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1811 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1813 save_exclude = mv64x60_pci_exclude_bridge;
1814 mv64x60_pci_exclude_bridge = 0;
1815 if (si->pci_0.enable_bus) {
1816 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1818 val |= PCI_COMMAND_INVALIDATE;
1819 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1823 if (si->pci_1.enable_bus) {
1824 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1826 val |= PCI_COMMAND_INVALIDATE;
1827 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1830 mv64x60_pci_exclude_bridge = save_exclude;
1833 /* Disable buffer/descriptor snooping */
1834 mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1835 mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1837 #ifdef CONFIG_SERIAL_MPSC
1839 * The 64260B is not supposed to have the bug where the MPSC & ENET
1840 * can't access cache coherent regions. However, testing has shown
1841 * that the MPSC, at least, still has this bug.
1843 mv64x60_mpsc0_pdata.cache_mgmt = 1;
1844 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1846 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1848 r->start = MV64x60_IRQ_SDMA_0;
1849 r->end = MV64x60_IRQ_SDMA_0;
1855 *****************************************************************************
1857 * MV64360-Specific Routines
1859 *****************************************************************************
1862 * mv64360_translate_size()
1864 * On the MV64360, the size register is set similar to the size you get
1865 * from a pci config space BAR register. That is, programmed from LSB to MSB
1866 * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1867 * assumption that the size is a power of 2.
1870 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
1872 return mv64x60_mask(size - 1, num_bits);
1876 * mv64360_untranslate_size()
1878 * Translate the size register value of a window into a window size.
1881 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
1884 size >>= (32 - num_bits);
1886 size <<= (32 - num_bits);
1893 * mv64360_set_pci2mem_window()
1895 * The PCI->MEM window registers are actually in PCI config space so need
1896 * to set them by setting the correct config space BARs.
1902 } static mv64360_reg_addrs[2][4] __initdata = {
1903 {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1904 { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1905 {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1906 { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1910 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1915 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1918 save_exclude = mv64x60_pci_exclude_bridge;
1919 mv64x60_pci_exclude_bridge = 0;
1920 early_write_config_dword(hose, 0,
1921 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1922 mv64360_reg_addrs[bus][window].base_hi_bar, 0);
1923 early_write_config_dword(hose, 0,
1924 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1925 mv64360_reg_addrs[bus][window].base_lo_bar,
1926 mv64x60_mask(base,20) | 0xc);
1927 mv64x60_pci_exclude_bridge = save_exclude;
1931 * mv64360_set_pci2regs_window()
1933 * Set where the bridge's registers appear in PCI MEM space.
1935 static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
1938 mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1939 struct pci_controller *hose, u32 bus, u32 base)
1943 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1946 save_exclude = mv64x60_pci_exclude_bridge;
1947 mv64x60_pci_exclude_bridge = 0;
1948 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1949 mv64360_offset[bus][0], (base << 16));
1950 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1951 mv64360_offset[bus][1], 0);
1952 mv64x60_pci_exclude_bridge = save_exclude;
1956 * mv64360_is_enabled_32bit()
1958 * On a MV64360, a window is enabled by either clearing a bit in the
1959 * CPU BAR Enable reg or setting a bit in the window's base reg.
1960 * Note that this doesn't work for windows on the PCI slave side but we don't
1961 * check those so its okay.
1964 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1968 if (((mv64360_32bit_windows[window].base_reg != 0) &&
1969 (mv64360_32bit_windows[window].size_reg != 0)) ||
1970 (window == MV64x60_CPU2SRAM_WIN)) {
1972 extra = mv64360_32bit_windows[window].extra;
1974 switch (extra & MV64x60_EXTRA_MASK) {
1975 case MV64x60_EXTRA_CPUWIN_ENAB:
1976 rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
1977 (1 << (extra & 0x1f))) == 0;
1980 case MV64x60_EXTRA_CPUPROT_ENAB:
1981 rc = (mv64x60_read(bh,
1982 mv64360_32bit_windows[window].base_reg) &
1983 (1 << (extra & 0x1f))) != 0;
1986 case MV64x60_EXTRA_ENET_ENAB:
1987 rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
1988 (1 << (extra & 0x7))) == 0;
1991 case MV64x60_EXTRA_MPSC_ENAB:
1992 rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
1993 (1 << (extra & 0x3))) == 0;
1996 case MV64x60_EXTRA_IDMA_ENAB:
1997 rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
1998 (1 << (extra & 0x7))) == 0;
2002 printk(KERN_ERR "mv64360_is_enabled: %s\n",
2003 "32bit table corrupted");
2011 * mv64360_enable_window_32bit()
2013 * On a MV64360, a window is enabled by either clearing a bit in the
2014 * CPU BAR Enable reg or setting a bit in the window's base reg.
2017 mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2021 pr_debug("enable 32bit window: %d\n", window);
2023 if (((mv64360_32bit_windows[window].base_reg != 0) &&
2024 (mv64360_32bit_windows[window].size_reg != 0)) ||
2025 (window == MV64x60_CPU2SRAM_WIN)) {
2027 extra = mv64360_32bit_windows[window].extra;
2029 switch (extra & MV64x60_EXTRA_MASK) {
2030 case MV64x60_EXTRA_CPUWIN_ENAB:
2031 mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2032 (1 << (extra & 0x1f)));
2035 case MV64x60_EXTRA_CPUPROT_ENAB:
2036 mv64x60_set_bits(bh,
2037 mv64360_32bit_windows[window].base_reg,
2038 (1 << (extra & 0x1f)));
2041 case MV64x60_EXTRA_ENET_ENAB:
2042 mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2043 (1 << (extra & 0x7)));
2046 case MV64x60_EXTRA_MPSC_ENAB:
2047 mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2048 (1 << (extra & 0x3)));
2051 case MV64x60_EXTRA_IDMA_ENAB:
2052 mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2053 (1 << (extra & 0x7)));
2057 printk(KERN_ERR "mv64360_enable: %s\n",
2058 "32bit table corrupted");
2064 * mv64360_disable_window_32bit()
2066 * On a MV64360, a window is disabled by either setting a bit in the
2067 * CPU BAR Enable reg or clearing a bit in the window's base reg.
2070 mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2074 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2075 window, mv64360_32bit_windows[window].base_reg,
2076 mv64360_32bit_windows[window].size_reg);
2078 if (((mv64360_32bit_windows[window].base_reg != 0) &&
2079 (mv64360_32bit_windows[window].size_reg != 0)) ||
2080 (window == MV64x60_CPU2SRAM_WIN)) {
2082 extra = mv64360_32bit_windows[window].extra;
2084 switch (extra & MV64x60_EXTRA_MASK) {
2085 case MV64x60_EXTRA_CPUWIN_ENAB:
2086 mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2087 (1 << (extra & 0x1f)));
2090 case MV64x60_EXTRA_CPUPROT_ENAB:
2091 mv64x60_clr_bits(bh,
2092 mv64360_32bit_windows[window].base_reg,
2093 (1 << (extra & 0x1f)));
2096 case MV64x60_EXTRA_ENET_ENAB:
2097 mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2098 (1 << (extra & 0x7)));
2101 case MV64x60_EXTRA_MPSC_ENAB:
2102 mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2103 (1 << (extra & 0x3)));
2106 case MV64x60_EXTRA_IDMA_ENAB:
2107 mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2108 (1 << (extra & 0x7)));
2112 printk(KERN_ERR "mv64360_disable: %s\n",
2113 "32bit table corrupted");
2119 * mv64360_enable_window_64bit()
2121 * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2125 mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2127 pr_debug("enable 64bit window: %d\n", window);
2129 if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2130 (mv64360_64bit_windows[window].size_reg != 0)) {
2132 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2133 == MV64x60_EXTRA_PCIACC_ENAB)
2134 mv64x60_set_bits(bh,
2135 mv64360_64bit_windows[window].base_lo_reg,
2136 (1 << (mv64360_64bit_windows[window].extra &
2139 printk(KERN_ERR "mv64360_enable: %s\n",
2140 "64bit table corrupted");
2145 * mv64360_disable_window_64bit()
2147 * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2151 mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2153 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2154 window, mv64360_64bit_windows[window].base_lo_reg,
2155 mv64360_64bit_windows[window].size_reg);
2157 if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2158 (mv64360_64bit_windows[window].size_reg != 0)) {
2159 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2160 == MV64x60_EXTRA_PCIACC_ENAB)
2161 mv64x60_clr_bits(bh,
2162 mv64360_64bit_windows[window].base_lo_reg,
2163 (1 << (mv64360_64bit_windows[window].extra &
2166 printk(KERN_ERR "mv64360_disable: %s\n",
2167 "64bit table corrupted");
2172 * mv64360_disable_all_windows()
2174 * The MV64360 has a few windows that aren't represented in the table of
2175 * windows at the top of this file. This routine turns all of them off
2176 * except for the memory controller windows, of course.
2179 mv64360_disable_all_windows(struct mv64x60_handle *bh,
2180 struct mv64x60_setup_info *si)
2184 /* Disable 32bit windows (don't disable cpu->mem windows) */
2185 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2187 preserve = si->window_preserve_mask_32_lo & (1 << i);
2189 preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
2192 mv64360_disable_window_32bit(bh, i);
2195 /* Disable 64bit windows */
2196 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
2197 if (!(si->window_preserve_mask_64 & (1<<i)))
2198 mv64360_disable_window_64bit(bh, i);
2200 /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2201 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2202 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2203 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2204 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2206 /* Disable all PCI-><whatever> windows */
2207 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2208 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2212 * mv64360_config_io2mem_windows()
2214 * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2215 * must be set up so that the respective ctlr can access system memory.
2217 static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2218 MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
2219 MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
2222 static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2223 MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
2224 MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
2227 static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2228 MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
2229 MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
2232 static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
2233 { 0xe, 0xd, 0xb, 0x7 };
2236 mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2237 struct mv64x60_setup_info *si,
2238 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
2242 pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2244 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
2245 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
2246 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
2248 mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
2249 mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
2251 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
2252 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
2253 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
2254 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
2256 /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2257 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
2258 if (bh->ci->is_enabled_32bit(bh, win)) {
2259 mv64x60_set_32bit_window(bh, enet_tab[i],
2260 mem_windows[i][0], mem_windows[i][1],
2261 (dram_selects[i] << 8) |
2262 (si->enet_options[i] & 0x3000));
2263 bh->ci->enable_window_32bit(bh, enet_tab[i]);
2265 /* Give enet r/w access to memory region */
2266 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
2268 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
2270 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
2273 mv64x60_set_32bit_window(bh, mpsc_tab[i],
2274 mem_windows[i][0], mem_windows[i][1],
2275 (dram_selects[i] << 8) |
2276 (si->mpsc_options[i] & 0x3000));
2277 bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
2279 /* Give mpsc r/w access to memory region */
2280 mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
2282 mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
2285 mv64x60_set_32bit_window(bh, idma_tab[i],
2286 mem_windows[i][0], mem_windows[i][1],
2287 (dram_selects[i] << 8) |
2288 (si->idma_options[i] & 0x3000));
2289 bh->ci->enable_window_32bit(bh, idma_tab[i]);
2291 /* Give idma r/w access to memory region */
2292 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
2294 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
2296 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
2298 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2304 * mv64360_set_mpsc2regs_window()
2306 * MPSC has a window to the bridge's internal registers. Call this routine
2307 * to change that window so it doesn't conflict with the windows mapping the
2308 * mpsc to system memory.
2311 mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2313 pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2314 mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2318 * mv64360_chip_specific_init()
2320 * Implement errata workarounds for the MV64360.
2323 mv64360_chip_specific_init(struct mv64x60_handle *bh,
2324 struct mv64x60_setup_info *si)
2326 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2327 mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24));
2329 #ifdef CONFIG_SERIAL_MPSC
2330 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2331 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2332 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2333 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2338 * mv64460_chip_specific_init()
2340 * Implement errata workarounds for the MV64460.
2343 mv64460_chip_specific_init(struct mv64x60_handle *bh,
2344 struct mv64x60_setup_info *si)
2346 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2347 mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25));
2348 mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4));
2350 #ifdef CONFIG_SERIAL_MPSC
2351 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2352 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2353 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2354 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2359 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2360 /* Export the hotswap register via sysfs for enum event monitoring */
2361 #define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */
2363 static DEFINE_MUTEX(mv64xxx_hs_lock);
2366 mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
2373 if (count < VAL_LEN_MAX)
2376 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2377 return -ERESTARTSYS;
2378 save_exclude = mv64x60_pci_exclude_bridge;
2379 mv64x60_pci_exclude_bridge = 0;
2380 early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2381 MV64360_PCICFG_CPCI_HOTSWAP, &v);
2382 mv64x60_pci_exclude_bridge = save_exclude;
2383 mutex_unlock(&mv64xxx_hs_lock);
2385 return sprintf(buf, "0x%08x\n", v);
2389 mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
2399 if (sscanf(buf, "%i", &v) == 1) {
2400 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2401 return -ERESTARTSYS;
2402 save_exclude = mv64x60_pci_exclude_bridge;
2403 mv64x60_pci_exclude_bridge = 0;
2404 early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2405 MV64360_PCICFG_CPCI_HOTSWAP, v);
2406 mv64x60_pci_exclude_bridge = save_exclude;
2407 mutex_unlock(&mv64xxx_hs_lock);
2415 static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */
2418 .mode = S_IRUGO | S_IWUSR,
2420 .size = VAL_LEN_MAX,
2421 .read = mv64xxx_hs_reg_read,
2422 .write = mv64xxx_hs_reg_write,
2425 /* Provide sysfs file indicating if this platform supports the hs_reg */
2427 mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr,
2430 struct platform_device *pdev;
2431 struct mv64xxx_pdata *pdp;
2434 pdev = container_of(dev, struct platform_device, dev);
2435 pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data;
2437 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2438 return -ERESTARTSYS;
2439 v = pdp->hs_reg_valid;
2440 mutex_unlock(&mv64xxx_hs_lock);
2442 return sprintf(buf, "%i\n", v);
2444 static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL);
2447 mv64xxx_sysfs_init(void)
2449 sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr);
2450 sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr);
2453 subsys_initcall(mv64xxx_sysfs_init);