err.no Git - linux-2.6/blob - arch/ppc/syslib/mv64x60.c

   1 /*
   2  * Common routines for the Marvell/Galileo Discovery line of host bridges
   3  * (gt64260, mv64360, mv64460, ...).
   4  *
   5  * Author: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/module.h>
  17 #include <linux/mutex.h>
  18 #include <linux/string.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/mv643xx.h>
  21 #include <linux/platform_device.h>
  22
  23 #include <asm/byteorder.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/machdep.h>
  28 #include <asm/pci-bridge.h>
  29 #include <asm/delay.h>
  30 #include <asm/mv64x60.h>
  31
  32
  33 u8 mv64x60_pci_exclude_bridge = 1;
  34 DEFINE_SPINLOCK(mv64x60_lock);
  35
  36 static phys_addr_t      mv64x60_bridge_pbase;
  37 static void             __iomem *mv64x60_bridge_vbase;
  38 static u32              mv64x60_bridge_type = MV64x60_TYPE_INVALID;
  39 static u32              mv64x60_bridge_rev;
  40 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  41 static struct pci_controller    sysfs_hose_a;
  42 #endif
  43
  44 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
  45 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
  46 static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  47         u32 window, u32 base);
  48 static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
  49         struct pci_controller *hose, u32 bus, u32 base);
  50 static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  51 static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  52 static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  53 static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  54 static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  55 static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
  56         struct mv64x60_setup_info *si);
  57 static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
  58         struct mv64x60_setup_info *si);
  59 static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
  60         struct mv64x60_setup_info *si);
  61
  62 static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
  63 static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
  64 static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  65         u32 window, u32 base);
  66 static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
  67         struct pci_controller *hose, u32 bus, u32 base);
  68 static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  69 static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  70 static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  71 static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  72 static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  73 static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
  74         struct mv64x60_setup_info *si);
  75 static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
  76         struct mv64x60_setup_info *si,
  77         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
  78 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
  79 static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
  80         struct mv64x60_setup_info *si);
  81 static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
  82         struct mv64x60_setup_info *si);
  83
  84
  85 /*
  86  * Define tables that have the chip-specific info for each type of
  87  * Marvell bridge chip.
  88  */
  89 static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
  90         .translate_size         = gt64260_translate_size,
  91         .untranslate_size       = gt64260_untranslate_size,
  92         .set_pci2mem_window     = gt64260_set_pci2mem_window,
  93         .set_pci2regs_window    = gt64260_set_pci2regs_window,
  94         .is_enabled_32bit       = gt64260_is_enabled_32bit,
  95         .enable_window_32bit    = gt64260_enable_window_32bit,
  96         .disable_window_32bit   = gt64260_disable_window_32bit,
  97         .enable_window_64bit    = gt64260_enable_window_64bit,
  98         .disable_window_64bit   = gt64260_disable_window_64bit,
  99         .disable_all_windows    = gt64260_disable_all_windows,
 100         .chip_specific_init     = gt64260a_chip_specific_init,
 101         .window_tab_32bit       = gt64260_32bit_windows,
 102         .window_tab_64bit       = gt64260_64bit_windows,
 103 };
 104
 105 static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
 106         .translate_size         = gt64260_translate_size,
 107         .untranslate_size       = gt64260_untranslate_size,
 108         .set_pci2mem_window     = gt64260_set_pci2mem_window,
 109         .set_pci2regs_window    = gt64260_set_pci2regs_window,
 110         .is_enabled_32bit       = gt64260_is_enabled_32bit,
 111         .enable_window_32bit    = gt64260_enable_window_32bit,
 112         .disable_window_32bit   = gt64260_disable_window_32bit,
 113         .enable_window_64bit    = gt64260_enable_window_64bit,
 114         .disable_window_64bit   = gt64260_disable_window_64bit,
 115         .disable_all_windows    = gt64260_disable_all_windows,
 116         .chip_specific_init     = gt64260b_chip_specific_init,
 117         .window_tab_32bit       = gt64260_32bit_windows,
 118         .window_tab_64bit       = gt64260_64bit_windows,
 119 };
 120
 121 static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
 122         .translate_size         = mv64360_translate_size,
 123         .untranslate_size       = mv64360_untranslate_size,
 124         .set_pci2mem_window     = mv64360_set_pci2mem_window,
 125         .set_pci2regs_window    = mv64360_set_pci2regs_window,
 126         .is_enabled_32bit       = mv64360_is_enabled_32bit,
 127         .enable_window_32bit    = mv64360_enable_window_32bit,
 128         .disable_window_32bit   = mv64360_disable_window_32bit,
 129         .enable_window_64bit    = mv64360_enable_window_64bit,
 130         .disable_window_64bit   = mv64360_disable_window_64bit,
 131         .disable_all_windows    = mv64360_disable_all_windows,
 132         .config_io2mem_windows  = mv64360_config_io2mem_windows,
 133         .set_mpsc2regs_window   = mv64360_set_mpsc2regs_window,
 134         .chip_specific_init     = mv64360_chip_specific_init,
 135         .window_tab_32bit       = mv64360_32bit_windows,
 136         .window_tab_64bit       = mv64360_64bit_windows,
 137 };
 138
 139 static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
 140         .translate_size         = mv64360_translate_size,
 141         .untranslate_size       = mv64360_untranslate_size,
 142         .set_pci2mem_window     = mv64360_set_pci2mem_window,
 143         .set_pci2regs_window    = mv64360_set_pci2regs_window,
 144         .is_enabled_32bit       = mv64360_is_enabled_32bit,
 145         .enable_window_32bit    = mv64360_enable_window_32bit,
 146         .disable_window_32bit   = mv64360_disable_window_32bit,
 147         .enable_window_64bit    = mv64360_enable_window_64bit,
 148         .disable_window_64bit   = mv64360_disable_window_64bit,
 149         .disable_all_windows    = mv64360_disable_all_windows,
 150         .config_io2mem_windows  = mv64360_config_io2mem_windows,
 151         .set_mpsc2regs_window   = mv64360_set_mpsc2regs_window,
 152         .chip_specific_init     = mv64460_chip_specific_init,
 153         .window_tab_32bit       = mv64360_32bit_windows,
 154         .window_tab_64bit       = mv64360_64bit_windows,
 155 };
 156
 157 /*
 158  *****************************************************************************
 159  *
 160  *      Platform Device Definitions
 161  *
 162  *****************************************************************************
 163  */
 164 #ifdef CONFIG_SERIAL_MPSC
 165 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
 166         .mrr_val                = 0x3ffffe38,
 167         .rcrr_val               = 0,
 168         .tcrr_val               = 0,
 169         .intr_cause_val         = 0,
 170         .intr_mask_val          = 0,
 171 };
 172
 173 static struct resource mv64x60_mpsc_shared_resources[] = {
 174         /* Do not change the order of the IORESOURCE_MEM resources */
 175         [0] = {
 176                 .name   = "mpsc routing base",
 177                 .start  = MV64x60_MPSC_ROUTING_OFFSET,
 178                 .end    = MV64x60_MPSC_ROUTING_OFFSET +
 179                         MPSC_ROUTING_REG_BLOCK_SIZE - 1,
 180                 .flags  = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .name   = "sdma intr base",
 184                 .start  = MV64x60_SDMA_INTR_OFFSET,
 185                 .end    = MV64x60_SDMA_INTR_OFFSET +
 186                         MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
 187                 .flags  = IORESOURCE_MEM,
 188         },
 189 };
 190
 191 static struct platform_device mpsc_shared_device = { /* Shared device */
 192         .name           = MPSC_SHARED_NAME,
 193         .id             = 0,
 194         .num_resources  = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
 195         .resource       = mv64x60_mpsc_shared_resources,
 196         .dev = {
 197                 .platform_data = &mv64x60_mpsc_shared_pdata,
 198         },
 199 };
 200
 201 static struct mpsc_pdata mv64x60_mpsc0_pdata = {
 202         .mirror_regs            = 0,
 203         .cache_mgmt             = 0,
 204         .max_idle               = 0,
 205         .default_baud           = 9600,
 206         .default_bits           = 8,
 207         .default_parity         = 'n',
 208         .default_flow           = 'n',
 209         .chr_1_val              = 0x00000000,
 210         .chr_2_val              = 0x00000000,
 211         .chr_10_val             = 0x00000003,
 212         .mpcr_val               = 0,
 213         .bcr_val                = 0,
 214         .brg_can_tune           = 0,
 215         .brg_clk_src            = 8,            /* Default to TCLK */
 216         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
 217 };
 218
 219 static struct resource mv64x60_mpsc0_resources[] = {
 220         /* Do not change the order of the IORESOURCE_MEM resources */
 221         [0] = {
 222                 .name   = "mpsc 0 base",
 223                 .start  = MV64x60_MPSC_0_OFFSET,
 224                 .end    = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
 225                 .flags  = IORESOURCE_MEM,
 226         },
 227         [1] = {
 228                 .name   = "sdma 0 base",
 229                 .start  = MV64x60_SDMA_0_OFFSET,
 230                 .end    = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
 231                 .flags  = IORESOURCE_MEM,
 232         },
 233         [2] = {
 234                 .name   = "brg 0 base",
 235                 .start  = MV64x60_BRG_0_OFFSET,
 236                 .end    = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
 237                 .flags  = IORESOURCE_MEM,
 238         },
 239         [3] = {
 240                 .name   = "sdma 0 irq",
 241                 .start  = MV64x60_IRQ_SDMA_0,
 242                 .end    = MV64x60_IRQ_SDMA_0,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static struct platform_device mpsc0_device = {
 248         .name           = MPSC_CTLR_NAME,
 249         .id             = 0,
 250         .num_resources  = ARRAY_SIZE(mv64x60_mpsc0_resources),
 251         .resource       = mv64x60_mpsc0_resources,
 252         .dev = {
 253                 .platform_data = &mv64x60_mpsc0_pdata,
 254         },
 255 };
 256
 257 static struct mpsc_pdata mv64x60_mpsc1_pdata = {
 258         .mirror_regs            = 0,
 259         .cache_mgmt             = 0,
 260         .max_idle               = 0,
 261         .default_baud           = 9600,
 262         .default_bits           = 8,
 263         .default_parity         = 'n',
 264         .default_flow           = 'n',
 265         .chr_1_val              = 0x00000000,
 266         .chr_1_val              = 0x00000000,
 267         .chr_2_val              = 0x00000000,
 268         .chr_10_val             = 0x00000003,
 269         .mpcr_val               = 0,
 270         .bcr_val                = 0,
 271         .brg_can_tune           = 0,
 272         .brg_clk_src            = 8,            /* Default to TCLK */
 273         .brg_clk_freq           = 100000000,    /* Default to 100 MHz */
 274 };
 275
 276 static struct resource mv64x60_mpsc1_resources[] = {
 277         /* Do not change the order of the IORESOURCE_MEM resources */
 278         [0] = {
 279                 .name   = "mpsc 1 base",
 280                 .start  = MV64x60_MPSC_1_OFFSET,
 281                 .end    = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
 282                 .flags  = IORESOURCE_MEM,
 283         },
 284         [1] = {
 285                 .name   = "sdma 1 base",
 286                 .start  = MV64x60_SDMA_1_OFFSET,
 287                 .end    = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
 288                 .flags  = IORESOURCE_MEM,
 289         },
 290         [2] = {
 291                 .name   = "brg 1 base",
 292                 .start  = MV64x60_BRG_1_OFFSET,
 293                 .end    = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
 294                 .flags  = IORESOURCE_MEM,
 295         },
 296         [3] = {
 297                 .name   = "sdma 1 irq",
 298                 .start  = MV64360_IRQ_SDMA_1,
 299                 .end    = MV64360_IRQ_SDMA_1,
 300                 .flags  = IORESOURCE_IRQ,
 301         },
 302 };
 303
 304 static struct platform_device mpsc1_device = {
 305         .name           = MPSC_CTLR_NAME,
 306         .id             = 1,
 307         .num_resources  = ARRAY_SIZE(mv64x60_mpsc1_resources),
 308         .resource       = mv64x60_mpsc1_resources,
 309         .dev = {
 310                 .platform_data = &mv64x60_mpsc1_pdata,
 311         },
 312 };
 313 #endif
 314
 315 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
 316 static struct resource mv64x60_eth_shared_resources[] = {
 317         [0] = {
 318                 .name   = "ethernet shared base",
 319                 .start  = MV643XX_ETH_SHARED_REGS,
 320                 .end    = MV643XX_ETH_SHARED_REGS +
 321                                         MV643XX_ETH_SHARED_REGS_SIZE - 1,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324 };
 325
 326 static struct platform_device mv64x60_eth_shared_device = {
 327         .name           = MV643XX_ETH_SHARED_NAME,
 328         .id             = 0,
 329         .num_resources  = ARRAY_SIZE(mv64x60_eth_shared_resources),
 330         .resource       = mv64x60_eth_shared_resources,
 331 };
 332
 333 #ifdef CONFIG_MV643XX_ETH_0
 334 static struct resource mv64x60_eth0_resources[] = {
 335         [0] = {
 336                 .name   = "eth0 irq",
 337                 .start  = MV64x60_IRQ_ETH_0,
 338                 .end    = MV64x60_IRQ_ETH_0,
 339                 .flags  = IORESOURCE_IRQ,
 340         },
 341 };
 342
 343 static struct mv643xx_eth_platform_data eth0_pd = {
 344         .port_number    = 0,
 345 };
 346
 347 static struct platform_device eth0_device = {
 348         .name           = MV643XX_ETH_NAME,
 349         .id             = 0,
 350         .num_resources  = ARRAY_SIZE(mv64x60_eth0_resources),
 351         .resource       = mv64x60_eth0_resources,
 352         .dev = {
 353                 .platform_data = &eth0_pd,
 354         },
 355 };
 356 #endif
 357
 358 #ifdef CONFIG_MV643XX_ETH_1
 359 static struct resource mv64x60_eth1_resources[] = {
 360         [0] = {
 361                 .name   = "eth1 irq",
 362                 .start  = MV64x60_IRQ_ETH_1,
 363                 .end    = MV64x60_IRQ_ETH_1,
 364                 .flags  = IORESOURCE_IRQ,
 365         },
 366 };
 367
 368 static struct mv643xx_eth_platform_data eth1_pd = {
 369         .port_number    = 1,
 370 };
 371
 372 static struct platform_device eth1_device = {
 373         .name           = MV643XX_ETH_NAME,
 374         .id             = 1,
 375         .num_resources  = ARRAY_SIZE(mv64x60_eth1_resources),
 376         .resource       = mv64x60_eth1_resources,
 377         .dev = {
 378                 .platform_data = &eth1_pd,
 379         },
 380 };
 381 #endif
 382
 383 #ifdef CONFIG_MV643XX_ETH_2
 384 static struct resource mv64x60_eth2_resources[] = {
 385         [0] = {
 386                 .name   = "eth2 irq",
 387                 .start  = MV64x60_IRQ_ETH_2,
 388                 .end    = MV64x60_IRQ_ETH_2,
 389                 .flags  = IORESOURCE_IRQ,
 390         },
 391 };
 392
 393 static struct mv643xx_eth_platform_data eth2_pd = {
 394         .port_number    = 2,
 395 };
 396
 397 static struct platform_device eth2_device = {
 398         .name           = MV643XX_ETH_NAME,
 399         .id             = 2,
 400         .num_resources  = ARRAY_SIZE(mv64x60_eth2_resources),
 401         .resource       = mv64x60_eth2_resources,
 402         .dev = {
 403                 .platform_data = &eth2_pd,
 404         },
 405 };
 406 #endif
 407 #endif
 408
 409 #ifdef  CONFIG_I2C_MV64XXX
 410 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
 411         .freq_m                 = 8,
 412         .freq_n                 = 3,
 413         .timeout                = 1000, /* Default timeout of 1 second */
 414         .retries                = 1,
 415 };
 416
 417 static struct resource mv64xxx_i2c_resources[] = {
 418         /* Do not change the order of the IORESOURCE_MEM resources */
 419         [0] = {
 420                 .name   = "mv64xxx i2c base",
 421                 .start  = MV64XXX_I2C_OFFSET,
 422                 .end    = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
 423                 .flags  = IORESOURCE_MEM,
 424         },
 425         [1] = {
 426                 .name   = "mv64xxx i2c irq",
 427                 .start  = MV64x60_IRQ_I2C,
 428                 .end    = MV64x60_IRQ_I2C,
 429                 .flags  = IORESOURCE_IRQ,
 430         },
 431 };
 432
 433 static struct platform_device i2c_device = {
 434         .name           = MV64XXX_I2C_CTLR_NAME,
 435         .id             = 0,
 436         .num_resources  = ARRAY_SIZE(mv64xxx_i2c_resources),
 437         .resource       = mv64xxx_i2c_resources,
 438         .dev = {
 439                 .platform_data = &mv64xxx_i2c_pdata,
 440         },
 441 };
 442 #endif
 443
 444 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
 445 static struct mv64xxx_pdata mv64xxx_pdata = {
 446         .hs_reg_valid   = 0,
 447 };
 448
 449 static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
 450         .name   = MV64XXX_DEV_NAME,
 451         .id     = 0,
 452         .dev = {
 453                 .platform_data = &mv64xxx_pdata,
 454         },
 455 };
 456 #endif
 457
 458 static struct platform_device *mv64x60_pd_devs[] __initdata = {
 459 #ifdef CONFIG_SERIAL_MPSC
 460         &mpsc_shared_device,
 461         &mpsc0_device,
 462         &mpsc1_device,
 463 #endif
 464 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
 465         &mv64x60_eth_shared_device,
 466 #endif
 467 #ifdef CONFIG_MV643XX_ETH_0
 468         &eth0_device,
 469 #endif
 470 #ifdef CONFIG_MV643XX_ETH_1
 471         &eth1_device,
 472 #endif
 473 #ifdef CONFIG_MV643XX_ETH_2
 474         &eth2_device,
 475 #endif
 476 #ifdef  CONFIG_I2C_MV64XXX
 477         &i2c_device,
 478 #endif
 479 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
 480         &mv64xxx_device,
 481 #endif
 482 };
 483
 484 /*
 485  *****************************************************************************
 486  *
 487  *      Bridge Initialization Routines
 488  *
 489  *****************************************************************************
 490  */
 491 /*
 492  * mv64x60_init()
 493  *
 494  * Initialize the bridge based on setting passed in via 'si'.  The bridge
 495  * handle, 'bh', will be set so that it can be used to make subsequent
 496  * calls to routines in this file.
 497  */
 498 int __init
 499 mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
 500 {
 501         u32     mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
 502
 503         if (ppc_md.progress)
 504                 ppc_md.progress("mv64x60 initialization", 0x0);
 505
 506         spin_lock_init(&mv64x60_lock);
 507         mv64x60_early_init(bh, si);
 508
 509         if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
 510                 iounmap(bh->v_base);
 511                 bh->v_base = 0;
 512                 if (ppc_md.progress)
 513                         ppc_md.progress("mv64x60_init: Can't determine chip",0);
 514                 return -1;
 515         }
 516
 517         bh->ci->disable_all_windows(bh, si);
 518         mv64x60_get_mem_windows(bh, mem_windows);
 519         mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
 520
 521         if (bh->ci->config_io2mem_windows)
 522                 bh->ci->config_io2mem_windows(bh, si, mem_windows);
 523         if (bh->ci->set_mpsc2regs_window)
 524                 bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
 525
 526         if (si->pci_1.enable_bus) {
 527                 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
 528                         si->pci_1.pci_io.size);
 529                 isa_io_base = bh->io_base_b;
 530         }
 531
 532         if (si->pci_0.enable_bus) {
 533                 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
 534                         si->pci_0.pci_io.size);
 535                 isa_io_base = bh->io_base_a;
 536
 537                 mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
 538                         MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
 539                 mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
 540                 mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
 541
 542                 mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
 543                 mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
 544                         mem_windows);
 545                 bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
 546                         si->phys_reg_base);
 547         }
 548
 549         if (si->pci_1.enable_bus) {
 550                 mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
 551                         MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
 552                 mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
 553                 mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
 554
 555                 mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
 556                 mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
 557                         mem_windows);
 558                 bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
 559                         si->phys_reg_base);
 560         }
 561
 562         bh->ci->chip_specific_init(bh, si);
 563         mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
 564
 565         return 0;
 566 }
 567
 568 /*
 569  * mv64x60_early_init()
 570  *
 571  * Do some bridge work that must take place before we start messing with
 572  * the bridge for real.
 573  */
 574 void __init
 575 mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
 576 {
 577         struct pci_controller   hose_a, hose_b;
 578
 579         memset(bh, 0, sizeof(*bh));
 580
 581         bh->p_base = si->phys_reg_base;
 582         bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
 583
 584         mv64x60_bridge_pbase = bh->p_base;
 585         mv64x60_bridge_vbase = bh->v_base;
 586
 587         /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
 588         bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
 589                 MV64x60_PCIMODE_MASK;
 590         bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
 591                 MV64x60_PCIMODE_MASK;
 592
 593         /* Need temporary hose structs to call mv64x60_set_bus() */
 594         memset(&hose_a, 0, sizeof(hose_a));
 595         memset(&hose_b, 0, sizeof(hose_b));
 596         setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
 597                 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
 598         setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
 599                 bh->v_base + MV64x60_PCI1_CONFIG_DATA);
 600         bh->hose_a = &hose_a;
 601         bh->hose_b = &hose_b;
 602
 603 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
 604         /* Save a copy of hose_a for sysfs functions -- hack */
 605         memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a));
 606 #endif
 607
 608         mv64x60_set_bus(bh, 0, 0);
 609         mv64x60_set_bus(bh, 1, 0);
 610
 611         bh->hose_a = NULL;
 612         bh->hose_b = NULL;
 613
 614         /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
 615         mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
 616         mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
 617
 618         /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
 619         mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
 620         mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
 621
 622         mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
 623         mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
 624 }
 625
 626 /*
 627  *****************************************************************************
 628  *
 629  *      Window Config Routines
 630  *
 631  *****************************************************************************
 632  */
 633 /*
 634  * mv64x60_get_32bit_window()
 635  *
 636  * Determine the base address and size of a 32-bit window on the bridge.
 637  */
 638 void __init
 639 mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
 640         u32 *base, u32 *size)
 641 {
 642         u32     val, base_reg, size_reg, base_bits, size_bits;
 643         u32     (*get_from_field)(u32 val, u32 num_bits);
 644
 645         base_reg = bh->ci->window_tab_32bit[window].base_reg;
 646
 647         if (base_reg != 0) {
 648                 size_reg  = bh->ci->window_tab_32bit[window].size_reg;
 649                 base_bits = bh->ci->window_tab_32bit[window].base_bits;
 650                 size_bits = bh->ci->window_tab_32bit[window].size_bits;
 651                 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
 652
 653                 val = mv64x60_read(bh, base_reg);
 654                 *base = get_from_field(val, base_bits);
 655
 656                 if (size_reg != 0) {
 657                         val = mv64x60_read(bh, size_reg);
 658                         val = get_from_field(val, size_bits);
 659                         *size = bh->ci->untranslate_size(*base, val, size_bits);
 660                 } else
 661                         *size = 0;
 662         } else {
 663                 *base = 0;
 664                 *size = 0;
 665         }
 666
 667         pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
 668                 window, *base, *size);
 669 }
 670
 671 /*
 672  * mv64x60_set_32bit_window()
 673  *
 674  * Set the base address and size of a 32-bit window on the bridge.
 675  */
 676 void __init
 677 mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
 678         u32 base, u32 size, u32 other_bits)
 679 {
 680         u32     val, base_reg, size_reg, base_bits, size_bits;
 681         u32     (*map_to_field)(u32 val, u32 num_bits);
 682
 683         pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
 684                 window, base, size, other_bits);
 685
 686         base_reg = bh->ci->window_tab_32bit[window].base_reg;
 687
 688         if (base_reg != 0) {
 689                 size_reg  = bh->ci->window_tab_32bit[window].size_reg;
 690                 base_bits = bh->ci->window_tab_32bit[window].base_bits;
 691                 size_bits = bh->ci->window_tab_32bit[window].size_bits;
 692                 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
 693
 694                 val = map_to_field(base, base_bits) | other_bits;
 695                 mv64x60_write(bh, base_reg, val);
 696
 697                 if (size_reg != 0) {
 698                         val = bh->ci->translate_size(base, size, size_bits);
 699                         val = map_to_field(val, size_bits);
 700                         mv64x60_write(bh, size_reg, val);
 701                 }
 702
 703                 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
 704         }
 705 }
 706
 707 /*
 708  * mv64x60_get_64bit_window()
 709  *
 710  * Determine the base address and size of a 64-bit window on the bridge.
 711  */
 712 void __init
 713 mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
 714         u32 *base_hi, u32 *base_lo, u32 *size)
 715 {
 716         u32     val, base_lo_reg, size_reg, base_lo_bits, size_bits;
 717         u32     (*get_from_field)(u32 val, u32 num_bits);
 718
 719         base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
 720
 721         if (base_lo_reg != 0) {
 722                 size_reg = bh->ci->window_tab_64bit[window].size_reg;
 723                 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
 724                 size_bits = bh->ci->window_tab_64bit[window].size_bits;
 725                 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
 726
 727                 *base_hi = mv64x60_read(bh,
 728                         bh->ci->window_tab_64bit[window].base_hi_reg);
 729
 730                 val = mv64x60_read(bh, base_lo_reg);
 731                 *base_lo = get_from_field(val, base_lo_bits);
 732
 733                 if (size_reg != 0) {
 734                         val = mv64x60_read(bh, size_reg);
 735                         val = get_from_field(val, size_bits);
 736                         *size = bh->ci->untranslate_size(*base_lo, val,
 737                                                                 size_bits);
 738                 } else
 739                         *size = 0;
 740         } else {
 741                 *base_hi = 0;
 742                 *base_lo = 0;
 743                 *size = 0;
 744         }
 745
 746         pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
 747                 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
 748 }
 749
 750 /*
 751  * mv64x60_set_64bit_window()
 752  *
 753  * Set the base address and size of a 64-bit window on the bridge.
 754  */
 755 void __init
 756 mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
 757         u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
 758 {
 759         u32     val, base_lo_reg, size_reg, base_lo_bits, size_bits;
 760         u32     (*map_to_field)(u32 val, u32 num_bits);
 761
 762         pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
 763                 "size: 0x%x, other: 0x%x\n",
 764                 window, base_hi, base_lo, size, other_bits);
 765
 766         base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
 767
 768         if (base_lo_reg != 0) {
 769                 size_reg = bh->ci->window_tab_64bit[window].size_reg;
 770                 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
 771                 size_bits = bh->ci->window_tab_64bit[window].size_bits;
 772                 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
 773
 774                 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
 775                         base_hi);
 776
 777                 val = map_to_field(base_lo, base_lo_bits) | other_bits;
 778                 mv64x60_write(bh, base_lo_reg, val);
 779
 780                 if (size_reg != 0) {
 781                         val = bh->ci->translate_size(base_lo, size, size_bits);
 782                         val = map_to_field(val, size_bits);
 783                         mv64x60_write(bh, size_reg, val);
 784                 }
 785
 786                 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
 787         }
 788 }
 789
 790 /*
 791  * mv64x60_mask()
 792  *
 793  * Take the high-order 'num_bits' of 'val' & mask off low bits.
 794  */
 795 u32 __init
 796 mv64x60_mask(u32 val, u32 num_bits)
 797 {
 798         return val & (0xffffffff << (32 - num_bits));
 799 }
 800
 801 /*
 802  * mv64x60_shift_left()
 803  *
 804  * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
 805  */
 806 u32 __init
 807 mv64x60_shift_left(u32 val, u32 num_bits)
 808 {
 809         return val << (32 - num_bits);
 810 }
 811
 812 /*
 813  * mv64x60_shift_right()
 814  *
 815  * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
 816  */
 817 u32 __init
 818 mv64x60_shift_right(u32 val, u32 num_bits)
 819 {
 820         return val >> (32 - num_bits);
 821 }
 822
 823 /*
 824  *****************************************************************************
 825  *
 826  *      Chip Identification Routines
 827  *
 828  *****************************************************************************
 829  */
 830 /*
 831  * mv64x60_get_type()
 832  *
 833  * Determine the type of bridge chip we have.
 834  */
 835 int __init
 836 mv64x60_get_type(struct mv64x60_handle *bh)
 837 {
 838         struct pci_controller hose;
 839         u16     val;
 840         u8      save_exclude;
 841
 842         memset(&hose, 0, sizeof(hose));
 843         setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
 844                 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
 845
 846         save_exclude = mv64x60_pci_exclude_bridge;
 847         mv64x60_pci_exclude_bridge = 0;
 848         /* Sanity check of bridge's Vendor ID */
 849         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
 850
 851         if (val != PCI_VENDOR_ID_MARVELL) {
 852                 mv64x60_pci_exclude_bridge = save_exclude;
 853                 return -1;
 854         }
 855
 856         /* Get the revision of the chip */
 857         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
 858                 &val);
 859         bh->rev = (u32)(val & 0xff);
 860
 861         /* Figure out the type of Marvell bridge it is */
 862         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
 863         mv64x60_pci_exclude_bridge = save_exclude;
 864
 865         switch (val) {
 866         case PCI_DEVICE_ID_MARVELL_GT64260:
 867                 switch (bh->rev) {
 868                 case GT64260_REV_A:
 869                         bh->type = MV64x60_TYPE_GT64260A;
 870                         break;
 871
 872                 default:
 873                         printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
 874                                 bh->rev);
 875                         /* Assume its similar to a 'B' rev and fallthru */
 876                 case GT64260_REV_B:
 877                         bh->type = MV64x60_TYPE_GT64260B;
 878                         break;
 879                 }
 880                 break;
 881
 882         case PCI_DEVICE_ID_MARVELL_MV64360:
 883                 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
 884                 bh->type = MV64x60_TYPE_MV64360;
 885                 break;
 886
 887         case PCI_DEVICE_ID_MARVELL_MV64460:
 888                 bh->type = MV64x60_TYPE_MV64460;
 889                 break;
 890
 891         default:
 892                 printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
 893                 return -1;
 894         }
 895
 896         /* Hang onto bridge type & rev for PIC code */
 897         mv64x60_bridge_type = bh->type;
 898         mv64x60_bridge_rev = bh->rev;
 899
 900         return 0;
 901 }
 902
 903 /*
 904  * mv64x60_setup_for_chip()
 905  *
 906  * Set 'bh' to use the proper set of routine for the bridge chip that we have.
 907  */
 908 int __init
 909 mv64x60_setup_for_chip(struct mv64x60_handle *bh)
 910 {
 911         int     rc = 0;
 912
 913         /* Set up chip-specific info based on the chip/bridge type */
 914         switch(bh->type) {
 915         case MV64x60_TYPE_GT64260A:
 916                 bh->ci = &gt64260a_ci;
 917                 break;
 918
 919         case MV64x60_TYPE_GT64260B:
 920                 bh->ci = &gt64260b_ci;
 921                 break;
 922
 923         case MV64x60_TYPE_MV64360:
 924                 bh->ci = &mv64360_ci;
 925                 break;
 926
 927         case MV64x60_TYPE_MV64460:
 928                 bh->ci = &mv64460_ci;
 929                 break;
 930
 931         case MV64x60_TYPE_INVALID:
 932         default:
 933                 if (ppc_md.progress)
 934                         ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
 935                 printk(KERN_ERR "mv64x60: Unsupported bridge\n");
 936                 rc = -1;
 937         }
 938
 939         return rc;
 940 }
 941
 942 /*
 943  * mv64x60_get_bridge_vbase()
 944  *
 945  * Return the virtual address of the bridge's registers.
 946  */
 947 void __iomem *
 948 mv64x60_get_bridge_vbase(void)
 949 {
 950         return mv64x60_bridge_vbase;
 951 }
 952
 953 /*
 954  * mv64x60_get_bridge_type()
 955  *
 956  * Return the type of bridge on the platform.
 957  */
 958 u32
 959 mv64x60_get_bridge_type(void)
 960 {
 961         return mv64x60_bridge_type;
 962 }
 963
 964 /*
 965  * mv64x60_get_bridge_rev()
 966  *
 967  * Return the revision of the bridge on the platform.
 968  */
 969 u32
 970 mv64x60_get_bridge_rev(void)
 971 {
 972         return mv64x60_bridge_rev;
 973 }
 974
 975 /*
 976  *****************************************************************************
 977  *
 978  *      System Memory Window Related Routines
 979  *
 980  *****************************************************************************
 981  */
 982 /*
 983  * mv64x60_get_mem_size()
 984  *
 985  * Calculate the amount of memory that the memory controller is set up for.
 986  * This should only be used by board-specific code if there is no other
 987  * way to determine the amount of memory in the system.
 988  */
 989 u32 __init
 990 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
 991 {
 992         struct mv64x60_handle   bh;
 993         u32     mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
 994         u32     rc = 0;
 995
 996         memset(&bh, 0, sizeof(bh));
 997
 998         bh.type = chip_type;
 999         bh.v_base = (void *)bridge_base;
1000
1001         if (!mv64x60_setup_for_chip(&bh)) {
1002                 mv64x60_get_mem_windows(&bh, mem_windows);
1003                 rc = mv64x60_calc_mem_size(&bh, mem_windows);
1004         }
1005
1006         return rc;
1007 }
1008
1009 /*
1010  * mv64x60_get_mem_windows()
1011  *
1012  * Get the values in the memory controller & return in the 'mem_windows' array.
1013  */
1014 void __init
1015 mv64x60_get_mem_windows(struct mv64x60_handle *bh,
1016         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1017 {
1018         u32     i, win;
1019
1020         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1021                 if (bh->ci->is_enabled_32bit(bh, win))
1022                         mv64x60_get_32bit_window(bh, win,
1023                                 &mem_windows[i][0], &mem_windows[i][1]);
1024                 else {
1025                         mem_windows[i][0] = 0;
1026                         mem_windows[i][1] = 0;
1027                 }
1028 }
1029
1030 /*
1031  * mv64x60_calc_mem_size()
1032  *
1033  * Using the memory controller register values in 'mem_windows', determine
1034  * how much memory it is set up for.
1035  */
1036 u32 __init
1037 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
1038         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1039 {
1040         u32     i, total = 0;
1041
1042         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
1043                 total += mem_windows[i][1];
1044
1045         return total;
1046 }
1047
1048 /*
1049  *****************************************************************************
1050  *
1051  *      CPU->System MEM, PCI Config Routines
1052  *
1053  *****************************************************************************
1054  */
1055 /*
1056  * mv64x60_config_cpu2mem_windows()
1057  *
1058  * Configure CPU->Memory windows on the bridge.
1059  */
1060 static u32 prot_tab[] __initdata = {
1061         MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1062         MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
1063 };
1064
1065 static u32 cpu_snoop_tab[] __initdata = {
1066         MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1067         MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
1068 };
1069
1070 void __init
1071 mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1072         struct mv64x60_setup_info *si,
1073         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1074 {
1075         u32     i, win;
1076
1077         /* Set CPU protection & snoop windows */
1078         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1079                 if (bh->ci->is_enabled_32bit(bh, win)) {
1080                         mv64x60_set_32bit_window(bh, prot_tab[i],
1081                                 mem_windows[i][0], mem_windows[i][1],
1082                                 si->cpu_prot_options[i]);
1083                         bh->ci->enable_window_32bit(bh, prot_tab[i]);
1084
1085                         if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
1086                                                                 base_reg != 0) {
1087                                 mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
1088                                         mem_windows[i][0], mem_windows[i][1],
1089                                         si->cpu_snoop_options[i]);
1090                                 bh->ci->enable_window_32bit(bh,
1091                                         cpu_snoop_tab[i]);
1092                         }
1093
1094                 }
1095 }
1096
1097 /*
1098  * mv64x60_config_cpu2pci_windows()
1099  *
1100  * Configure the CPU->PCI windows for one of the PCI buses.
1101  */
1102 static u32 win_tab[2][4] __initdata = {
1103         { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
1104           MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
1105         { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
1106           MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
1107 };
1108
1109 static u32 remap_tab[2][4] __initdata = {
1110         { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1111           MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
1112         { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1113           MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
1114 };
1115
1116 void __init
1117 mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1118         struct mv64x60_pci_info *pi, u32 bus)
1119 {
1120         int     i;
1121
1122         if (pi->pci_io.size > 0) {
1123                 mv64x60_set_32bit_window(bh, win_tab[bus][0],
1124                         pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
1125                 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1126                         pi->pci_io.pci_base_lo, 0, 0);
1127                 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1128         } else /* Actually, the window should already be disabled */
1129                 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1130
1131         for (i=0; i<3; i++)
1132                 if (pi->pci_mem[i].size > 0) {
1133                         mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
1134                                 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1135                                 pi->pci_mem[i].swap);
1136                         mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
1137                                 pi->pci_mem[i].pci_base_hi,
1138                                 pi->pci_mem[i].pci_base_lo, 0, 0);
1139                         bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1140                 } else /* Actually, the window should already be disabled */
1141                         bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1142 }
1143
1144 /*
1145  *****************************************************************************
1146  *
1147  *      PCI->System MEM Config Routines
1148  *
1149  *****************************************************************************
1150  */
1151 /*
1152  * mv64x60_config_pci2mem_windows()
1153  *
1154  * Configure the PCI->Memory windows on the bridge.
1155  */
1156 static u32 pci_acc_tab[2][4] __initdata = {
1157         { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1158           MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
1159         { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1160           MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
1161 };
1162
1163 static u32 pci_snoop_tab[2][4] __initdata = {
1164         { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
1165           MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
1166         { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
1167           MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
1168 };
1169
1170 static u32 pci_size_tab[2][4] __initdata = {
1171         { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1172           MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
1173         { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1174           MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
1175 };
1176
1177 void __init
1178 mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1179         struct pci_controller *hose, struct mv64x60_pci_info *pi,
1180         u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1181 {
1182         u32     i, win;
1183
1184         /*
1185          * Set the access control, snoop, BAR size, and window base addresses.
1186          * PCI->MEM windows base addresses will match exactly what the
1187          * CPU->MEM windows are.
1188          */
1189         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1190                 if (bh->ci->is_enabled_32bit(bh, win)) {
1191                         mv64x60_set_64bit_window(bh,
1192                                 pci_acc_tab[bus][i], 0,
1193                                 mem_windows[i][0], mem_windows[i][1],
1194                                 pi->acc_cntl_options[i]);
1195                         bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
1196
1197                         if (bh->ci->window_tab_64bit[
1198                                 pci_snoop_tab[bus][i]].base_lo_reg != 0) {
1199
1200                                 mv64x60_set_64bit_window(bh,
1201                                         pci_snoop_tab[bus][i], 0,
1202                                         mem_windows[i][0], mem_windows[i][1],
1203                                         pi->snoop_options[i]);
1204                                 bh->ci->enable_window_64bit(bh,
1205                                         pci_snoop_tab[bus][i]);
1206                         }
1207
1208                         bh->ci->set_pci2mem_window(hose, bus, i,
1209                                 mem_windows[i][0]);
1210                         mv64x60_write(bh, pci_size_tab[bus][i],
1211                                 mv64x60_mask(mem_windows[i][1] - 1, 20));
1212
1213                         /* Enable the window */
1214                         mv64x60_clr_bits(bh, ((bus == 0) ?
1215                                 MV64x60_PCI0_BAR_ENABLE :
1216                                 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1217                 }
1218 }
1219
1220 /*
1221  *****************************************************************************
1222  *
1223  *      Hose & Resource Alloc/Init Routines
1224  *
1225  *****************************************************************************
1226  */
1227 /*
1228  * mv64x60_alloc_hoses()
1229  *
1230  * Allocate the PCI hose structures for the bridge's PCI buses.
1231  */
1232 void __init
1233 mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1234         struct pci_controller **hose)
1235 {
1236         *hose = pcibios_alloc_controller();
1237         setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1238                 bh->v_base + cfg_data);
1239 }
1240
1241 /*
1242  * mv64x60_config_resources()
1243  *
1244  * Calculate the offsets, etc. for the hose structures to reflect all of
1245  * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1246  */
1247 void __init
1248 mv64x60_config_resources(struct pci_controller *hose,
1249         struct mv64x60_pci_info *pi, u32 io_base)
1250 {
1251         int             i;
1252         /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1253         static char     s[2][4][64];
1254
1255         if (pi->pci_io.size != 0) {
1256                 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
1257                         hose->index);
1258                 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
1259                         io_base - isa_io_base + pi->pci_io.size - 1,
1260                         IORESOURCE_IO, s[hose->index][0]);
1261                 hose->io_space.start = pi->pci_io.pci_base_lo;
1262                 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
1263                 hose->io_base_phys = pi->pci_io.cpu_base;
1264                 hose->io_base_virt = (void *)isa_io_base;
1265         }
1266
1267         for (i=0; i<3; i++)
1268                 if (pi->pci_mem[i].size != 0) {
1269                         sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
1270                                 hose->index, i);
1271                         pci_init_resource(&hose->mem_resources[i],
1272                                 pi->pci_mem[i].cpu_base,
1273                                 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
1274                                 IORESOURCE_MEM, s[hose->index][i+1]);
1275                 }
1276
1277         hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
1278                                                 pi->pci_mem[0].size - 1;
1279         hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1280                                                 pi->pci_mem[0].pci_base_lo;
1281 }
1282
1283 /*
1284  * mv64x60_config_pci_params()
1285  *
1286  * Configure a hose's PCI config space parameters.
1287  */
1288 void __init
1289 mv64x60_config_pci_params(struct pci_controller *hose,
1290         struct mv64x60_pci_info *pi)
1291 {
1292         u32     devfn;
1293         u16     u16_val;
1294         u8      save_exclude;
1295
1296         devfn = PCI_DEVFN(0,0);
1297
1298         save_exclude = mv64x60_pci_exclude_bridge;
1299         mv64x60_pci_exclude_bridge = 0;
1300
1301         /* Set class code to indicate host bridge */
1302         u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
1303         early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
1304
1305         /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1306         early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
1307         u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
1308                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
1309         u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1310         early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
1311
1312         /* Set latency timer, cache line size, clear BIST */
1313         u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2);
1314         early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1315
1316         mv64x60_pci_exclude_bridge = save_exclude;
1317 }
1318
1319 /*
1320  *****************************************************************************
1321  *
1322  *      PCI Related Routine
1323  *
1324  *****************************************************************************
1325  */
1326 /*
1327  * mv64x60_set_bus()
1328  *
1329  * Set the bus number for the hose directly under the bridge.
1330  */
1331 void __init
1332 mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1333 {
1334         struct pci_controller   *hose;
1335         u32     pci_mode, p2p_cfg, pci_cfg_offset, val;
1336         u8      save_exclude;
1337
1338         if (bus == 0) {
1339                 pci_mode = bh->pci_mode_a;
1340                 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1341                 pci_cfg_offset = 0x64;
1342                 hose = bh->hose_a;
1343         } else {
1344                 pci_mode = bh->pci_mode_b;
1345                 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1346                 pci_cfg_offset = 0xe4;
1347                 hose = bh->hose_b;
1348         }
1349
1350         child_bus &= 0xff;
1351         val = mv64x60_read(bh, p2p_cfg);
1352
1353         if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
1354                 val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1355                 val |= (child_bus << 16) | 0xff;
1356                 mv64x60_write(bh, p2p_cfg, val);
1357                 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1358         } else { /* PCI-X */
1359                 /*
1360                  * Need to use the current bus/dev number (that's in the
1361                  * P2P CONFIG reg) to access the bridge's pci config space.
1362                  */
1363                 save_exclude = mv64x60_pci_exclude_bridge;
1364                 mv64x60_pci_exclude_bridge = 0;
1365                 early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
1366                         PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
1367                         pci_cfg_offset, child_bus << 8);
1368                 mv64x60_pci_exclude_bridge = save_exclude;
1369         }
1370 }
1371
1372 /*
1373  * mv64x60_pci_exclude_device()
1374  *
1375  * This routine is used to make the bridge not appear when the
1376  * PCI subsystem is accessing PCI devices (in PCI config space).
1377  */
1378 int
1379 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
1380 {
1381         struct pci_controller   *hose;
1382
1383         hose = pci_bus_to_hose(bus);
1384
1385         /* Skip slot 0 on both hoses */
1386         if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
1387                 (hose->first_busno == bus))
1388
1389                 return PCIBIOS_DEVICE_NOT_FOUND;
1390         else
1391                 return PCIBIOS_SUCCESSFUL;
1392 } /* mv64x60_pci_exclude_device() */
1393
1394 /*
1395  *****************************************************************************
1396  *
1397  *      Platform Device Routines
1398  *
1399  *****************************************************************************
1400  */
1401
1402 /*
1403  * mv64x60_pd_fixup()
1404  *
1405  * Need to add the base addr of where the bridge's regs are mapped in the
1406  * physical addr space so drivers can ioremap() them.
1407  */
1408 void __init
1409 mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1410         u32 entries)
1411 {
1412         struct resource *r;
1413         u32             i, j;
1414
1415         for (i=0; i<entries; i++) {
1416                 j = 0;
1417
1418                 while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
1419                         != NULL) {
1420
1421                         r->start += bh->p_base;
1422                         r->end += bh->p_base;
1423                         j++;
1424                 }
1425         }
1426 }
1427
1428 /*
1429  * mv64x60_add_pds()
1430  *
1431  * Add the mv64x60 platform devices to the list of platform devices.
1432  */
1433 static int __init
1434 mv64x60_add_pds(void)
1435 {
1436         return platform_add_devices(mv64x60_pd_devs,
1437                 ARRAY_SIZE(mv64x60_pd_devs));
1438 }
1439 arch_initcall(mv64x60_add_pds);
1440
1441 /*
1442  *****************************************************************************
1443  *
1444  *      GT64260-Specific Routines
1445  *
1446  *****************************************************************************
1447  */
1448 /*
1449  * gt64260_translate_size()
1450  *
1451  * On the GT64260, the size register is really the "top" address of the window.
1452  */
1453 static u32 __init
1454 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
1455 {
1456         return base + mv64x60_mask(size - 1, num_bits);
1457 }
1458
1459 /*
1460  * gt64260_untranslate_size()
1461  *
1462  * Translate the top address of a window into a window size.
1463  */
1464 static u32 __init
1465 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
1466 {
1467         if (size >= base)
1468                 size = size - base + (1 << (32 - num_bits));
1469         else
1470                 size = 0;
1471
1472         return size;
1473 }
1474
1475 /*
1476  * gt64260_set_pci2mem_window()
1477  *
1478  * The PCI->MEM window registers are actually in PCI config space so need
1479  * to set them by setting the correct config space BARs.
1480  */
1481 static u32 gt64260_reg_addrs[2][4] __initdata = {
1482         { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1483 };
1484
1485 static void __init
1486 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1487         u32 base)
1488 {
1489         u8      save_exclude;
1490
1491         pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1492                 hose->index, base);
1493
1494         save_exclude = mv64x60_pci_exclude_bridge;
1495         mv64x60_pci_exclude_bridge = 0;
1496         early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1497                 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1498         mv64x60_pci_exclude_bridge = save_exclude;
1499 }
1500
1501 /*
1502  * gt64260_set_pci2regs_window()
1503  *
1504  * Set where the bridge's registers appear in PCI MEM space.
1505  */
1506 static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
1507
1508 static void __init
1509 gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1510         struct pci_controller *hose, u32 bus, u32 base)
1511 {
1512         u8      save_exclude;
1513
1514         pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1515                 base);
1516
1517         save_exclude = mv64x60_pci_exclude_bridge;
1518         mv64x60_pci_exclude_bridge = 0;
1519         early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1520                 (base << 16));
1521         mv64x60_pci_exclude_bridge = save_exclude;
1522 }
1523
1524 /*
1525  * gt64260_is_enabled_32bit()
1526  *
1527  * On a GT64260, a window is enabled iff its top address is >= to its base
1528  * address.
1529  */
1530 static u32 __init
1531 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1532 {
1533         u32     rc = 0;
1534
1535         if ((gt64260_32bit_windows[window].base_reg != 0) &&
1536                 (gt64260_32bit_windows[window].size_reg != 0) &&
1537                 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
1538                         ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
1539                  (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
1540                         ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
1541
1542                 rc = 1;
1543
1544         return rc;
1545 }
1546
1547 /*
1548  * gt64260_enable_window_32bit()
1549  *
1550  * On the GT64260, a window is enabled iff the top address is >= to the base
1551  * address of the window.  Since the window has already been configured by
1552  * the time this routine is called, we have nothing to do here.
1553  */
1554 static void __init
1555 gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1556 {
1557         pr_debug("enable 32bit window: %d\n", window);
1558 }
1559
1560 /*
1561  * gt64260_disable_window_32bit()
1562  *
1563  * On a GT64260, you disable a window by setting its top address to be less
1564  * than its base address.
1565  */
1566 static void __init
1567 gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1568 {
1569         pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1570                 window, gt64260_32bit_windows[window].base_reg,
1571                 gt64260_32bit_windows[window].size_reg);
1572
1573         if ((gt64260_32bit_windows[window].base_reg != 0) &&
1574                 (gt64260_32bit_windows[window].size_reg != 0)) {
1575
1576                 /* To disable, make bottom reg higher than top reg */
1577                 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1578                 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1579         }
1580 }
1581
1582 /*
1583  * gt64260_enable_window_64bit()
1584  *
1585  * On the GT64260, a window is enabled iff the top address is >= to the base
1586  * address of the window.  Since the window has already been configured by
1587  * the time this routine is called, we have nothing to do here.
1588  */
1589 static void __init
1590 gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1591 {
1592         pr_debug("enable 64bit window: %d\n", window);
1593 }
1594
1595 /*
1596  * gt64260_disable_window_64bit()
1597  *
1598  * On a GT64260, you disable a window by setting its top address to be less
1599  * than its base address.
1600  */
1601 static void __init
1602 gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1603 {
1604         pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1605                 window, gt64260_64bit_windows[window].base_lo_reg,
1606                 gt64260_64bit_windows[window].size_reg);
1607
1608         if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
1609                 (gt64260_64bit_windows[window].size_reg != 0)) {
1610
1611                 /* To disable, make bottom reg higher than top reg */
1612                 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
1613                                                                         0xfff);
1614                 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1615                 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1616         }
1617 }
1618
1619 /*
1620  * gt64260_disable_all_windows()
1621  *
1622  * The GT64260 has several windows that aren't represented in the table of
1623  * windows at the top of this file.  This routine turns all of them off
1624  * except for the memory controller windows, of course.
1625  */
1626 static void __init
1627 gt64260_disable_all_windows(struct mv64x60_handle *bh,
1628         struct mv64x60_setup_info *si)
1629 {
1630         u32     i, preserve;
1631
1632         /* Disable 32bit windows (don't disable cpu->mem windows) */
1633         for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
1634                 if (i < 32)
1635                         preserve = si->window_preserve_mask_32_lo & (1 << i);
1636                 else
1637                         preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
1638
1639                 if (!preserve)
1640                         gt64260_disable_window_32bit(bh, i);
1641         }
1642
1643         /* Disable 64bit windows */
1644         for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
1645                 if (!(si->window_preserve_mask_64 & (1<<i)))
1646                         gt64260_disable_window_64bit(bh, i);
1647
1648         /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1649         mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
1650         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
1651         mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
1652         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
1653         mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
1654         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
1655         mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
1656         mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
1657
1658         /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1659         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
1660         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
1661         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
1662         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
1663         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
1664         mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
1665         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
1666         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
1667         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
1668         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
1669         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
1670         mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
1671
1672         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
1673         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
1674         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
1675         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
1676         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
1677         mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
1678         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
1679         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
1680         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
1681         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
1682         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
1683         mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
1684
1685         /* Disable all PCI-><whatever> windows */
1686         mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
1687         mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
1688
1689         /*
1690          * Some firmwares enable a bunch of intr sources
1691          * for the PCI INT output pins.
1692          */
1693         mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
1694         mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
1695         mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
1696         mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
1697         mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
1698         mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
1699         mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
1700         mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1701         mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1702         mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1703 }
1704
1705 /*
1706  * gt64260a_chip_specific_init()
1707  *
1708  * Implement errata workarounds for the GT64260A.
1709  */
1710 static void __init
1711 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1712         struct mv64x60_setup_info *si)
1713 {
1714 #ifdef CONFIG_SERIAL_MPSC
1715         struct resource *r;
1716 #endif
1717 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1718         u32     val;
1719         u8      save_exclude;
1720 #endif
1721
1722         if (si->pci_0.enable_bus)
1723                 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1724                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1725
1726         if (si->pci_1.enable_bus)
1727                 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1728                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1729
1730         /*
1731          * Dave Wilhardt found that bit 4 in the PCI Command registers must
1732          * be set if you are using cache coherency.
1733          */
1734 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1735         /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1736         if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1737                 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1738
1739         save_exclude = mv64x60_pci_exclude_bridge;
1740         mv64x60_pci_exclude_bridge = 0;
1741         if (si->pci_0.enable_bus) {
1742                 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1743                         PCI_COMMAND, &val);
1744                 val |= PCI_COMMAND_INVALIDATE;
1745                 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1746                         PCI_COMMAND, val);
1747         }
1748
1749         if (si->pci_1.enable_bus) {
1750                 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1751                         PCI_COMMAND, &val);
1752                 val |= PCI_COMMAND_INVALIDATE;
1753                 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1754                         PCI_COMMAND, val);
1755         }
1756         mv64x60_pci_exclude_bridge = save_exclude;
1757 #endif
1758
1759         /* Disable buffer/descriptor snooping */
1760         mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1761         mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1762
1763 #ifdef CONFIG_SERIAL_MPSC
1764         mv64x60_mpsc0_pdata.mirror_regs = 1;
1765         mv64x60_mpsc0_pdata.cache_mgmt = 1;
1766         mv64x60_mpsc1_pdata.mirror_regs = 1;
1767         mv64x60_mpsc1_pdata.cache_mgmt = 1;
1768
1769         if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1770                         != NULL) {
1771                 r->start = MV64x60_IRQ_SDMA_0;
1772                 r->end = MV64x60_IRQ_SDMA_0;
1773         }
1774 #endif
1775 }
1776
1777 /*
1778  * gt64260b_chip_specific_init()
1779  *
1780  * Implement errata workarounds for the GT64260B.
1781  */
1782 static void __init
1783 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1784         struct mv64x60_setup_info *si)
1785 {
1786 #ifdef CONFIG_SERIAL_MPSC
1787         struct resource *r;
1788 #endif
1789 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1790         u32     val;
1791         u8      save_exclude;
1792 #endif
1793
1794         if (si->pci_0.enable_bus)
1795                 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1796                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1797
1798         if (si->pci_1.enable_bus)
1799                 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1800                         ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1801
1802         /*
1803          * Dave Wilhardt found that bit 4 in the PCI Command registers must
1804          * be set if you are using cache coherency.
1805          */
1806 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1807         mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
1808
1809         /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1810         if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1811                 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1812
1813         save_exclude = mv64x60_pci_exclude_bridge;
1814         mv64x60_pci_exclude_bridge = 0;
1815         if (si->pci_0.enable_bus) {
1816                 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1817                         PCI_COMMAND, &val);
1818                 val |= PCI_COMMAND_INVALIDATE;
1819                 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1820                         PCI_COMMAND, val);
1821         }
1822
1823         if (si->pci_1.enable_bus) {
1824                 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1825                         PCI_COMMAND, &val);
1826                 val |= PCI_COMMAND_INVALIDATE;
1827                 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1828                         PCI_COMMAND, val);
1829         }
1830         mv64x60_pci_exclude_bridge = save_exclude;
1831 #endif
1832
1833         /* Disable buffer/descriptor snooping */
1834         mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1835         mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1836
1837 #ifdef CONFIG_SERIAL_MPSC
1838         /*
1839          * The 64260B is not supposed to have the bug where the MPSC & ENET
1840          * can't access cache coherent regions.  However, testing has shown
1841          * that the MPSC, at least, still has this bug.
1842          */
1843         mv64x60_mpsc0_pdata.cache_mgmt = 1;
1844         mv64x60_mpsc1_pdata.cache_mgmt = 1;
1845
1846         if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1847                         != NULL) {
1848                 r->start = MV64x60_IRQ_SDMA_0;
1849                 r->end = MV64x60_IRQ_SDMA_0;
1850         }
1851 #endif
1852 }
1853
1854 /*
1855  *****************************************************************************
1856  *
1857  *      MV64360-Specific Routines
1858  *
1859  *****************************************************************************
1860  */
1861 /*
1862  * mv64360_translate_size()
1863  *
1864  * On the MV64360, the size register is set similar to the size you get
1865  * from a pci config space BAR register.  That is, programmed from LSB to MSB
1866  * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1867  * assumption that the size is a power of 2.
1868  */
1869 static u32 __init
1870 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
1871 {
1872         return mv64x60_mask(size - 1, num_bits);
1873 }
1874
1875 /*
1876  * mv64360_untranslate_size()
1877  *
1878  * Translate the size register value of a window into a window size.
1879  */
1880 static u32 __init
1881 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
1882 {
1883         if (size > 0) {
1884                 size >>= (32 - num_bits);
1885                 size++;
1886                 size <<= (32 - num_bits);
1887         }
1888
1889         return size;
1890 }
1891
1892 /*
1893  * mv64360_set_pci2mem_window()
1894  *
1895  * The PCI->MEM window registers are actually in PCI config space so need
1896  * to set them by setting the correct config space BARs.
1897  */
1898 struct {
1899         u32     fcn;
1900         u32     base_hi_bar;
1901         u32     base_lo_bar;
1902 } static mv64360_reg_addrs[2][4] __initdata = {
1903         {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1904          { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1905         {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1906          { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1907 };
1908
1909 static void __init
1910 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1911         u32 base)
1912 {
1913         u8 save_exclude;
1914
1915         pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1916                 hose->index, base);
1917
1918         save_exclude = mv64x60_pci_exclude_bridge;
1919         mv64x60_pci_exclude_bridge = 0;
1920         early_write_config_dword(hose, 0,
1921                 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1922                 mv64360_reg_addrs[bus][window].base_hi_bar, 0);
1923         early_write_config_dword(hose, 0,
1924                 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1925                 mv64360_reg_addrs[bus][window].base_lo_bar,
1926                 mv64x60_mask(base,20) | 0xc);
1927         mv64x60_pci_exclude_bridge = save_exclude;
1928 }
1929
1930 /*
1931  * mv64360_set_pci2regs_window()
1932  *
1933  * Set where the bridge's registers appear in PCI MEM space.
1934  */
1935 static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
1936
1937 static void __init
1938 mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1939         struct pci_controller *hose, u32 bus, u32 base)
1940 {
1941         u8      save_exclude;
1942
1943         pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1944                 base);
1945
1946         save_exclude = mv64x60_pci_exclude_bridge;
1947         mv64x60_pci_exclude_bridge = 0;
1948         early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1949                 mv64360_offset[bus][0], (base << 16));
1950         early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1951                 mv64360_offset[bus][1], 0);
1952         mv64x60_pci_exclude_bridge = save_exclude;
1953 }
1954
1955 /*
1956  * mv64360_is_enabled_32bit()
1957  *
1958  * On a MV64360, a window is enabled by either clearing a bit in the
1959  * CPU BAR Enable reg or setting a bit in the window's base reg.
1960  * Note that this doesn't work for windows on the PCI slave side but we don't
1961  * check those so its okay.
1962  */
1963 static u32 __init
1964 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1965 {
1966         u32     extra, rc = 0;
1967
1968         if (((mv64360_32bit_windows[window].base_reg != 0) &&
1969                 (mv64360_32bit_windows[window].size_reg != 0)) ||
1970                 (window == MV64x60_CPU2SRAM_WIN)) {
1971
1972                 extra = mv64360_32bit_windows[window].extra;
1973
1974                 switch (extra & MV64x60_EXTRA_MASK) {
1975                 case MV64x60_EXTRA_CPUWIN_ENAB:
1976                         rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
1977                                 (1 << (extra & 0x1f))) == 0;
1978                         break;
1979
1980                 case MV64x60_EXTRA_CPUPROT_ENAB:
1981                         rc = (mv64x60_read(bh,
1982                                 mv64360_32bit_windows[window].base_reg) &
1983                                         (1 << (extra & 0x1f))) != 0;
1984                         break;
1985
1986                 case MV64x60_EXTRA_ENET_ENAB:
1987                         rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
1988                                 (1 << (extra & 0x7))) == 0;
1989                         break;
1990
1991                 case MV64x60_EXTRA_MPSC_ENAB:
1992                         rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
1993                                 (1 << (extra & 0x3))) == 0;
1994                         break;
1995
1996                 case MV64x60_EXTRA_IDMA_ENAB:
1997                         rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
1998                                 (1 << (extra & 0x7))) == 0;
1999                         break;
2000
2001                 default:
2002                         printk(KERN_ERR "mv64360_is_enabled: %s\n",
2003                                 "32bit table corrupted");
2004                 }
2005         }
2006
2007         return rc;
2008 }
2009
2010 /*
2011  * mv64360_enable_window_32bit()
2012  *
2013  * On a MV64360, a window is enabled by either clearing a bit in the
2014  * CPU BAR Enable reg or setting a bit in the window's base reg.
2015  */
2016 static void __init
2017 mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2018 {
2019         u32     extra;
2020
2021         pr_debug("enable 32bit window: %d\n", window);
2022
2023         if (((mv64360_32bit_windows[window].base_reg != 0) &&
2024                 (mv64360_32bit_windows[window].size_reg != 0)) ||
2025                 (window == MV64x60_CPU2SRAM_WIN)) {
2026
2027                 extra = mv64360_32bit_windows[window].extra;
2028
2029                 switch (extra & MV64x60_EXTRA_MASK) {
2030                 case MV64x60_EXTRA_CPUWIN_ENAB:
2031                         mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2032                                 (1 << (extra & 0x1f)));
2033                         break;
2034
2035                 case MV64x60_EXTRA_CPUPROT_ENAB:
2036                         mv64x60_set_bits(bh,
2037                                 mv64360_32bit_windows[window].base_reg,
2038                                 (1 << (extra & 0x1f)));
2039                         break;
2040
2041                 case MV64x60_EXTRA_ENET_ENAB:
2042                         mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2043                                 (1 << (extra & 0x7)));
2044                         break;
2045
2046                 case MV64x60_EXTRA_MPSC_ENAB:
2047                         mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2048                                 (1 << (extra & 0x3)));
2049                         break;
2050
2051                 case MV64x60_EXTRA_IDMA_ENAB:
2052                         mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2053                                 (1 << (extra & 0x7)));
2054                         break;
2055
2056                 default:
2057                         printk(KERN_ERR "mv64360_enable: %s\n",
2058                                 "32bit table corrupted");
2059                 }
2060         }
2061 }
2062
2063 /*
2064  * mv64360_disable_window_32bit()
2065  *
2066  * On a MV64360, a window is disabled by either setting a bit in the
2067  * CPU BAR Enable reg or clearing a bit in the window's base reg.
2068  */
2069 static void __init
2070 mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2071 {
2072         u32     extra;
2073
2074         pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2075                 window, mv64360_32bit_windows[window].base_reg,
2076                 mv64360_32bit_windows[window].size_reg);
2077
2078         if (((mv64360_32bit_windows[window].base_reg != 0) &&
2079                 (mv64360_32bit_windows[window].size_reg != 0)) ||
2080                 (window == MV64x60_CPU2SRAM_WIN)) {
2081
2082                 extra = mv64360_32bit_windows[window].extra;
2083
2084                 switch (extra & MV64x60_EXTRA_MASK) {
2085                 case MV64x60_EXTRA_CPUWIN_ENAB:
2086                         mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2087                                 (1 << (extra & 0x1f)));
2088                         break;
2089
2090                 case MV64x60_EXTRA_CPUPROT_ENAB:
2091                         mv64x60_clr_bits(bh,
2092                                 mv64360_32bit_windows[window].base_reg,
2093                                 (1 << (extra & 0x1f)));
2094                         break;
2095
2096                 case MV64x60_EXTRA_ENET_ENAB:
2097                         mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2098                                 (1 << (extra & 0x7)));
2099                         break;
2100
2101                 case MV64x60_EXTRA_MPSC_ENAB:
2102                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2103                                 (1 << (extra & 0x3)));
2104                         break;
2105
2106                 case MV64x60_EXTRA_IDMA_ENAB:
2107                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2108                                 (1 << (extra & 0x7)));
2109                         break;
2110
2111                 default:
2112                         printk(KERN_ERR "mv64360_disable: %s\n",
2113                                 "32bit table corrupted");
2114                 }
2115         }
2116 }
2117
2118 /*
2119  * mv64360_enable_window_64bit()
2120  *
2121  * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2122  * base reg.
2123  */
2124 static void __init
2125 mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2126 {
2127         pr_debug("enable 64bit window: %d\n", window);
2128
2129         if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2130                 (mv64360_64bit_windows[window].size_reg != 0)) {
2131
2132                 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2133                                 == MV64x60_EXTRA_PCIACC_ENAB)
2134                         mv64x60_set_bits(bh,
2135                                 mv64360_64bit_windows[window].base_lo_reg,
2136                                 (1 << (mv64360_64bit_windows[window].extra &
2137                                                                         0x1f)));
2138                 else
2139                         printk(KERN_ERR "mv64360_enable: %s\n",
2140                                 "64bit table corrupted");
2141         }
2142 }
2143
2144 /*
2145  * mv64360_disable_window_64bit()
2146  *
2147  * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2148  * base reg.
2149  */
2150 static void __init
2151 mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2152 {
2153         pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2154                 window, mv64360_64bit_windows[window].base_lo_reg,
2155                 mv64360_64bit_windows[window].size_reg);
2156
2157         if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2158                         (mv64360_64bit_windows[window].size_reg != 0)) {
2159                 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2160                                 == MV64x60_EXTRA_PCIACC_ENAB)
2161                         mv64x60_clr_bits(bh,
2162                                 mv64360_64bit_windows[window].base_lo_reg,
2163                                 (1 << (mv64360_64bit_windows[window].extra &
2164                                                                         0x1f)));
2165                 else
2166                         printk(KERN_ERR "mv64360_disable: %s\n",
2167                                 "64bit table corrupted");
2168         }
2169 }
2170
2171 /*
2172  * mv64360_disable_all_windows()
2173  *
2174  * The MV64360 has a few windows that aren't represented in the table of
2175  * windows at the top of this file.  This routine turns all of them off
2176  * except for the memory controller windows, of course.
2177  */
2178 static void __init
2179 mv64360_disable_all_windows(struct mv64x60_handle *bh,
2180         struct mv64x60_setup_info *si)
2181 {
2182         u32     preserve, i;
2183
2184         /* Disable 32bit windows (don't disable cpu->mem windows) */
2185         for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2186                 if (i < 32)
2187                         preserve = si->window_preserve_mask_32_lo & (1 << i);
2188                 else
2189                         preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
2190
2191                 if (!preserve)
2192                         mv64360_disable_window_32bit(bh, i);
2193         }
2194
2195         /* Disable 64bit windows */
2196         for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
2197                 if (!(si->window_preserve_mask_64 & (1<<i)))
2198                         mv64360_disable_window_64bit(bh, i);
2199
2200         /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2201         mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2202         mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2203         mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2204         mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2205
2206         /* Disable all PCI-><whatever> windows */
2207         mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2208         mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2209 }
2210
2211 /*
2212  * mv64360_config_io2mem_windows()
2213  *
2214  * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2215  * must be set up so that the respective ctlr can access system memory.
2216  */
2217 static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2218         MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
2219         MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
2220 };
2221
2222 static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2223         MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
2224         MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
2225 };
2226
2227 static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2228         MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
2229         MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
2230 };
2231
2232 static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
2233         { 0xe, 0xd, 0xb, 0x7 };
2234
2235 static void __init
2236 mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2237         struct mv64x60_setup_info *si,
2238         u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
2239 {
2240         u32     i, win;
2241
2242         pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2243
2244         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
2245         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
2246         mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
2247
2248         mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
2249         mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
2250
2251         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
2252         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
2253         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
2254         mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
2255
2256         /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2257         for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
2258                 if (bh->ci->is_enabled_32bit(bh, win)) {
2259                         mv64x60_set_32bit_window(bh, enet_tab[i],
2260                                 mem_windows[i][0], mem_windows[i][1],
2261                                 (dram_selects[i] << 8) |
2262                                 (si->enet_options[i] & 0x3000));
2263                         bh->ci->enable_window_32bit(bh, enet_tab[i]);
2264
2265                         /* Give enet r/w access to memory region */
2266                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
2267                                 (0x3 << (i << 1)));
2268                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
2269                                 (0x3 << (i << 1)));
2270                         mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
2271                                 (0x3 << (i << 1)));
2272
2273                         mv64x60_set_32bit_window(bh, mpsc_tab[i],
2274                                 mem_windows[i][0], mem_windows[i][1],
2275                                 (dram_selects[i] << 8) |
2276                                 (si->mpsc_options[i] & 0x3000));
2277                         bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
2278
2279                         /* Give mpsc r/w access to memory region */
2280                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
2281                                 (0x3 << (i << 1)));
2282                         mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
2283                                 (0x3 << (i << 1)));
2284
2285                         mv64x60_set_32bit_window(bh, idma_tab[i],
2286                                 mem_windows[i][0], mem_windows[i][1],
2287                                 (dram_selects[i] << 8) |
2288                                 (si->idma_options[i] & 0x3000));
2289                         bh->ci->enable_window_32bit(bh, idma_tab[i]);
2290
2291                         /* Give idma r/w access to memory region */
2292                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
2293                                 (0x3 << (i << 1)));
2294                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
2295                                 (0x3 << (i << 1)));
2296                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
2297                                 (0x3 << (i << 1)));
2298                         mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2299                                 (0x3 << (i << 1)));
2300                 }
2301 }
2302
2303 /*
2304  * mv64360_set_mpsc2regs_window()
2305  *
2306  * MPSC has a window to the bridge's internal registers.  Call this routine
2307  * to change that window so it doesn't conflict with the windows mapping the
2308  * mpsc to system memory.
2309  */
2310 static void __init
2311 mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2312 {
2313         pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2314         mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2315 }
2316
2317 /*
2318  * mv64360_chip_specific_init()
2319  *
2320  * Implement errata workarounds for the MV64360.
2321  */
2322 static void __init
2323 mv64360_chip_specific_init(struct mv64x60_handle *bh,
2324         struct mv64x60_setup_info *si)
2325 {
2326 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2327         mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24));
2328 #endif
2329 #ifdef CONFIG_SERIAL_MPSC
2330         mv64x60_mpsc0_pdata.brg_can_tune = 1;
2331         mv64x60_mpsc0_pdata.cache_mgmt = 1;
2332         mv64x60_mpsc1_pdata.brg_can_tune = 1;
2333         mv64x60_mpsc1_pdata.cache_mgmt = 1;
2334 #endif
2335 }
2336
2337 /*
2338  * mv64460_chip_specific_init()
2339  *
2340  * Implement errata workarounds for the MV64460.
2341  */
2342 static void __init
2343 mv64460_chip_specific_init(struct mv64x60_handle *bh,
2344         struct mv64x60_setup_info *si)
2345 {
2346 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2347         mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25));
2348         mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4));
2349 #endif
2350 #ifdef CONFIG_SERIAL_MPSC
2351         mv64x60_mpsc0_pdata.brg_can_tune = 1;
2352         mv64x60_mpsc0_pdata.cache_mgmt = 1;
2353         mv64x60_mpsc1_pdata.brg_can_tune = 1;
2354         mv64x60_mpsc1_pdata.cache_mgmt = 1;
2355 #endif
2356 }
2357
2358
2359 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2360 /* Export the hotswap register via sysfs for enum event monitoring */
2361 #define VAL_LEN_MAX     11 /* 32-bit hex or dec stringified number + '\n' */
2362
2363 static DEFINE_MUTEX(mv64xxx_hs_lock);
2364
2365 static ssize_t
2366 mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
2367 {
2368         u32     v;
2369         u8      save_exclude;
2370
2371         if (off > 0)
2372                 return 0;
2373         if (count < VAL_LEN_MAX)
2374                 return -EINVAL;
2375
2376         if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2377                 return -ERESTARTSYS;
2378         save_exclude = mv64x60_pci_exclude_bridge;
2379         mv64x60_pci_exclude_bridge = 0;
2380         early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2381                         MV64360_PCICFG_CPCI_HOTSWAP, &v);
2382         mv64x60_pci_exclude_bridge = save_exclude;
2383         mutex_unlock(&mv64xxx_hs_lock);
2384
2385         return sprintf(buf, "0x%08x\n", v);
2386 }
2387
2388 static ssize_t
2389 mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
2390 {
2391         u32     v;
2392         u8      save_exclude;
2393
2394         if (off > 0)
2395                 return 0;
2396         if (count <= 0)
2397                 return -EINVAL;
2398
2399         if (sscanf(buf, "%i", &v) == 1) {
2400                 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2401                         return -ERESTARTSYS;
2402                 save_exclude = mv64x60_pci_exclude_bridge;
2403                 mv64x60_pci_exclude_bridge = 0;
2404                 early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2405                                 MV64360_PCICFG_CPCI_HOTSWAP, v);
2406                 mv64x60_pci_exclude_bridge = save_exclude;
2407                 mutex_unlock(&mv64xxx_hs_lock);
2408         }
2409         else
2410                 count = -EINVAL;
2411
2412         return count;
2413 }
2414
2415 static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */
2416         .attr = {
2417                 .name = "hs_reg",
2418                 .mode = S_IRUGO | S_IWUSR,
2419         },
2420         .size  = VAL_LEN_MAX,
2421         .read  = mv64xxx_hs_reg_read,
2422         .write = mv64xxx_hs_reg_write,
2423 };
2424
2425 /* Provide sysfs file indicating if this platform supports the hs_reg */
2426 static ssize_t
2427 mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr,
2428                 char *buf)
2429 {
2430         struct platform_device  *pdev;
2431         struct mv64xxx_pdata    *pdp;
2432         u32                     v;
2433
2434         pdev = container_of(dev, struct platform_device, dev);
2435         pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data;
2436
2437         if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2438                 return -ERESTARTSYS;
2439         v = pdp->hs_reg_valid;
2440         mutex_unlock(&mv64xxx_hs_lock);
2441
2442         return sprintf(buf, "%i\n", v);
2443 }
2444 static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL);
2445
2446 static int __init
2447 mv64xxx_sysfs_init(void)
2448 {
2449         sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr);
2450         sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr);
2451         return 0;
2452 }
2453 subsys_initcall(mv64xxx_sysfs_init);
2454 #endif