2 * arch/ppc/syslib/mpc52xx_pci.c
4 * PCI code for the Freescale MPC52xx embedded CPU.
7 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
9 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
16 #include <linux/config.h>
20 #include <asm/mpc52xx.h>
21 #include "mpc52xx_pci.h"
23 #include <asm/delay.h>
24 #include <asm/machdep.h>
27 /* This macro is defined to activate the workaround for the bug
28 435 of the MPC5200 (L25R). With it activated, we don't do any
29 32 bits configuration access during type-1 cycles */
30 #define MPC5200_BUG_435_WORKAROUND
34 mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
35 int offset, int len, u32 *val)
37 struct pci_controller *hose = bus->sysdata;
40 if (ppc_md.pci_exclude_device)
41 if (ppc_md.pci_exclude_device(bus->number, devfn))
42 return PCIBIOS_DEVICE_NOT_FOUND;
44 out_be32(hose->cfg_addr,
46 ((bus->number - hose->bus_offset) << 16) |
51 #ifdef MPC5200_BUG_435_WORKAROUND
52 if (bus->number != hose->bus_offset) {
55 value = in_8(((u8 __iomem *)hose->cfg_data) + (offset & 3));
58 value = in_le16(((u16 __iomem *)hose->cfg_data) + ((offset>>1) & 1));
62 value = in_le16((u16 __iomem *)hose->cfg_data) |
63 (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
70 value = in_le32(hose->cfg_data);
73 value >>= ((offset & 0x3) << 3);
74 value &= 0xffffffff >> (32 - (len << 3));
80 out_be32(hose->cfg_addr, 0);
83 return PCIBIOS_SUCCESSFUL;
87 mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
88 int offset, int len, u32 val)
90 struct pci_controller *hose = bus->sysdata;
93 if (ppc_md.pci_exclude_device)
94 if (ppc_md.pci_exclude_device(bus->number, devfn))
95 return PCIBIOS_DEVICE_NOT_FOUND;
97 out_be32(hose->cfg_addr,
99 ((bus->number - hose->bus_offset) << 16) |
104 #ifdef MPC5200_BUG_435_WORKAROUND
105 if (bus->number != hose->bus_offset) {
108 out_8(((u8 __iomem *)hose->cfg_data) +
112 out_le16(((u16 __iomem *)hose->cfg_data) +
113 ((offset>>1) & 1), val);
117 out_le16((u16 __iomem *)hose->cfg_data,
119 out_le16(((u16 __iomem *)hose->cfg_data) + 1,
128 value = in_le32(hose->cfg_data);
130 offset = (offset & 0x3) << 3;
131 mask = (0xffffffff >> (32 - (len << 3)));
135 val = value | ((val << offset) & mask);
138 out_le32(hose->cfg_data, val);
142 out_be32(hose->cfg_addr, 0);
145 return PCIBIOS_SUCCESSFUL;
148 static struct pci_ops mpc52xx_pci_ops = {
149 .read = mpc52xx_pci_read_config,
150 .write = mpc52xx_pci_write_config
155 mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
158 /* Setup control regs */
159 /* Nothing to do afaik */
162 out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
163 MPC52xx_PCI_MEM_START + MPC52xx_PCI_MEM_OFFSET,
164 MPC52xx_PCI_MEM_START,
165 MPC52xx_PCI_MEM_SIZE ));
167 out_be32(&pci_regs->iw1btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
168 MPC52xx_PCI_MMIO_START + MPC52xx_PCI_MEM_OFFSET,
169 MPC52xx_PCI_MMIO_START,
170 MPC52xx_PCI_MMIO_SIZE ));
172 out_be32(&pci_regs->iw2btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
174 MPC52xx_PCI_IO_START,
175 MPC52xx_PCI_IO_SIZE ));
177 out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(
178 ( MPC52xx_PCI_IWCR_ENABLE | /* iw0btar */
179 MPC52xx_PCI_IWCR_READ_MULTI |
180 MPC52xx_PCI_IWCR_MEM ),
181 ( MPC52xx_PCI_IWCR_ENABLE | /* iw1btar */
182 MPC52xx_PCI_IWCR_READ |
183 MPC52xx_PCI_IWCR_MEM ),
184 ( MPC52xx_PCI_IWCR_ENABLE | /* iw2btar */
185 MPC52xx_PCI_IWCR_IO )
189 out_be32(&pci_regs->tbatr0,
190 MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
191 out_be32(&pci_regs->tbatr1,
192 MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
194 out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
196 /* Reset the exteral bus ( internal PCI controller is NOT resetted ) */
197 /* Not necessary and can be a bad thing if for example the bootloader
198 is displaying a splash screen or ... Just left here for
199 documentation purpose if anyone need it */
202 tmp = in_be32(&pci_regs->gscr);
203 out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
205 out_be32(&pci_regs->gscr, tmp);
210 mpc52xx_pci_fixup_resources(struct pci_dev *dev)
214 /* We don't rely on boot loader for PCI and resets all
216 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
217 struct resource *res = &dev->resource[i];
218 if (res->end > res->start) { /* Only valid resources */
219 res->end -= res->start;
221 res->flags |= IORESOURCE_UNSET;
225 /* The PCI Host bridge of MPC52xx has a prefetch memory resource
226 fixed to 1Gb. Doesn't fit in the resource system so we remove it */
227 if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
228 (dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200) ) {
229 struct resource *res = &dev->resource[1];
230 res->start = res->end = res->flags = 0;
235 mpc52xx_find_bridges(void)
237 struct mpc52xx_pci __iomem *pci_regs;
238 struct pci_controller *hose;
240 pci_assign_all_buses = 1;
242 pci_regs = ioremap(MPC52xx_PA(MPC52xx_PCI_OFFSET), MPC52xx_PCI_SIZE);
246 hose = pcibios_alloc_controller();
252 ppc_md.pci_swizzle = common_swizzle;
253 ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
255 hose->first_busno = 0;
256 hose->last_busno = 0xff;
257 hose->bus_offset = 0;
258 hose->ops = &mpc52xx_pci_ops;
260 mpc52xx_pci_setup(pci_regs);
262 hose->pci_mem_offset = MPC52xx_PCI_MEM_OFFSET;
264 hose->io_base_virt = ioremap(MPC52xx_PCI_IO_BASE, MPC52xx_PCI_IO_SIZE);
265 isa_io_base = (unsigned long) hose->io_base_virt;
267 hose->cfg_addr = &pci_regs->car;
268 hose->cfg_data = hose->io_base_virt;
270 /* Setup resources */
271 pci_init_resource(&hose->mem_resources[0],
272 MPC52xx_PCI_MEM_START,
273 MPC52xx_PCI_MEM_STOP,
274 IORESOURCE_MEM|IORESOURCE_PREFETCH,
275 "PCI prefetchable memory");
277 pci_init_resource(&hose->mem_resources[1],
278 MPC52xx_PCI_MMIO_START,
279 MPC52xx_PCI_MMIO_STOP,
283 pci_init_resource(&hose->io_resource,
284 MPC52xx_PCI_IO_START,