4 * arch/ppc/platforms/82xx/pq2ads_pd.h
6 * Some defines for MPC82xx board-specific PlatformDevice descriptions
8 * 2005 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
16 /* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
17 Can only choose from CLK9-12 */
22 /* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
23 Can only choose from CLK13-16 */
27 /* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
28 Can only choose from CLK13-16 */
32 /* Automatically generates register configurations */
33 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
35 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
36 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
37 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
38 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
39 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
40 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
42 #define PC_F1RXCLK PC_CLK(F1_RXCLK)
43 #define PC_F1TXCLK PC_CLK(F1_TXCLK)
44 #define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
45 #define CMX1_CLK_MASK ((uint)0xff000000)
47 #define PC_F2RXCLK PC_CLK(F2_RXCLK)
48 #define PC_F2TXCLK PC_CLK(F2_TXCLK)
49 #define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
50 #define CMX2_CLK_MASK ((uint)0x00ff0000)
52 #define PC_F3RXCLK PC_CLK(F3_RXCLK)
53 #define PC_F3TXCLK PC_CLK(F3_TXCLK)
54 #define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
55 #define CMX3_CLK_MASK ((uint)0x0000ff00)
57 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
58 * but there is little variation among the choices.
60 #define PA1_COL 0x00000001U
61 #define PA1_CRS 0x00000002U
62 #define PA1_TXER 0x00000004U
63 #define PA1_TXEN 0x00000008U
64 #define PA1_RXDV 0x00000010U
65 #define PA1_RXER 0x00000020U
66 #define PA1_TXDAT 0x00003c00U
67 #define PA1_RXDAT 0x0003c000U
68 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
69 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
71 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
72 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
75 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
76 * but there is little variation among the choices.
78 #define PB2_TXER 0x00000001U
79 #define PB2_RXDV 0x00000002U
80 #define PB2_TXEN 0x00000004U
81 #define PB2_RXER 0x00000008U
82 #define PB2_COL 0x00000010U
83 #define PB2_CRS 0x00000020U
84 #define PB2_TXDAT 0x000003c0U
85 #define PB2_RXDAT 0x00003c00U
86 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
87 PB2_RXER | PB2_RXDV | PB2_TXER)
88 #define PB2_PSORB1 (PB2_TXEN)
89 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
90 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
93 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
94 * but there is little variation among the choices.
96 #define PB3_RXDV 0x00004000U
97 #define PB3_RXER 0x00008000U
98 #define PB3_TXER 0x00010000U
99 #define PB3_TXEN 0x00020000U
100 #define PB3_COL 0x00040000U
101 #define PB3_CRS 0x00080000U
102 #define PB3_TXDAT 0x0f000000U
103 #define PB3_RXDAT 0x00f00000U
104 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
105 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
107 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
108 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
110 #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
111 #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
112 #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)