2 * MPC85xx CDS board specific routines
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * Copyright 2004 Freescale Semiconductor, Inc
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/config.h>
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/reboot.h>
20 #include <linux/pci.h>
21 #include <linux/kdev_t.h>
22 #include <linux/major.h>
23 #include <linux/console.h>
24 #include <linux/delay.h>
25 #include <linux/seq_file.h>
26 #include <linux/serial.h>
27 #include <linux/module.h>
28 #include <linux/root_dev.h>
29 #include <linux/initrd.h>
30 #include <linux/tty.h>
31 #include <linux/serial_core.h>
32 #include <linux/fsl_devices.h>
34 #include <asm/system.h>
35 #include <asm/pgtable.h>
37 #include <asm/atomic.h>
41 #include <asm/machdep.h>
42 #include <asm/open_pic.h>
43 #include <asm/i8259.h>
44 #include <asm/bootinfo.h>
45 #include <asm/pci-bridge.h>
46 #include <asm/mpc85xx.h>
48 #include <asm/immap_85xx.h>
50 #include <asm/ppc_sys.h>
53 #include <mm/mmu_decl.h>
54 #include <syslib/cpm2_pic.h>
55 #include <syslib/ppc85xx_common.h>
56 #include <syslib/ppc85xx_setup.h>
60 unsigned long isa_io_base = 0;
61 unsigned long isa_mem_base = 0;
64 extern unsigned long total_memory; /* in mm/init */
66 unsigned char __res[sizeof (bd_t)];
68 static int cds_pci_slot = 2;
69 static volatile u8 * cadmus;
71 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
72 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
73 MPC85XX_INTERNAL_IRQ_SENSES,
74 #if defined(CONFIG_PCI)
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
80 0x0, /* External 0: */
81 0x0, /* External 1: */
82 0x0, /* External 2: */
83 0x0, /* External 3: */
85 0x0, /* External 4: */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
87 0x0, /* External 6: */
88 0x0, /* External 7: */
89 0x0, /* External 8: */
90 0x0, /* External 9: */
91 0x0, /* External 10: */
92 #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
95 0x0, /* External 11: */
99 /* ************************************************************************ */
101 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
103 uint pvid, svid, phid1;
104 uint memsize = total_memory;
105 bd_t *binfo = (bd_t *) __res;
108 /* get the core frequency */
109 freq = binfo->bi_intfreq;
111 pvid = mfspr(SPRN_PVR);
112 svid = mfspr(SPRN_SVR);
114 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
115 seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
116 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
117 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
118 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
120 /* Display cpu Pll setting */
121 phid1 = mfspr(SPRN_HID1);
122 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
124 /* Display the amount of memory */
125 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
131 static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
133 while((irq = cpm2_get_irq(regs)) >= 0)
138 static struct irqaction cpm2_irqaction = {
139 .handler = cpm2_cascade,
140 .flags = SA_INTERRUPT,
141 .mask = CPU_MASK_NONE,
142 .name = "cpm2_cascade",
144 #endif /* CONFIG_CPM2 */
147 mpc85xx_cds_init_IRQ(void)
149 bd_t *binfo = (bd_t *) __res;
152 /* Determine the Physical Address of the OpenPIC regs */
153 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
154 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
155 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
156 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
158 /* Skip reserved space and internal sources */
159 #ifdef CONFIG_MPC8548
160 openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
162 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
164 /* Map PIC IRQs 0-11 */
165 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
167 /* we let openpic interrupts starting from an offset, to
168 * leave space for cascading interrupts underneath.
170 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
173 openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
182 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
193 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
195 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
199 /* Handle PCI1 interrupts */
200 char pci_irq_table[][4] =
202 * PCI IDSEL/INTPIN->INTLINE
206 /* Note IRQ assignment for slots is based on which slot the elysium is
207 * in -- in this setup elysium is in slot #2 (this PIRQA as first
208 * interrupt on slot */
210 { 0, 1, 2, 3 }, /* 16 - PMC */
211 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
212 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
213 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
214 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
215 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
218 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
221 for (i = 0; i < 6; i++)
222 for (j = 0; j < 4; j++)
223 pci_irq_table[i][j] =
224 ((pci_irq_table[i][j] + 5 -
225 cds_pci_slot) & 0x3) + PIRQ0A;
227 return PCI_IRQ_TABLE_LOOKUP;
229 /* Handle PCI2 interrupts (if we have one) */
230 char pci_irq_table[][4] =
233 * We only have one slot and one interrupt
234 * going to PIRQA - PIRQD */
235 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
238 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
240 return PCI_IRQ_TABLE_LOOKUP;
244 #define ARCADIA_HOST_BRIDGE_IDSEL 17
245 #define ARCADIA_2ND_BRIDGE_IDSEL 3
247 extern int mpc85xx_pci1_last_busno;
250 mpc85xx_exclude_device(u_char bus, u_char devfn)
252 if (bus == 0 && PCI_SLOT(devfn) == 0)
253 return PCIBIOS_DEVICE_NOT_FOUND;
254 #ifdef CONFIG_85xx_PCI2
255 if (mpc85xx_pci1_last_busno)
256 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
257 return PCIBIOS_DEVICE_NOT_FOUND;
259 /* We explicitly do not go past the Tundra 320 Bridge */
260 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
261 return PCIBIOS_DEVICE_NOT_FOUND;
262 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
263 return PCIBIOS_DEVICE_NOT_FOUND;
265 return PCIBIOS_SUCCESSFUL;
269 mpc85xx_cds_enable_via(struct pci_controller *hose)
274 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
275 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
278 /* Configure P2P so that we can reach bus 1 */
279 early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
280 early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
281 early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
283 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
284 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
286 if ((vid != PCI_VENDOR_ID_VIA) ||
287 (did != PCI_DEVICE_ID_VIA_82C686))
290 /* Enable USB and IDE functions */
291 early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
295 mpc85xx_cds_fixup_via(struct pci_controller *hose)
300 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
301 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
305 * Force the backplane P2P bridge to have a window
306 * open from 0x00000000-0x00001fff in PCI I/O space.
307 * This allows legacy I/O (i8259, etc) on the VIA
308 * southbridge to be accessed.
310 early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
311 early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
312 early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
313 early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
315 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
316 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
317 if ((vid != PCI_VENDOR_ID_VIA) ||
318 (did != PCI_DEVICE_ID_VIA_82C686))
322 * Since the P2P window was forced to cover the fixed
323 * legacy I/O addresses, it is necessary to manually
324 * place the base addresses for the IDE and USB functions
325 * within this window.
327 /* Function 1, IDE */
328 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
329 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
330 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
331 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
332 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
334 /* Function 2, USB ports 0-1 */
335 early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
337 /* Function 3, USB ports 2-3 */
338 early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
340 /* Function 5, Power Management */
341 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
342 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
343 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
345 /* Function 6, AC97 Interface */
346 early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
350 mpc85xx_cds_pcibios_fixup(void)
355 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
356 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
358 * U-Boot does not set the enable bits
359 * for the IDE device. Force them on here.
361 pci_read_config_byte(dev, 0x40, &c);
362 c |= 0x03; /* IDE: Chip Enable Bits */
363 pci_write_config_byte(dev, 0x40, c);
366 * Since only primary interface works, force the
367 * IDE function to standard primary IDE interrupt
371 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
376 * Force legacy USB interrupt routing
378 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
379 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
381 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
385 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
386 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
388 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
392 #endif /* CONFIG_PCI */
396 /* ************************************************************************
398 * Setup the architecture
402 mpc85xx_cds_setup_arch(void)
404 bd_t *binfo = (bd_t *) __res;
406 struct gianfar_platform_data *pdata;
407 struct gianfar_mdio_data *mdata;
409 /* get the core frequency */
410 freq = binfo->bi_intfreq;
412 printk("mpc85xx_cds_setup_arch\n");
418 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
419 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
420 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
422 /* Setup TODC access */
423 TODC_INIT(TODC_TYPE_DS1743,
426 ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
429 /* Set loops_per_jiffy to a half-way reasonable value,
430 for use until calibrate_delay gets called. */
431 loops_per_jiffy = freq / HZ;
434 /* VIA IDE configuration */
435 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
437 /* setup PCI host bridges */
438 mpc85xx_setup_hose();
441 #ifdef CONFIG_SERIAL_8250
442 mpc85xx_early_serial_map();
445 #ifdef CONFIG_SERIAL_TEXT_DEBUG
446 /* Invalidate the entry we stole earlier the serial ports
447 * should be properly mapped */
448 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
451 /* setup the board related info for the MDIO bus */
452 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
454 mdata->irq[0] = MPC85xx_IRQ_EXT5;
455 mdata->irq[1] = MPC85xx_IRQ_EXT5;
460 /* setup the board related information for the enet controllers */
461 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
463 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
466 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
469 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
471 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
474 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
477 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
479 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
482 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
485 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
487 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
490 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
493 ppc_sys_device_remove(MPC85xx_eTSEC3);
494 ppc_sys_device_remove(MPC85xx_eTSEC4);
496 #ifdef CONFIG_BLK_DEV_INITRD
498 ROOT_DEV = Root_RAM0;
501 #ifdef CONFIG_ROOT_NFS
504 ROOT_DEV = Root_HDA1;
508 /* ************************************************************************ */
510 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
511 unsigned long r6, unsigned long r7)
513 /* parse_bootinfo must always be called first */
514 parse_bootinfo(find_bootinfo());
517 * If we were passed in a board information, copy it into the
518 * residual data area.
521 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
525 #ifdef CONFIG_SERIAL_TEXT_DEBUG
527 bd_t *binfo = (bd_t *) __res;
530 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
531 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
532 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
534 memset(&p, 0, sizeof (p));
536 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
537 p.uartclk = binfo->bi_busfreq;
541 memset(&p, 0, sizeof (p));
543 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
544 p.uartclk = binfo->bi_busfreq;
550 #if defined(CONFIG_BLK_DEV_INITRD)
552 * If the init RAM disk has been configured in, and there's a valid
553 * starting address for it, set it up.
556 initrd_start = r4 + KERNELBASE;
557 initrd_end = r5 + KERNELBASE;
559 #endif /* CONFIG_BLK_DEV_INITRD */
561 /* Copy the kernel command line arguments to a safe place. */
564 *(char *) (r7 + KERNELBASE) = 0;
565 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
568 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
570 /* setup the PowerPC module struct */
571 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
572 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
574 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
575 ppc_md.get_irq = openpic_get_irq;
577 ppc_md.restart = mpc85xx_restart;
578 ppc_md.power_off = mpc85xx_power_off;
579 ppc_md.halt = mpc85xx_halt;
581 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
583 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
585 ppc_md.time_init = todc_time_init;
586 ppc_md.set_rtc_time = todc_set_rtc_time;
587 ppc_md.get_rtc_time = todc_get_rtc_time;
589 ppc_md.nvram_read_val = todc_direct_read_val;
590 ppc_md.nvram_write_val = todc_direct_write_val;
592 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
593 ppc_md.progress = gen550_progress;
594 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
595 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
596 ppc_md.early_serial_map = mpc85xx_early_serial_map;
597 #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
600 ppc_md.progress("mpc85xx_cds_init(): exit", 0);