2 * Author: Armin Kuster <akuster@mvista.com>
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/smp.h>
13 #include <linux/threads.h>
14 #include <linux/param.h>
15 #include <linux/string.h>
16 #include <platforms/4xx/ibm405gpr.h>
17 #include <asm/ibm4xx.h>
19 #include <asm/ppc4xx_pic.h>
21 static struct ocp_func_emac_data ibm405gpr_emac0_def = {
22 .rgmii_idx = -1, /* No RGMII */
23 .rgmii_mux = -1, /* No RGMII */
24 .zmii_idx = -1, /* ZMII device index */
25 .zmii_mux = 0, /* ZMII input of this EMAC */
26 .mal_idx = 0, /* MAL device index */
27 .mal_rx_chan = 0, /* MAL rx channel number */
28 .mal_tx_chan = 0, /* MAL tx channel number */
29 .wol_irq = 9, /* WOL interrupt number */
30 .mdio_idx = -1, /* No shared MDIO */
31 .tah_idx = -1, /* No TAH */
35 static struct ocp_func_mal_data ibm405gpr_mal0_def = {
36 .num_tx_chans = 1, /* Number of TX channels */
37 .num_rx_chans = 1, /* Number of RX channels */
38 .txeob_irq = 11, /* TX End Of Buffer IRQ */
39 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
40 .txde_irq = 13, /* TX Descriptor Error IRQ */
41 .rxde_irq = 14, /* RX Descriptor Error IRQ */
42 .serr_irq = 10, /* MAL System Error IRQ */
43 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
47 static struct ocp_func_iic_data ibm405gpr_iic0_def = {
48 .fast_mode = 0, /* Use standad mode (100Khz) */
53 struct ocp_def core_ocp[] = {
54 { .vendor = OCP_VENDOR_IBM,
55 .function = OCP_FUNC_OPB,
61 { .vendor = OCP_VENDOR_IBM,
62 .function = OCP_FUNC_16550,
64 .paddr = UART0_IO_BASE,
68 { .vendor = OCP_VENDOR_IBM,
69 .function = OCP_FUNC_16550,
71 .paddr = UART1_IO_BASE,
75 { .vendor = OCP_VENDOR_IBM,
76 .function = OCP_FUNC_IIC,
80 .additions = &ibm405gpr_iic0_def,
81 .show = &ocp_show_iic_data,
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_GPIO,
89 { .vendor = OCP_VENDOR_IBM,
90 .function = OCP_FUNC_MAL,
91 .paddr = OCP_PADDR_NA,
94 .additions = &ibm405gpr_mal0_def,
95 .show = &ocp_show_mal_data,
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_EMAC,
103 .additions = &ibm405gpr_emac0_def,
104 .show = &ocp_show_emac_data,
106 { .vendor = OCP_VENDOR_INVALID
110 /* Polarity and triggering settings for internal interrupt sources */
111 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
112 { .polarity = 0xffffe000,
113 .triggering = 0x10000000,
114 .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */