err.no Git - linux-2.6/blob - arch/ppc/kernel/cputable.c

   1 /*
   2  *  arch/ppc/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/threads.h>
  16 #include <linux/init.h>
  17 #include <asm/cputable.h>
  18
  19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
  20
  21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  33 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  34
  35 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  36                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
  37                      !defined(CONFIG_BOOKE))
  38
  39 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  40  * ones as well...
  41  */
  42 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  43                          PPC_FEATURE_HAS_MMU)
  44
  45 /* We only set the altivec features if the kernel was compiled with altivec
  46  * support
  47  */
  48 #ifdef CONFIG_ALTIVEC
  49 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
  50 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
  51 #else
  52 #define CPU_FTR_ALTIVEC_COMP            0
  53 #define PPC_FEATURE_ALTIVEC_COMP        0
  54 #endif
  55
  56 /* We only set the spe features if the kernel was compiled with
  57  * spe support
  58  */
  59 #ifdef CONFIG_SPE
  60 #define PPC_FEATURE_SPE_COMP            PPC_FEATURE_HAS_SPE
  61 #else
  62 #define PPC_FEATURE_SPE_COMP            0
  63 #endif
  64
  65 /* We need to mark all pages as being coherent if we're SMP or we
  66  * have a 74[45]x and an MPC107 host bridge.
  67  */
  68 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
  69 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  70 #else
  71 #define CPU_FTR_COMMON                  0
  72 #endif
  73
  74 /* The powersave features NAP & DOZE seems to confuse BDI when
  75    debugging. So if a BDI is used, disable theses
  76  */
  77 #ifndef CONFIG_BDI_SWITCH
  78 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
  79 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
  80 #else
  81 #define CPU_FTR_MAYBE_CAN_DOZE  0
  82 #define CPU_FTR_MAYBE_CAN_NAP   0
  83 #endif
  84
  85 struct cpu_spec cpu_specs[] = {
  86 #if CLASSIC_PPC
  87         {       /* 601 */
  88                 .pvr_mask               = 0xffff0000,
  89                 .pvr_value              = 0x00010000,
  90                 .cpu_name               = "601",
  91                 .cpu_features           = CPU_FTR_COMMON | CPU_FTR_601 |
  92                         CPU_FTR_HPTE_TABLE,
  93                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_601_INSTR |
  94                         PPC_FEATURE_UNIFIED_CACHE,
  95                 .icache_bsize           = 32,
  96                 .dcache_bsize           = 32,
  97                 .cpu_setup              = __setup_cpu_601
  98         },
  99         {       /* 603 */
 100                 .pvr_mask               = 0xffff0000,
 101                 .pvr_value              = 0x00030000,
 102                 .cpu_name               = "603",
 103                 .cpu_features           = CPU_FTR_COMMON |
 104                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 105                         CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
 106                 .cpu_user_features      = COMMON_PPC,
 107                 .icache_bsize           = 32,
 108                 .dcache_bsize           = 32,
 109                 .cpu_setup              = __setup_cpu_603
 110         },
 111         {       /* 603e */
 112                 .pvr_mask               = 0xffff0000,
 113                 .pvr_value              = 0x00060000,
 114                 .cpu_name               = "603e",
 115                 .cpu_features           = CPU_FTR_COMMON |
 116                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 117                         CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
 118                 .cpu_user_features      = COMMON_PPC,
 119                 .icache_bsize           = 32,
 120                 .dcache_bsize           = 32,
 121                 .cpu_setup              = __setup_cpu_603
 122         },
 123         {       /* 603ev */
 124                 .pvr_mask               = 0xffff0000,
 125                 .pvr_value              = 0x00070000,
 126                 .cpu_name               = "603ev",
 127                 .cpu_features           = CPU_FTR_COMMON |
 128                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 129                         CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
 130                 .cpu_user_features      = COMMON_PPC,
 131                 .icache_bsize           = 32,
 132                 .dcache_bsize           = 32,
 133                 .cpu_setup              = __setup_cpu_603
 134         },
 135         {       /* 604 */
 136                 .pvr_mask               = 0xffff0000,
 137                 .pvr_value              = 0x00040000,
 138                 .cpu_name               = "604",
 139                 .cpu_features           = CPU_FTR_COMMON |
 140                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 141                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
 142                 .cpu_user_features      = COMMON_PPC,
 143                 .icache_bsize           = 32,
 144                 .dcache_bsize           = 32,
 145                 .num_pmcs               = 2,
 146                 .cpu_setup              = __setup_cpu_604
 147         },
 148         {       /* 604e */
 149                 .pvr_mask               = 0xfffff000,
 150                 .pvr_value              = 0x00090000,
 151                 .cpu_name               = "604e",
 152                 .cpu_features           = CPU_FTR_COMMON |
 153                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 154                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
 155                 .cpu_user_features      = COMMON_PPC,
 156                 .icache_bsize           = 32,
 157                 .dcache_bsize           = 32,
 158                 .num_pmcs               = 4,
 159                 .cpu_setup              = __setup_cpu_604
 160         },
 161         {       /* 604r */
 162                 .pvr_mask               = 0xffff0000,
 163                 .pvr_value              = 0x00090000,
 164                 .cpu_name               = "604r",
 165                 .cpu_features           = CPU_FTR_COMMON |
 166                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 167                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
 168                 .cpu_user_features      = COMMON_PPC,
 169                 .icache_bsize           = 32,
 170                 .dcache_bsize           = 32,
 171                 .num_pmcs               = 4,
 172                 .cpu_setup              = __setup_cpu_604
 173         },
 174         {       /* 604ev */
 175                 .pvr_mask               = 0xffff0000,
 176                 .pvr_value              = 0x000a0000,
 177                 .cpu_name               = "604ev",
 178                 .cpu_features           = CPU_FTR_COMMON |
 179                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 180                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
 181                 .cpu_user_features      = COMMON_PPC,
 182                 .icache_bsize           = 32,
 183                 .dcache_bsize           = 32,
 184                 .num_pmcs               = 4,
 185                 .cpu_setup              = __setup_cpu_604
 186         },
 187         {       /* 740/750 (0x4202, don't support TAU ?) */
 188                 .pvr_mask               = 0xffffffff,
 189                 .pvr_value              = 0x00084202,
 190                 .cpu_name               = "740/750",
 191                 .cpu_features           = CPU_FTR_COMMON |
 192                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 193                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
 194                         CPU_FTR_MAYBE_CAN_NAP,
 195                 .cpu_user_features      = COMMON_PPC,
 196                 .icache_bsize           = 32,
 197                 .dcache_bsize           = 32,
 198                 .num_pmcs               = 4,
 199                 .cpu_setup              = __setup_cpu_750
 200         },
 201         {       /* 750CX (80100 and 8010x?) */
 202                 .pvr_mask               = 0xfffffff0,
 203                 .pvr_value              = 0x00080100,
 204                 .cpu_name               = "750CX",
 205                 .cpu_features           = CPU_FTR_COMMON |
 206                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 207                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 208                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 209                 .cpu_user_features      = COMMON_PPC,
 210                 .icache_bsize           = 32,
 211                 .dcache_bsize           = 32,
 212                 .num_pmcs               = 4,
 213                 .cpu_setup              = __setup_cpu_750cx
 214         },
 215         {       /* 750CX (82201 and 82202) */
 216                 .pvr_mask               = 0xfffffff0,
 217                 .pvr_value              = 0x00082200,
 218                 .cpu_name               = "750CX",
 219                 .cpu_features           = CPU_FTR_COMMON |
 220                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 221                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 222                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 223                 .cpu_user_features      = COMMON_PPC,
 224                 .icache_bsize           = 32,
 225                 .dcache_bsize           = 32,
 226                 .num_pmcs               = 4,
 227                 .cpu_setup              = __setup_cpu_750cx
 228         },
 229         {       /* 750CXe (82214) */
 230                 .pvr_mask               = 0xfffffff0,
 231                 .pvr_value              = 0x00082210,
 232                 .cpu_name               = "750CXe",
 233                 .cpu_features           = CPU_FTR_COMMON |
 234                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 235                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 236                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 237                 .cpu_user_features      = COMMON_PPC,
 238                 .icache_bsize           = 32,
 239                 .dcache_bsize           = 32,
 240                 .num_pmcs               = 4,
 241                 .cpu_setup              = __setup_cpu_750cx
 242         },
 243         {       /* 750CXe "Gekko" (83214) */
 244                 .pvr_mask               = 0xffffffff,
 245                 .pvr_value              = 0x00083214,
 246                 .cpu_name               = "750CXe",
 247                 .cpu_features           = CPU_FTR_COMMON |
 248                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 249                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 250                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 251                 .cpu_user_features      = COMMON_PPC,
 252                 .icache_bsize           = 32,
 253                 .dcache_bsize           = 32,
 254                 .num_pmcs               = 4,
 255                 .cpu_setup              = __setup_cpu_750cx
 256         },
 257         {       /* 745/755 */
 258                 .pvr_mask               = 0xfffff000,
 259                 .pvr_value              = 0x00083000,
 260                 .cpu_name               = "745/755",
 261                 .cpu_features           = CPU_FTR_COMMON |
 262                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 263                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 264                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 265                 .cpu_user_features      = COMMON_PPC,
 266                 .icache_bsize           = 32,
 267                 .dcache_bsize           = 32,
 268                 .num_pmcs               = 4,
 269                 .cpu_setup              = __setup_cpu_750
 270         },
 271         {       /* 750FX rev 1.x */
 272                 .pvr_mask               = 0xffffff00,
 273                 .pvr_value              = 0x70000100,
 274                 .cpu_name               = "750FX",
 275                 .cpu_features           = CPU_FTR_COMMON |
 276                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 277                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 278                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 279                         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 280                 .cpu_user_features      = COMMON_PPC,
 281                 .icache_bsize           = 32,
 282                 .dcache_bsize           = 32,
 283                 .num_pmcs               = 4,
 284                 .cpu_setup              = __setup_cpu_750
 285         },
 286         {       /* 750FX rev 2.0 must disable HID0[DPM] */
 287                 .pvr_mask               = 0xffffffff,
 288                 .pvr_value              = 0x70000200,
 289                 .cpu_name               = "750FX",
 290                 .cpu_features           = CPU_FTR_COMMON |
 291                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 292                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 293                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 294                         CPU_FTR_NO_DPM,
 295                 .cpu_user_features      = COMMON_PPC,
 296                 .icache_bsize           = 32,
 297                 .dcache_bsize           = 32,
 298                 .num_pmcs               = 4,
 299                 .cpu_setup              = __setup_cpu_750
 300         },
 301         {       /* 750FX (All revs except 2.0) */
 302                 .pvr_mask               = 0xffff0000,
 303                 .pvr_value              = 0x70000000,
 304                 .cpu_name               = "750FX",
 305                 .cpu_features           = CPU_FTR_COMMON |
 306                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 307                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 308                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 309                         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 310                 .cpu_user_features      = COMMON_PPC,
 311                 .icache_bsize           = 32,
 312                 .dcache_bsize           = 32,
 313                 .num_pmcs               = 4,
 314                 .cpu_setup              = __setup_cpu_750fx
 315         },
 316         {       /* 750GX */
 317                 .pvr_mask               = 0xffff0000,
 318                 .pvr_value              = 0x70020000,
 319                 .cpu_name               = "750GX",
 320                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 321                         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 322                         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
 323                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
 324                         CPU_FTR_HAS_HIGH_BATS,
 325                 .cpu_user_features      = COMMON_PPC,
 326                 .icache_bsize           = 32,
 327                 .dcache_bsize           = 32,
 328                 .num_pmcs               = 4,
 329                 .cpu_setup              = __setup_cpu_750fx
 330         },
 331         {       /* 740/750 (L2CR bit need fixup for 740) */
 332                 .pvr_mask               = 0xffff0000,
 333                 .pvr_value              = 0x00080000,
 334                 .cpu_name               = "740/750",
 335                 .cpu_features           = CPU_FTR_COMMON |
 336                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 337                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 338                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 339                 .cpu_user_features      = COMMON_PPC,
 340                 .icache_bsize           = 32,
 341                 .dcache_bsize           = 32,
 342                 .num_pmcs               = 4,
 343                 .cpu_setup              = __setup_cpu_750
 344         },
 345         {       /* 7400 rev 1.1 ? (no TAU) */
 346                 .pvr_mask               = 0xffffffff,
 347                 .pvr_value              = 0x000c1101,
 348                 .cpu_name               = "7400 (1.1)",
 349                 .cpu_features           = CPU_FTR_COMMON |
 350                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 351                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 352                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 353                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 354                 .icache_bsize           = 32,
 355                 .dcache_bsize           = 32,
 356                 .num_pmcs               = 4,
 357                 .cpu_setup              = __setup_cpu_7400
 358         },
 359         {       /* 7400 */
 360                 .pvr_mask               = 0xffff0000,
 361                 .pvr_value              = 0x000c0000,
 362                 .cpu_name               = "7400",
 363                 .cpu_features           = CPU_FTR_COMMON |
 364                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 365                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 366                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 367                         CPU_FTR_MAYBE_CAN_NAP,
 368                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 369                 .icache_bsize           = 32,
 370                 .dcache_bsize           = 32,
 371                 .num_pmcs               = 4,
 372                 .cpu_setup              = __setup_cpu_7400
 373         },
 374         {       /* 7410 */
 375                 .pvr_mask               = 0xffff0000,
 376                 .pvr_value              = 0x800c0000,
 377                 .cpu_name               = "7410",
 378                 .cpu_features           = CPU_FTR_COMMON |
 379                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 380                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 381                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 382                         CPU_FTR_MAYBE_CAN_NAP,
 383                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 384                 .icache_bsize           = 32,
 385                 .dcache_bsize           = 32,
 386                 .num_pmcs               = 4,
 387                 .cpu_setup              = __setup_cpu_7410
 388         },
 389         {       /* 7450 2.0 - no doze/nap */
 390                 .pvr_mask               = 0xffffffff,
 391                 .pvr_value              = 0x80000200,
 392                 .cpu_name               = "7450",
 393                 .cpu_features           = CPU_FTR_COMMON |
 394                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 395                         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 396                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 397                         CPU_FTR_NEED_COHERENT,
 398                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 399                 .icache_bsize           = 32,
 400                 .dcache_bsize           = 32,
 401                 .num_pmcs               = 6,
 402                 .cpu_setup              = __setup_cpu_745x
 403         },
 404         {       /* 7450 2.1 */
 405                 .pvr_mask               = 0xffffffff,
 406                 .pvr_value              = 0x80000201,
 407                 .cpu_name               = "7450",
 408                 .cpu_features           = CPU_FTR_COMMON |
 409                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 410                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 411                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 412                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 413                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
 414                         CPU_FTR_NEED_COHERENT,
 415                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 416                 .icache_bsize           = 32,
 417                 .dcache_bsize           = 32,
 418                 .num_pmcs               = 6,
 419                 .cpu_setup              = __setup_cpu_745x
 420         },
 421         {       /* 7450 2.3 and newer */
 422                 .pvr_mask               = 0xffff0000,
 423                 .pvr_value              = 0x80000000,
 424                 .cpu_name               = "7450",
 425                 .cpu_features           = CPU_FTR_COMMON |
 426                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 427                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 428                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 429                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 430                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
 431                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 432                 .icache_bsize           = 32,
 433                 .dcache_bsize           = 32,
 434                 .num_pmcs               = 6,
 435                 .cpu_setup              = __setup_cpu_745x
 436         },
 437         {       /* 7455 rev 1.x */
 438                 .pvr_mask               = 0xffffff00,
 439                 .pvr_value              = 0x80010100,
 440                 .cpu_name               = "7455",
 441                 .cpu_features           = CPU_FTR_COMMON |
 442                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 443                         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 444                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 445                         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 446                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 447                 .icache_bsize           = 32,
 448                 .dcache_bsize           = 32,
 449                 .num_pmcs               = 6,
 450                 .cpu_setup              = __setup_cpu_745x
 451         },
 452         {       /* 7455 rev 2.0 */
 453                 .pvr_mask               = 0xffffffff,
 454                 .pvr_value              = 0x80010200,
 455                 .cpu_name               = "7455",
 456                 .cpu_features           = CPU_FTR_COMMON |
 457                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 458                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 459                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 460                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 461                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
 462                         CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 463                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 464                 .icache_bsize           = 32,
 465                 .dcache_bsize           = 32,
 466                 .num_pmcs               = 6,
 467                 .cpu_setup              = __setup_cpu_745x
 468         },
 469         {       /* 7455 others */
 470                 .pvr_mask               = 0xffff0000,
 471                 .pvr_value              = 0x80010000,
 472                 .cpu_name               = "7455",
 473                 .cpu_features           = CPU_FTR_COMMON |
 474                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 475                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 476                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 477                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 478                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 479                         CPU_FTR_NEED_COHERENT,
 480                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 481                 .icache_bsize           = 32,
 482                 .dcache_bsize           = 32,
 483                 .num_pmcs               = 6,
 484                 .cpu_setup              = __setup_cpu_745x
 485         },
 486         {       /* 7447/7457 Rev 1.0 */
 487                 .pvr_mask               = 0xffffffff,
 488                 .pvr_value              = 0x80020100,
 489                 .cpu_name               = "7447/7457",
 490                 .cpu_features           = CPU_FTR_COMMON |
 491                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 492                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 493                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 494                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 495                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 496                         CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 497                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 498                 .icache_bsize           = 32,
 499                 .dcache_bsize           = 32,
 500                 .num_pmcs               = 6,
 501                 .cpu_setup              = __setup_cpu_745x
 502         },
 503         {       /* 7447/7457 Rev 1.1 */
 504                 .pvr_mask               = 0xffffffff,
 505                 .pvr_value              = 0x80020101,
 506                 .cpu_name               = "7447/7457",
 507                 .cpu_features           = CPU_FTR_COMMON |
 508                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 509                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 510                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 511                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 512                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 513                         CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 514                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 515                 .icache_bsize           = 32,
 516                 .dcache_bsize           = 32,
 517                 .num_pmcs               = 6,
 518                 .cpu_setup              = __setup_cpu_745x
 519         },
 520         {       /* 7447/7457 Rev 1.2 and later */
 521                 .pvr_mask               = 0xffff0000,
 522                 .pvr_value              = 0x80020000,
 523                 .cpu_name               = "7447/7457",
 524                 .cpu_features           = CPU_FTR_COMMON |
 525                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 526                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 527                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 528                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 529                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 530                         CPU_FTR_NEED_COHERENT,
 531                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 532                 .icache_bsize           = 32,
 533                 .dcache_bsize           = 32,
 534                 .num_pmcs               = 6,
 535                 .cpu_setup              = __setup_cpu_745x
 536         },
 537         {       /* 7447A */
 538                 .pvr_mask               = 0xffff0000,
 539                 .pvr_value              = 0x80030000,
 540                 .cpu_name               = "7447A",
 541                 .cpu_features           = CPU_FTR_COMMON |
 542                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 543                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
 544                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 545                         CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 546                         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
 547                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 548                 .icache_bsize           = 32,
 549                 .dcache_bsize           = 32,
 550                 .num_pmcs               = 6,
 551                 .cpu_setup              = __setup_cpu_745x
 552         },
 553         {       /* 82xx (8240, 8245, 8260 are all 603e cores) */
 554                 .pvr_mask               = 0x7fff0000,
 555                 .pvr_value              = 0x00810000,
 556                 .cpu_name               = "82xx",
 557                 .cpu_features           = CPU_FTR_COMMON |
 558                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 559                         CPU_FTR_USE_TB,
 560                 .cpu_user_features      = COMMON_PPC,
 561                 .icache_bsize           = 32,
 562                 .dcache_bsize           = 32,
 563                 .cpu_setup              = __setup_cpu_603
 564         },
 565         {       /* All G2_LE (603e core, plus some) have the same pvr */
 566                 .pvr_mask               = 0x7fff0000,
 567                 .pvr_value              = 0x00820000,
 568                 .cpu_name               = "G2_LE",
 569                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 570                         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 571                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 572                 .cpu_user_features      = COMMON_PPC,
 573                 .icache_bsize           = 32,
 574                 .dcache_bsize           = 32,
 575                 .cpu_setup              = __setup_cpu_603
 576         },
 577         {       /* e300 (a 603e core, plus some) on 83xx */
 578                 .pvr_mask               = 0x7fff0000,
 579                 .pvr_value              = 0x00830000,
 580                 .cpu_name               = "e300",
 581                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 582                         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 583                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 584                 .cpu_user_features      = COMMON_PPC,
 585                 .icache_bsize           = 32,
 586                 .dcache_bsize           = 32,
 587                 .cpu_setup              = __setup_cpu_603
 588         },
 589         {       /* default match, we assume split I/D cache & TB (non-601)... */
 590                 .pvr_mask               = 0x00000000,
 591                 .pvr_value              = 0x00000000,
 592                 .cpu_name               = "(generic PPC)",
 593                 .cpu_features           = CPU_FTR_COMMON |
 594                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 595                         CPU_FTR_HPTE_TABLE,
 596                 .cpu_user_features      = COMMON_PPC,
 597                 .icache_bsize           = 32,
 598                 .dcache_bsize           = 32,
 599                 .cpu_setup              = __setup_cpu_generic
 600         },
 601 #endif /* CLASSIC_PPC */
 602 #ifdef CONFIG_PPC64BRIDGE
 603         {       /* Power3 */
 604                 .pvr_mask               = 0xffff0000,
 605                 .pvr_value              = 0x00400000,
 606                 .cpu_name               = "Power3 (630)",
 607                 .cpu_features           = CPU_FTR_COMMON |
 608                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 609                         CPU_FTR_HPTE_TABLE,
 610                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
 611                 .icache_bsize           = 128,
 612                 .dcache_bsize           = 128,
 613                 .num_pmcs               = 8,
 614                 .cpu_setup              = __setup_cpu_power3
 615         },
 616         {       /* Power3+ */
 617                 .pvr_mask               = 0xffff0000,
 618                 .pvr_value              = 0x00410000,
 619                 .cpu_name               = "Power3 (630+)",
 620                 .cpu_features           = CPU_FTR_COMMON |
 621                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 622                         CPU_FTR_HPTE_TABLE,
 623                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
 624                 .icache_bsize           = 128,
 625                 .dcache_bsize           = 128,
 626                 .num_pmcs               = 8,
 627                 .cpu_setup              = __setup_cpu_power3
 628         },
 629         {       /* I-star */
 630                 .pvr_mask               = 0xffff0000,
 631                 .pvr_value              = 0x00360000,
 632                 .cpu_name               = "I-star",
 633                 .cpu_features           = CPU_FTR_COMMON |
 634                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 635                         CPU_FTR_HPTE_TABLE,
 636                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
 637                 .icache_bsize           = 128,
 638                 .dcache_bsize           = 128,
 639                 .num_pmcs               = 8,
 640                 .cpu_setup              = __setup_cpu_power3
 641         },
 642         {       /* S-star */
 643                 .pvr_mask               = 0xffff0000,
 644                 .pvr_value              = 0x00370000,
 645                 .cpu_name               = "S-star",
 646                 .cpu_features           = CPU_FTR_COMMON |
 647                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 648                         CPU_FTR_HPTE_TABLE,
 649                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
 650                 .icache_bsize           = 128,
 651                 .dcache_bsize           = 128,
 652                 .num_pmcs               = 8,
 653                 .cpu_setup              = __setup_cpu_power3
 654         },
 655 #endif /* CONFIG_PPC64BRIDGE */
 656 #ifdef CONFIG_POWER4
 657         {       /* Power4 */
 658                 .pvr_mask               = 0xffff0000,
 659                 .pvr_value              = 0x00350000,
 660                 .cpu_name               = "Power4",
 661                 .cpu_features           = CPU_FTR_COMMON |
 662                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 663                         CPU_FTR_HPTE_TABLE,
 664                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
 665                 .icache_bsize           = 128,
 666                 .dcache_bsize           = 128,
 667                 .num_pmcs               = 8,
 668                 .cpu_setup              = __setup_cpu_power4
 669         },
 670         {       /* PPC970 */
 671                 .pvr_mask               = 0xffff0000,
 672                 .pvr_value              = 0x00390000,
 673                 .cpu_name               = "PPC970",
 674                 .cpu_features           = CPU_FTR_COMMON |
 675                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 676                         CPU_FTR_HPTE_TABLE |
 677                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
 678                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64 |
 679                         PPC_FEATURE_ALTIVEC_COMP,
 680                 .icache_bsize           = 128,
 681                 .dcache_bsize           = 128,
 682                 .num_pmcs               = 8,
 683                 .cpu_setup              = __setup_cpu_ppc970
 684         },
 685         {       /* PPC970FX */
 686                 .pvr_mask               = 0xffff0000,
 687                 .pvr_value              = 0x003c0000,
 688                 .cpu_name               = "PPC970FX",
 689                 .cpu_features           = CPU_FTR_COMMON |
 690                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 691                         CPU_FTR_HPTE_TABLE |
 692                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
 693                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64 |
 694                         PPC_FEATURE_ALTIVEC_COMP,
 695                 .icache_bsize           = 128,
 696                 .dcache_bsize           = 128,
 697                 .num_pmcs               = 8,
 698                 .cpu_setup              = __setup_cpu_ppc970
 699         },
 700 #endif /* CONFIG_POWER4 */
 701 #ifdef CONFIG_8xx
 702         {       /* 8xx */
 703                 .pvr_mask               = 0xffff0000,
 704                 .pvr_value              = 0x00500000,
 705                 .cpu_name               = "8xx",
 706                 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
 707                  * if the 8xx code is there.... */
 708                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 709                         CPU_FTR_USE_TB,
 710                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 711                 .icache_bsize           = 16,
 712                 .dcache_bsize           = 16,
 713         },
 714 #endif /* CONFIG_8xx */
 715 #ifdef CONFIG_40x
 716         {       /* 403GC */
 717                 .pvr_mask               = 0xffffff00,
 718                 .pvr_value              = 0x00200200,
 719                 .cpu_name               = "403GC",
 720                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 721                         CPU_FTR_USE_TB,
 722                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 723                 .icache_bsize           = 16,
 724                 .dcache_bsize           = 16,
 725         },
 726         {       /* 403GCX */
 727                 .pvr_mask               = 0xffffff00,
 728                 .pvr_value              = 0x00201400,
 729                 .cpu_name               = "403GCX",
 730                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 731                         CPU_FTR_USE_TB,
 732                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 733                 .icache_bsize           = 16,
 734                 .dcache_bsize           = 16,
 735         },
 736         {       /* 403G ?? */
 737                 .pvr_mask               = 0xffff0000,
 738                 .pvr_value              = 0x00200000,
 739                 .cpu_name               = "403G ??",
 740                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 741                         CPU_FTR_USE_TB,
 742                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 743                 .icache_bsize           = 16,
 744                 .dcache_bsize           = 16,
 745         },
 746         {       /* 405GP */
 747                 .pvr_mask               = 0xffff0000,
 748                 .pvr_value              = 0x40110000,
 749                 .cpu_name               = "405GP",
 750                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 751                         CPU_FTR_USE_TB,
 752                 .cpu_user_features      = PPC_FEATURE_32 |
 753                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 754                 .icache_bsize           = 32,
 755                 .dcache_bsize           = 32,
 756         },
 757         {       /* STB 03xxx */
 758                 .pvr_mask               = 0xffff0000,
 759                 .pvr_value              = 0x40130000,
 760                 .cpu_name               = "STB03xxx",
 761                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 762                         CPU_FTR_USE_TB,
 763                 .cpu_user_features      = PPC_FEATURE_32 |
 764                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 765                 .icache_bsize           = 32,
 766                 .dcache_bsize           = 32,
 767         },
 768         {       /* STB 04xxx */
 769                 .pvr_mask               = 0xffff0000,
 770                 .pvr_value              = 0x41810000,
 771                 .cpu_name               = "STB04xxx",
 772                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 773                         CPU_FTR_USE_TB,
 774                 .cpu_user_features      = PPC_FEATURE_32 |
 775                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 776                 .icache_bsize           = 32,
 777                 .dcache_bsize           = 32,
 778         },
 779         {       /* NP405L */
 780                 .pvr_mask               = 0xffff0000,
 781                 .pvr_value              = 0x41610000,
 782                 .cpu_name               = "NP405L",
 783                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 784                         CPU_FTR_USE_TB,
 785                 .cpu_user_features      = PPC_FEATURE_32 |
 786                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 787                 .icache_bsize           = 32,
 788                 .dcache_bsize           = 32,
 789         },
 790         {       /* NP4GS3 */
 791                 .pvr_mask               = 0xffff0000,
 792                 .pvr_value              = 0x40B10000,
 793                 .cpu_name               = "NP4GS3",
 794                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 795                         CPU_FTR_USE_TB,
 796                 .cpu_user_features      = PPC_FEATURE_32 |
 797                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 798                 .icache_bsize           = 32,
 799                 .dcache_bsize           = 32,
 800         },
 801         {   /* NP405H */
 802                 .pvr_mask               = 0xffff0000,
 803                 .pvr_value              = 0x41410000,
 804                 .cpu_name               = "NP405H",
 805                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 806                         CPU_FTR_USE_TB,
 807                 .cpu_user_features      = PPC_FEATURE_32 |
 808                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 809                 .icache_bsize           = 32,
 810                 .dcache_bsize           = 32,
 811         },
 812         {       /* 405GPr */
 813                 .pvr_mask               = 0xffff0000,
 814                 .pvr_value              = 0x50910000,
 815                 .cpu_name               = "405GPr",
 816                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 817                         CPU_FTR_USE_TB,
 818                 .cpu_user_features      = PPC_FEATURE_32 |
 819                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 820                 .icache_bsize           = 32,
 821                 .dcache_bsize           = 32,
 822         },
 823         {   /* STBx25xx */
 824                 .pvr_mask               = 0xffff0000,
 825                 .pvr_value              = 0x51510000,
 826                 .cpu_name               = "STBx25xx",
 827                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 828                         CPU_FTR_USE_TB,
 829                 .cpu_user_features      = PPC_FEATURE_32 |
 830                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 831                 .icache_bsize           = 32,
 832                 .dcache_bsize           = 32,
 833         },
 834         {       /* 405LP */
 835                 .pvr_mask               = 0xffff0000,
 836                 .pvr_value              = 0x41F10000,
 837                 .cpu_name               = "405LP",
 838                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 839                         CPU_FTR_USE_TB,
 840                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 841                 .icache_bsize           = 32,
 842                 .dcache_bsize           = 32,
 843         },
 844         {       /* Xilinx Virtex-II Pro  */
 845                 .pvr_mask               = 0xffff0000,
 846                 .pvr_value              = 0x20010000,
 847                 .cpu_name               = "Virtex-II Pro",
 848                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 849                         CPU_FTR_USE_TB,
 850                 .cpu_user_features      = PPC_FEATURE_32 |
 851                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 852                 .icache_bsize           = 32,
 853                 .dcache_bsize           = 32,
 854         },
 855         {       /* 405EP */
 856                 .pvr_mask               = 0xffff0000,
 857                 .pvr_value              = 0x51210000,
 858                 .cpu_name               = "405EP",
 859                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 860                         CPU_FTR_USE_TB,
 861                 .cpu_user_features      = PPC_FEATURE_32 |
 862                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 863                 .icache_bsize           = 32,
 864                 .dcache_bsize           = 32,
 865         },
 866
 867 #endif /* CONFIG_40x */
 868 #ifdef CONFIG_44x
 869         {
 870                 .pvr_mask               = 0xf0000fff,
 871                 .pvr_value              = 0x40000850,
 872                 .cpu_name               = "440EP Rev. A",
 873                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 874                         CPU_FTR_USE_TB,
 875                 .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
 876                 .icache_bsize           = 32,
 877                 .dcache_bsize           = 32,
 878         },
 879         {
 880                 .pvr_mask               = 0xf0000fff,
 881                 .pvr_value              = 0x400008d3,
 882                 .cpu_name               = "440EP Rev. B",
 883                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 884                         CPU_FTR_USE_TB,
 885                 .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
 886                 .icache_bsize           = 32,
 887                 .dcache_bsize           = 32,
 888         },
 889         {       /* 440GP Rev. B */
 890                 .pvr_mask               = 0xf0000fff,
 891                 .pvr_value              = 0x40000440,
 892                 .cpu_name               = "440GP Rev. B",
 893                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 894                         CPU_FTR_USE_TB,
 895                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 896                 .icache_bsize           = 32,
 897                 .dcache_bsize           = 32,
 898         },
 899         {       /* 440GP Rev. C */
 900                 .pvr_mask               = 0xf0000fff,
 901                 .pvr_value              = 0x40000481,
 902                 .cpu_name               = "440GP Rev. C",
 903                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 904                         CPU_FTR_USE_TB,
 905                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 906                 .icache_bsize           = 32,
 907                 .dcache_bsize           = 32,
 908         },
 909         { /* 440GX Rev. A */
 910                 .pvr_mask               = 0xf0000fff,
 911                 .pvr_value              = 0x50000850,
 912                 .cpu_name               = "440GX Rev. A",
 913                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 914                         CPU_FTR_USE_TB,
 915                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 916                 .icache_bsize           = 32,
 917                 .dcache_bsize           = 32,
 918         },
 919         { /* 440GX Rev. B */
 920                 .pvr_mask               = 0xf0000fff,
 921                 .pvr_value              = 0x50000851,
 922                 .cpu_name               = "440GX Rev. B",
 923                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 924                         CPU_FTR_USE_TB,
 925                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 926                 .icache_bsize           = 32,
 927                 .dcache_bsize           = 32,
 928         },
 929         { /* 440GX Rev. C */
 930                 .pvr_mask               = 0xf0000fff,
 931                 .pvr_value              = 0x50000892,
 932                 .cpu_name               = "440GX Rev. C",
 933                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 934                         CPU_FTR_USE_TB,
 935                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 936                 .icache_bsize           = 32,
 937                 .dcache_bsize           = 32,
 938         },
 939         { /* 440GX Rev. F */
 940                 .pvr_mask               = 0xf0000fff,
 941                 .pvr_value              = 0x50000894,
 942                 .cpu_name               = "440GX Rev. F",
 943                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 944                         CPU_FTR_USE_TB,
 945                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 946                 .icache_bsize           = 32,
 947                 .dcache_bsize           = 32,
 948         },
 949         { /* 440SP Rev. A */
 950                 .pvr_mask               = 0xff000fff,
 951                 .pvr_value              = 0x53000891,
 952                 .cpu_name               = "440SP Rev. A",
 953                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 954                         CPU_FTR_USE_TB,
 955                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 956                 .icache_bsize           = 32,
 957                 .dcache_bsize           = 32,
 958         },
 959 #endif /* CONFIG_44x */
 960 #ifdef CONFIG_FSL_BOOKE
 961         {       /* e200z5 */
 962                 .pvr_mask               = 0xfff00000,
 963                 .pvr_value              = 0x81000000,
 964                 .cpu_name               = "e200z5",
 965                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
 966                 .cpu_features           = CPU_FTR_USE_TB,
 967                 .cpu_user_features      = PPC_FEATURE_32 |
 968                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
 969                         PPC_FEATURE_UNIFIED_CACHE,
 970                 .dcache_bsize           = 32,
 971         },
 972         {       /* e200z6 */
 973                 .pvr_mask               = 0xfff00000,
 974                 .pvr_value              = 0x81100000,
 975                 .cpu_name               = "e200z6",
 976                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
 977                 .cpu_features           = CPU_FTR_USE_TB,
 978                 .cpu_user_features      = PPC_FEATURE_32 |
 979                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
 980                         PPC_FEATURE_HAS_EFP_SINGLE |
 981                         PPC_FEATURE_UNIFIED_CACHE,
 982                 .dcache_bsize           = 32,
 983         },
 984         {       /* e500 */
 985                 .pvr_mask               = 0xffff0000,
 986                 .pvr_value              = 0x80200000,
 987                 .cpu_name               = "e500",
 988                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
 989                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 990                         CPU_FTR_USE_TB,
 991                 .cpu_user_features      = PPC_FEATURE_32 |
 992                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
 993                         PPC_FEATURE_HAS_EFP_SINGLE,
 994                 .icache_bsize           = 32,
 995                 .dcache_bsize           = 32,
 996                 .num_pmcs               = 4,
 997         },
 998         {       /* e500v2 */
 999                 .pvr_mask               = 0xffff0000,
1000                 .pvr_value              = 0x80210000,
1001                 .cpu_name               = "e500v2",
1002                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1003                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
1004                         CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
1005                 .cpu_user_features      = PPC_FEATURE_32 |
1006                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
1007                         PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
1008                 .icache_bsize           = 32,
1009                 .dcache_bsize           = 32,
1010                 .num_pmcs               = 4,
1011         },
1012 #endif
1013 #if !CLASSIC_PPC
1014         {       /* default match */
1015                 .pvr_mask               = 0x00000000,
1016                 .pvr_value              = 0x00000000,
1017                 .cpu_name               = "(generic PPC)",
1018                 .cpu_features           = CPU_FTR_COMMON,
1019                 .cpu_user_features      = PPC_FEATURE_32,
1020                 .icache_bsize           = 32,
1021                 .dcache_bsize           = 32,
1022         }
1023 #endif /* !CLASSIC_PPC */
1024 };