2 * arch/powerpc/sysdev/uic.c
4 * IBM PowerPC 4xx Universal Interrupt Controller
6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel_stat.h>
33 #define NR_UIC_INTS 32
44 #define uic_irq_to_hw(virq) (irq_map[virq].hwirq)
46 struct uic *primary_uic;
54 /* The remapper for this UIC */
55 struct irq_host *irqhost;
57 /* For secondary UICs, the cascade interrupt's irqaction */
58 struct irqaction cascade;
61 static void uic_unmask_irq(unsigned int virq)
63 struct irq_desc *desc = get_irq_desc(virq);
64 struct uic *uic = get_irq_chip_data(virq);
65 unsigned int src = uic_irq_to_hw(virq);
70 spin_lock_irqsave(&uic->lock, flags);
71 /* ack level-triggered interrupts here */
72 if (desc->status & IRQ_LEVEL)
73 mtdcr(uic->dcrbase + UIC_SR, sr);
74 er = mfdcr(uic->dcrbase + UIC_ER);
76 mtdcr(uic->dcrbase + UIC_ER, er);
77 spin_unlock_irqrestore(&uic->lock, flags);
80 static void uic_mask_irq(unsigned int virq)
82 struct uic *uic = get_irq_chip_data(virq);
83 unsigned int src = uic_irq_to_hw(virq);
87 spin_lock_irqsave(&uic->lock, flags);
88 er = mfdcr(uic->dcrbase + UIC_ER);
89 er &= ~(1 << (31 - src));
90 mtdcr(uic->dcrbase + UIC_ER, er);
91 spin_unlock_irqrestore(&uic->lock, flags);
94 static void uic_ack_irq(unsigned int virq)
96 struct uic *uic = get_irq_chip_data(virq);
97 unsigned int src = uic_irq_to_hw(virq);
100 spin_lock_irqsave(&uic->lock, flags);
101 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
102 spin_unlock_irqrestore(&uic->lock, flags);
105 static void uic_mask_ack_irq(unsigned int virq)
107 struct irq_desc *desc = get_irq_desc(virq);
108 struct uic *uic = get_irq_chip_data(virq);
109 unsigned int src = uic_irq_to_hw(virq);
114 spin_lock_irqsave(&uic->lock, flags);
115 er = mfdcr(uic->dcrbase + UIC_ER);
117 mtdcr(uic->dcrbase + UIC_ER, er);
118 /* On the UIC, acking (i.e. clearing the SR bit)
119 * a level irq will have no effect if the interrupt
120 * is still asserted by the device, even if
121 * the interrupt is already masked. Therefore
122 * we only ack the egde interrupts here, while
123 * level interrupts are ack'ed after the actual
124 * isr call in the uic_unmask_irq()
126 if (!(desc->status & IRQ_LEVEL))
127 mtdcr(uic->dcrbase + UIC_SR, sr);
128 spin_unlock_irqrestore(&uic->lock, flags);
131 static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
133 struct uic *uic = get_irq_chip_data(virq);
134 unsigned int src = uic_irq_to_hw(virq);
135 struct irq_desc *desc = get_irq_desc(virq);
137 int trigger, polarity;
140 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
145 case IRQ_TYPE_EDGE_RISING:
146 trigger = 1; polarity = 1;
148 case IRQ_TYPE_EDGE_FALLING:
149 trigger = 1; polarity = 0;
151 case IRQ_TYPE_LEVEL_HIGH:
152 trigger = 0; polarity = 1;
154 case IRQ_TYPE_LEVEL_LOW:
155 trigger = 0; polarity = 0;
161 mask = ~(1 << (31 - src));
163 spin_lock_irqsave(&uic->lock, flags);
164 tr = mfdcr(uic->dcrbase + UIC_TR);
165 pr = mfdcr(uic->dcrbase + UIC_PR);
166 tr = (tr & mask) | (trigger << (31-src));
167 pr = (pr & mask) | (polarity << (31-src));
169 mtdcr(uic->dcrbase + UIC_PR, pr);
170 mtdcr(uic->dcrbase + UIC_TR, tr);
172 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
173 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
175 desc->status |= IRQ_LEVEL;
177 spin_unlock_irqrestore(&uic->lock, flags);
182 static struct irq_chip uic_irq_chip = {
184 .unmask = uic_unmask_irq,
185 .mask = uic_mask_irq,
186 .mask_ack = uic_mask_ack_irq,
188 .set_type = uic_set_irq_type,
191 static int uic_host_map(struct irq_host *h, unsigned int virq,
194 struct uic *uic = h->host_data;
196 set_irq_chip_data(virq, uic);
197 /* Despite the name, handle_level_irq() works for both level
198 * and edge irqs on UIC. FIXME: check this is correct */
199 set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
201 /* Set default irq type */
202 set_irq_type(virq, IRQ_TYPE_NONE);
207 static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
208 u32 *intspec, unsigned int intsize,
209 irq_hw_number_t *out_hwirq, unsigned int *out_type)
212 /* UIC intspecs must have 2 cells */
213 BUG_ON(intsize != 2);
214 *out_hwirq = intspec[0];
215 *out_type = intspec[1];
219 static struct irq_host_ops uic_host_ops = {
221 .xlate = uic_host_xlate,
224 irqreturn_t uic_cascade(int virq, void *data)
226 struct uic *uic = data;
231 msr = mfdcr(uic->dcrbase + UIC_MSR);
232 if (!msr) /* spurious interrupt */
237 subvirq = irq_linear_revmap(uic->irqhost, src);
238 generic_handle_irq(subvirq);
243 static struct uic * __init uic_init_one(struct device_node *node)
246 const u32 *indexp, *dcrreg;
249 BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
251 uic = alloc_bootmem(sizeof(*uic));
253 return NULL; /* FIXME: panic? */
255 memset(uic, 0, sizeof(*uic));
256 spin_lock_init(&uic->lock);
257 indexp = of_get_property(node, "cell-index", &len);
258 if (!indexp || (len != sizeof(u32))) {
259 printk(KERN_ERR "uic: Device node %s has missing or invalid "
260 "cell-index property\n", node->full_name);
263 uic->index = *indexp;
265 dcrreg = of_get_property(node, "dcr-reg", &len);
266 if (!dcrreg || (len != 2*sizeof(u32))) {
267 printk(KERN_ERR "uic: Device node %s has missing or invalid "
268 "dcr-reg property\n", node->full_name);
271 uic->dcrbase = *dcrreg;
273 uic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
274 NR_UIC_INTS, &uic_host_ops, -1);
275 if (! uic->irqhost) {
277 return NULL; /* FIXME: panic? */
280 uic->irqhost->host_data = uic;
282 /* Start with all interrupts disabled, level and non-critical */
283 mtdcr(uic->dcrbase + UIC_ER, 0);
284 mtdcr(uic->dcrbase + UIC_CR, 0);
285 mtdcr(uic->dcrbase + UIC_TR, 0);
286 /* Clear any pending interrupts, in case the firmware left some */
287 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
289 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
290 NR_UIC_INTS, uic->dcrbase);
295 void __init uic_init_tree(void)
297 struct device_node *np;
299 const u32 *interrupts;
301 /* First locate and initialize the top-level UIC */
303 np = of_find_compatible_node(NULL, NULL, "ibm,uic");
305 interrupts = of_get_property(np, "interrupts", NULL);
309 np = of_find_compatible_node(np, NULL, "ibm,uic");
312 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
313 * top-level interrupt controller */
314 primary_uic = uic_init_one(np);
316 panic("Unable to initialize primary UIC %s\n", np->full_name);
318 irq_set_default_host(primary_uic->irqhost);
321 /* The scan again for cascaded UICs */
322 np = of_find_compatible_node(NULL, NULL, "ibm,uic");
324 interrupts = of_get_property(np, "interrupts", NULL);
330 uic = uic_init_one(np);
332 panic("Unable to initialize a secondary UIC %s\n",
335 cascade_virq = irq_of_parse_and_map(np, 0);
337 uic->cascade.handler = uic_cascade;
338 uic->cascade.name = "UIC cascade";
339 uic->cascade.dev_id = uic;
341 ret = setup_irq(cascade_virq, &uic->cascade);
343 printk(KERN_ERR "Failed to setup_irq(%d) for "
344 "UIC%d cascade\n", cascade_virq,
347 /* FIXME: setup critical cascade?? */
350 np = of_find_compatible_node(np, NULL, "ibm,uic");
354 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
355 unsigned int uic_get_irq(void)
360 BUG_ON(! primary_uic);
362 msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
365 return irq_linear_revmap(primary_uic->irqhost, src);