2 * Common routines for Tundra Semiconductor TSI108 host bridge.
4 * 2004-2005 (c) Tundra Semiconductor Corp.
5 * Author: Alex Bounine (alexandreb@tundra.com)
6 * Author: Roy Zang (tie-fei.zang@freescale.com)
7 * Add pci interrupt router host
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
31 #include <asm/byteorder.h>
34 #include <asm/uaccess.h>
35 #include <asm/machdep.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/tsi108.h>
38 #include <asm/tsi108_pci.h>
39 #include <asm/tsi108_irq.h>
44 #define DBG(x...) printk(x)
49 #define tsi_mk_config_addr(bus, devfunc, offset) \
50 ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
52 u32 tsi108_pci_cfg_base;
53 static u32 tsi108_pci_cfg_phys;
54 u32 tsi108_csr_vir_base;
55 static struct device_node *pci_irq_node;
56 static struct irq_host *pci_irq_host;
58 extern u32 get_vir_csrbase(void);
59 extern u32 tsi108_read_reg(u32 reg_offset);
60 extern void tsi108_write_reg(u32 reg_offset, u32 val);
63 tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
64 int offset, int len, u32 val)
66 volatile unsigned char *cfg_addr;
67 struct pci_controller *hose = bus->sysdata;
69 if (ppc_md.pci_exclude_device)
70 if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
71 return PCIBIOS_DEVICE_NOT_FOUND;
73 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
78 printk("PCI CFG write : ");
79 printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
80 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
81 printk("data = 0x%08x\n", val);
86 out_8((u8 *) cfg_addr, val);
89 out_le16((u16 *) cfg_addr, val);
92 out_le32((u32 *) cfg_addr, val);
96 return PCIBIOS_SUCCESSFUL;
99 void tsi108_clear_pci_error(u32 pci_cfg_base)
101 u32 err_stat, err_addr, pci_stat;
104 * Quietly clear PB and PCI error flags set as result
105 * of PCI/X configuration read requests.
108 /* Read PB Error Log Registers */
110 err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
111 err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
113 if (err_stat & TSI108_PB_ERRCS_ES) {
114 /* Clear error flag */
115 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
118 /* Clear read error reported in PB_ISR */
119 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
120 TSI108_PB_ISR_PBS_RD_ERR);
122 /* Clear PCI/X bus cfg errors if applicable */
123 if ((err_addr & 0xFF000000) == pci_cfg_base) {
125 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
126 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
134 #define __tsi108_read_pci_config(x, addr, op) \
135 __asm__ __volatile__( \
139 ".section .fixup,\"ax\"\n" \
142 ".section __ex_table,\"a\"\n" \
146 : "=r"(x) : "r"(addr))
149 tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
152 volatile unsigned char *cfg_addr;
153 struct pci_controller *hose = bus->sysdata;
156 if (ppc_md.pci_exclude_device)
157 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
158 return PCIBIOS_DEVICE_NOT_FOUND;
160 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
167 __tsi108_read_pci_config(temp, cfg_addr, "lbzx");
170 __tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
173 __tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
180 if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
181 printk("PCI CFG read : ");
182 printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
183 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
184 printk("data = 0x%x\n", *val);
187 return PCIBIOS_SUCCESSFUL;
190 void tsi108_clear_pci_cfg_error(void)
192 tsi108_clear_pci_error(tsi108_pci_cfg_phys);
195 static struct pci_ops tsi108_direct_pci_ops = {
196 tsi108_direct_read_config,
197 tsi108_direct_write_config
200 int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
203 struct pci_controller *hose;
204 struct resource rsrc;
205 const int *bus_range;
208 /* PCI Config mapping */
209 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
210 tsi108_pci_cfg_phys = cfg_phys;
211 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
212 tsi108_pci_cfg_base);
214 /* Fetch host bridge registers address */
215 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
217 /* Get bus range if any */
218 bus_range = of_get_property(dev, "bus-range", &len);
219 if (bus_range == NULL || len < 2 * sizeof(int)) {
220 printk(KERN_WARNING "Can't get bus-range for %s, assume"
221 " bus 0\n", dev->full_name);
224 hose = pcibios_alloc_controller();
227 printk("PCI Host bridge init failed\n");
230 hose->arch_data = dev;
232 hose->first_busno = bus_range ? bus_range[0] : 0;
233 hose->last_busno = bus_range ? bus_range[1] : 0xff;
235 (hose)->ops = &tsi108_direct_pci_ops;
237 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
238 "Firmware bus number: %d->%d\n",
239 rsrc.start, hose->first_busno, hose->last_busno);
241 /* Interpret the "ranges" property */
242 /* This also maps the I/O region and sets isa_io/mem_base */
243 pci_process_bridge_OF_ranges(hose, dev, primary);
248 * Low level utility functions
251 static void tsi108_pci_int_mask(u_int irq)
254 int int_line = (irq - IRQ_PCI_INTAD_BASE);
256 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
258 irp_cfg |= (1 << int_line); /* INTx_DIR = output */
259 irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
260 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
262 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
265 static void tsi108_pci_int_unmask(u_int irq)
268 int int_line = (irq - IRQ_PCI_INTAD_BASE);
270 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
272 irp_cfg &= ~(1 << int_line);
273 irp_cfg |= (3 << (8 + (int_line * 2)));
274 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
278 static void init_pci_source(void)
280 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
282 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
283 TSI108_PCI_IRP_ENABLE_P_INT);
287 static inline unsigned int get_pci_source(void)
295 /* Read PCI/X block interrupt status register */
296 pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
299 if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
300 /* Process Interrupt from PCI bus INTA# - INTD# lines */
302 tsi108_read_reg(TSI108_PCI_OFFSET +
303 TSI108_PCI_IRP_INTAD) & 0xf;
305 for (i = 0; i < 4; i++, mask++) {
306 if (temp & (1 << mask % 4)) {
307 irq = IRQ_PCI_INTA + mask % 4;
313 /* Disable interrupts from PCI block */
314 temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
315 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
316 temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
318 (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
323 printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
325 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
327 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
329 printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
331 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
333 printk("cfg_ctl=0x%08x ", temp);
335 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
337 printk("irp_enable=0x%08x\n", temp);
339 #endif /* end of DEBUG */
346 * Linux descriptor level callbacks
349 static void tsi108_pci_irq_enable(u_int irq)
351 tsi108_pci_int_unmask(irq);
354 static void tsi108_pci_irq_disable(u_int irq)
356 tsi108_pci_int_mask(irq);
359 static void tsi108_pci_irq_ack(u_int irq)
361 tsi108_pci_int_mask(irq);
364 static void tsi108_pci_irq_end(u_int irq)
366 tsi108_pci_int_unmask(irq);
368 /* Enable interrupts from PCI block */
369 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
370 tsi108_read_reg(TSI108_PCI_OFFSET +
371 TSI108_PCI_IRP_ENABLE) |
372 TSI108_PCI_IRP_ENABLE_P_INT);
377 * Interrupt controller descriptor for cascaded PCI interrupt controller.
380 static struct irq_chip tsi108_pci_irq = {
381 .typename = "tsi108_PCI_int",
382 .mask = tsi108_pci_irq_disable,
383 .ack = tsi108_pci_irq_ack,
384 .end = tsi108_pci_irq_end,
385 .unmask = tsi108_pci_irq_enable,
388 static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
389 u32 *intspec, unsigned int intsize,
390 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
392 *out_hwirq = intspec[0];
393 *out_flags = IRQ_TYPE_LEVEL_HIGH;
397 static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
400 DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw);
401 if ((virq >= 1) && (virq <= 4)){
402 irq = virq + IRQ_PCI_INTAD_BASE - 1;
403 get_irq_desc(irq)->status |= IRQ_LEVEL;
404 set_irq_chip(irq, &tsi108_pci_irq);
409 static int pci_irq_host_match(struct irq_host *h, struct device_node *node)
411 return pci_irq_node == node;
414 static struct irq_host_ops pci_irq_host_ops = {
415 .match = pci_irq_host_match,
416 .map = pci_irq_host_map,
417 .xlate = pci_irq_host_xlate,
425 * The Tsi108 PCI interrupts initialization routine.
427 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
428 * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
429 * PCI block has to be treated as a cascaded interrupt controller connected
433 void __init tsi108_pci_int_init(struct device_node *node)
435 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
437 pci_irq_node = of_node_get(node);
438 pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0);
439 if (pci_irq_host == NULL) {
440 printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n");
447 void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
449 unsigned int cascade_irq = get_pci_source();
450 if (cascade_irq != NO_IRQ)
451 generic_handle_irq(cascade_irq);
452 desc->chip->eoi(irq);