2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
33 #include <asm/pgtable.h>
35 #include <asm/machdep.h>
40 #define DBG(fmt...) printk(fmt)
45 static struct mpic *mpics;
46 static struct mpic *mpic_primary;
47 static DEFINE_SPINLOCK(mpic_lock);
49 #ifdef CONFIG_PPC32 /* XXX for now */
50 #ifdef CONFIG_IRQ_ALL_CPUS
51 #define distribute_irqs (1)
53 #define distribute_irqs (0)
58 * Register accessor functions
62 static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
66 return in_be32(base + (reg >> 2));
68 return in_le32(base + (reg >> 2));
71 static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
72 unsigned int reg, u32 value)
75 out_be32(base + (reg >> 2), value);
77 out_le32(base + (reg >> 2), value);
80 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
82 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
85 if (mpic->flags & MPIC_BROKEN_IPI)
87 return _mpic_read(be, mpic->gregs, offset);
90 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
92 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
94 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
97 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
101 if (mpic->flags & MPIC_PRIMARY)
102 cpu = hard_smp_processor_id();
103 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,
104 mpic->cpuregs[cpu], reg);
107 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
109 unsigned int cpu = 0;
111 if (mpic->flags & MPIC_PRIMARY)
112 cpu = hard_smp_processor_id();
114 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
117 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
119 unsigned int isu = src_no >> mpic->isu_shift;
120 unsigned int idx = src_no & mpic->isu_mask;
122 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE));
126 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
127 unsigned int reg, u32 value)
129 unsigned int isu = src_no >> mpic->isu_shift;
130 unsigned int idx = src_no & mpic->isu_mask;
132 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
133 reg + (idx * MPIC_IRQ_STRIDE), value);
136 #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
137 #define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
138 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
139 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
140 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
141 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
142 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
143 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
147 * Low level utility functions
152 /* Check if we have one of those nice broken MPICs with a flipped endian on
153 * reads from IPI registers
155 static void __init mpic_test_broken_ipi(struct mpic *mpic)
159 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
160 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
162 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
163 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
164 mpic->flags |= MPIC_BROKEN_IPI;
168 #ifdef CONFIG_MPIC_BROKEN_U3
170 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
171 * to force the edge setting on the MPIC and do the ack workaround.
173 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
175 if (source >= 128 || !mpic->fixups)
177 return mpic->fixups[source].base != NULL;
181 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
183 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
185 if (fixup->applebase) {
186 unsigned int soff = (fixup->index >> 3) & ~3;
187 unsigned int mask = 1U << (fixup->index & 0x1f);
188 writel(mask, fixup->applebase + soff);
190 spin_lock(&mpic->fixup_lock);
191 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
192 writel(fixup->data, fixup->base + 4);
193 spin_unlock(&mpic->fixup_lock);
197 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
198 unsigned int irqflags)
200 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
204 if (fixup->base == NULL)
207 DBG("startup_ht_interrupt(%u, %u) index: %d\n",
208 source, irqflags, fixup->index);
209 spin_lock_irqsave(&mpic->fixup_lock, flags);
210 /* Enable and configure */
211 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
212 tmp = readl(fixup->base + 4);
214 if (irqflags & IRQ_LEVEL)
216 writel(tmp, fixup->base + 4);
217 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
220 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
221 unsigned int irqflags)
223 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
227 if (fixup->base == NULL)
230 DBG("shutdown_ht_interrupt(%u, %u)\n", source, irqflags);
233 spin_lock_irqsave(&mpic->fixup_lock, flags);
234 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
235 tmp = readl(fixup->base + 4);
237 writel(tmp, fixup->base + 4);
238 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
241 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
242 unsigned int devfn, u32 vdid)
249 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
250 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
251 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
252 if (id == PCI_CAP_ID_HT_IRQCONF) {
253 id = readb(devbase + pos + 3);
261 base = devbase + pos;
262 writeb(0x01, base + 2);
263 n = (readl(base + 4) >> 16) & 0xff;
265 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
267 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
269 for (i = 0; i <= n; i++) {
270 writeb(0x10 + 2 * i, base + 2);
271 tmp = readl(base + 4);
272 irq = (tmp >> 16) & 0xff;
273 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
274 /* mask it , will be unmasked later */
276 writel(tmp, base + 4);
277 mpic->fixups[irq].index = i;
278 mpic->fixups[irq].base = base;
279 /* Apple HT PIC has a non-standard way of doing EOIs */
280 if ((vdid & 0xffff) == 0x106b)
281 mpic->fixups[irq].applebase = devbase + 0x60;
283 mpic->fixups[irq].applebase = NULL;
284 writeb(0x11 + 2 * i, base + 2);
285 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
290 static void __init mpic_scan_ht_pics(struct mpic *mpic)
293 u8 __iomem *cfgspace;
295 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
297 /* Allocate fixups array */
298 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
299 BUG_ON(mpic->fixups == NULL);
300 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
303 spin_lock_init(&mpic->fixup_lock);
305 /* Map U3 config space. We assume all IO-APICs are on the primary bus
306 * so we only need to map 64kB.
308 cfgspace = ioremap(0xf2000000, 0x10000);
309 BUG_ON(cfgspace == NULL);
311 /* Now we scan all slots. We do a very quick scan, we read the header
312 * type, vendor ID and device ID only, that's plenty enough
314 for (devfn = 0; devfn < 0x100; devfn++) {
315 u8 __iomem *devbase = cfgspace + (devfn << 8);
316 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
317 u32 l = readl(devbase + PCI_VENDOR_ID);
320 DBG("devfn %x, l: %x\n", devfn, l);
322 /* If no device, skip */
323 if (l == 0xffffffff || l == 0x00000000 ||
324 l == 0x0000ffff || l == 0xffff0000)
326 /* Check if is supports capability lists */
327 s = readw(devbase + PCI_STATUS);
328 if (!(s & PCI_STATUS_CAP_LIST))
331 mpic_scan_ht_pic(mpic, devbase, devfn, l);
334 /* next device, if function 0 */
335 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
340 #endif /* CONFIG_MPIC_BROKEN_U3 */
343 /* Find an mpic associated with a given linux interrupt */
344 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
346 struct mpic *mpic = mpics;
349 /* search IPIs first since they may override the main interrupts */
350 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
355 if (irq >= mpic->irq_offset &&
356 irq < (mpic->irq_offset + mpic->irq_count)) {
366 /* Convert a cpu mask from logical to physical cpu numbers. */
367 static inline u32 mpic_physmask(u32 cpumask)
372 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
373 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
378 /* Get the mpic structure from the IPI number */
379 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
381 return irq_desc[ipi].chip_data;
385 /* Get the mpic structure from the irq number */
386 static inline struct mpic * mpic_from_irq(unsigned int irq)
388 return irq_desc[irq].chip_data;
392 static inline void mpic_eoi(struct mpic *mpic)
394 mpic_cpu_write(MPIC_CPU_EOI, 0);
395 (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
399 static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
401 struct mpic *mpic = dev_id;
403 smp_message_recv(irq - mpic->ipi_offset, regs);
406 #endif /* CONFIG_SMP */
409 * Linux descriptor level callbacks
413 static void mpic_unmask_irq(unsigned int irq)
415 unsigned int loops = 100000;
416 struct mpic *mpic = mpic_from_irq(irq);
417 unsigned int src = irq - mpic->irq_offset;
419 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
421 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
422 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
425 /* make sure mask gets to controller before we return to user */
428 printk(KERN_ERR "mpic_enable_irq timeout\n");
431 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
434 static void mpic_mask_irq(unsigned int irq)
436 unsigned int loops = 100000;
437 struct mpic *mpic = mpic_from_irq(irq);
438 unsigned int src = irq - mpic->irq_offset;
440 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
442 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
443 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
446 /* make sure mask gets to controller before we return to user */
449 printk(KERN_ERR "mpic_enable_irq timeout\n");
452 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
455 static void mpic_end_irq(unsigned int irq)
457 struct mpic *mpic = mpic_from_irq(irq);
460 DBG("%s: end_irq: %d\n", mpic->name, irq);
462 /* We always EOI on end_irq() even for edge interrupts since that
463 * should only lower the priority, the MPIC should have properly
464 * latched another edge interrupt coming in anyway
470 #ifdef CONFIG_MPIC_BROKEN_U3
472 static void mpic_unmask_ht_irq(unsigned int irq)
474 struct mpic *mpic = mpic_from_irq(irq);
475 unsigned int src = irq - mpic->irq_offset;
477 mpic_unmask_irq(irq);
479 if (irq_desc[irq].status & IRQ_LEVEL)
480 mpic_ht_end_irq(mpic, src);
483 static unsigned int mpic_startup_ht_irq(unsigned int irq)
485 struct mpic *mpic = mpic_from_irq(irq);
486 unsigned int src = irq - mpic->irq_offset;
488 mpic_unmask_irq(irq);
489 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
494 static void mpic_shutdown_ht_irq(unsigned int irq)
496 struct mpic *mpic = mpic_from_irq(irq);
497 unsigned int src = irq - mpic->irq_offset;
499 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
503 static void mpic_end_ht_irq(unsigned int irq)
505 struct mpic *mpic = mpic_from_irq(irq);
506 unsigned int src = irq - mpic->irq_offset;
509 DBG("%s: end_irq: %d\n", mpic->name, irq);
511 /* We always EOI on end_irq() even for edge interrupts since that
512 * should only lower the priority, the MPIC should have properly
513 * latched another edge interrupt coming in anyway
516 if (irq_desc[irq].status & IRQ_LEVEL)
517 mpic_ht_end_irq(mpic, src);
521 #endif /* CONFIG_MPIC_BROKEN_U3 */
525 static void mpic_unmask_ipi(unsigned int irq)
527 struct mpic *mpic = mpic_from_ipi(irq);
528 unsigned int src = irq - mpic->ipi_offset;
530 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
531 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
534 static void mpic_mask_ipi(unsigned int irq)
536 /* NEVER disable an IPI... that's just plain wrong! */
539 static void mpic_end_ipi(unsigned int irq)
541 struct mpic *mpic = mpic_from_ipi(irq);
544 * IPIs are marked IRQ_PER_CPU. This has the side effect of
545 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
546 * applying to them. We EOI them late to avoid re-entering.
547 * We mark IPI's with IRQF_DISABLED as they must run with
553 #endif /* CONFIG_SMP */
555 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
557 struct mpic *mpic = mpic_from_irq(irq);
561 cpus_and(tmp, cpumask, cpu_online_map);
563 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
564 mpic_physmask(cpus_addr(tmp)[0]));
567 static struct irq_chip mpic_irq_chip = {
568 .mask = mpic_mask_irq,
569 .unmask = mpic_unmask_irq,
574 static struct irq_chip mpic_ipi_chip = {
575 .mask = mpic_mask_ipi,
576 .unmask = mpic_unmask_ipi,
579 #endif /* CONFIG_SMP */
581 #ifdef CONFIG_MPIC_BROKEN_U3
582 static struct irq_chip mpic_irq_ht_chip = {
583 .startup = mpic_startup_ht_irq,
584 .shutdown = mpic_shutdown_ht_irq,
585 .mask = mpic_mask_irq,
586 .unmask = mpic_unmask_ht_irq,
587 .eoi = mpic_end_ht_irq,
589 #endif /* CONFIG_MPIC_BROKEN_U3 */
597 struct mpic * __init mpic_alloc(unsigned long phys_addr,
599 unsigned int isu_size,
600 unsigned int irq_offset,
601 unsigned int irq_count,
602 unsigned int ipi_offset,
603 unsigned char *senses,
604 unsigned int senses_count,
612 mpic = alloc_bootmem(sizeof(struct mpic));
617 memset(mpic, 0, sizeof(struct mpic));
620 mpic->hc_irq = mpic_irq_chip;
621 mpic->hc_irq.typename = name;
622 if (flags & MPIC_PRIMARY)
623 mpic->hc_irq.set_affinity = mpic_set_affinity;
624 #ifdef CONFIG_MPIC_BROKEN_U3
625 mpic->hc_ht_irq = mpic_irq_ht_chip;
626 mpic->hc_ht_irq.typename = name;
627 if (flags & MPIC_PRIMARY)
628 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
629 #endif /* CONFIG_MPIC_BROKEN_U3 */
631 mpic->hc_ipi.typename = name;
632 mpic->hc_ipi = mpic_ipi_chip;
633 #endif /* CONFIG_SMP */
636 mpic->isu_size = isu_size;
637 mpic->irq_offset = irq_offset;
638 mpic->irq_count = irq_count;
639 mpic->ipi_offset = ipi_offset;
640 mpic->num_sources = 0; /* so far */
641 mpic->senses = senses;
642 mpic->senses_count = senses_count;
644 /* Map the global registers */
645 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
646 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
647 BUG_ON(mpic->gregs == NULL);
650 if (flags & MPIC_WANTS_RESET) {
651 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
652 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
653 | MPIC_GREG_GCONF_RESET);
654 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
655 & MPIC_GREG_GCONF_RESET)
659 /* Read feature register, calculate num CPUs and, for non-ISU
660 * MPICs, num sources as well. On ISU MPICs, sources are counted
663 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
664 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
665 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
667 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
668 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
670 /* Map the per-CPU registers */
671 for (i = 0; i < mpic->num_cpus; i++) {
672 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
673 i * MPIC_CPU_STRIDE, 0x1000);
674 BUG_ON(mpic->cpuregs[i] == NULL);
677 /* Initialize main ISU if none provided */
678 if (mpic->isu_size == 0) {
679 mpic->isu_size = mpic->num_sources;
680 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
681 MPIC_IRQ_STRIDE * mpic->isu_size);
682 BUG_ON(mpic->isus[0] == NULL);
684 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
685 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
687 /* Display version */
688 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
702 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
703 name, vers, phys_addr, mpic->num_cpus);
704 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
705 mpic->isu_shift, mpic->isu_mask);
710 if (flags & MPIC_PRIMARY)
716 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
717 unsigned long phys_addr)
719 unsigned int isu_first = isu_num * mpic->isu_size;
721 BUG_ON(isu_num >= MPIC_MAX_ISU);
723 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
724 if ((isu_first + mpic->isu_size) > mpic->num_sources)
725 mpic->num_sources = isu_first + mpic->isu_size;
728 void __init mpic_init(struct mpic *mpic)
732 BUG_ON(mpic->num_sources == 0);
734 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
736 /* Set current processor priority to max */
737 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
739 /* Initialize timers: just disable them all */
740 for (i = 0; i < 4; i++) {
741 mpic_write(mpic->tmregs,
742 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
743 mpic_write(mpic->tmregs,
744 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
746 (MPIC_VEC_TIMER_0 + i));
749 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
750 mpic_test_broken_ipi(mpic);
751 for (i = 0; i < 4; i++) {
754 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
755 (MPIC_VEC_IPI_0 + i));
757 if (!(mpic->flags & MPIC_PRIMARY))
759 set_irq_chip_data(mpic->ipi_offset+i, mpic);
760 set_irq_chip_and_handler(mpic->ipi_offset+i,
763 #endif /* CONFIG_SMP */
766 /* Initialize interrupt sources */
767 if (mpic->irq_count == 0)
768 mpic->irq_count = mpic->num_sources;
770 #ifdef CONFIG_MPIC_BROKEN_U3
771 /* Do the HT PIC fixups on U3 broken mpic */
772 DBG("MPIC flags: %x\n", mpic->flags);
773 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
774 mpic_scan_ht_pics(mpic);
775 #endif /* CONFIG_MPIC_BROKEN_U3 */
777 for (i = 0; i < mpic->num_sources; i++) {
778 /* start with vector = source number, and masked */
779 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
782 /* if it's an IPI, we skip it */
783 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
784 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
787 /* do senses munging */
788 if (mpic->senses && i < mpic->senses_count) {
789 if (mpic->senses[i] & IRQ_SENSE_LEVEL)
790 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
791 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
792 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
794 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
796 /* remember if it was a level interrupts */
797 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
799 /* deal with broken U3 */
800 if (mpic->flags & MPIC_BROKEN_U3) {
801 #ifdef CONFIG_MPIC_BROKEN_U3
802 if (mpic_is_ht_interrupt(mpic, i)) {
803 vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
804 MPIC_VECPRI_POLARITY_MASK);
805 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
808 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
812 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
816 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
817 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
818 1 << hard_smp_processor_id());
820 /* init linux descriptors */
821 if (i < mpic->irq_count) {
822 struct irq_chip *chip = &mpic->hc_irq;
824 irq_desc[mpic->irq_offset+i].status |=
825 level ? IRQ_LEVEL : 0;
826 #ifdef CONFIG_MPIC_BROKEN_U3
827 if (mpic_is_ht_interrupt(mpic, i))
828 chip = &mpic->hc_ht_irq;
829 #endif /* CONFIG_MPIC_BROKEN_U3 */
830 set_irq_chip_data(mpic->irq_offset+i, mpic);
831 set_irq_chip_and_handler(mpic->irq_offset+i, chip,
836 /* Init spurrious vector */
837 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
839 /* Disable 8259 passthrough */
840 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
841 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
842 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
844 /* Set current processor priority to 0 */
845 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
848 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
852 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
853 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
854 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
855 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
858 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
862 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
864 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
866 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
867 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
870 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
873 struct mpic *mpic = mpic_find(irq, &is_ipi);
877 spin_lock_irqsave(&mpic_lock, flags);
879 reg = mpic_ipi_read(irq - mpic->ipi_offset) &
880 ~MPIC_VECPRI_PRIORITY_MASK;
881 mpic_ipi_write(irq - mpic->ipi_offset,
882 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
884 reg = mpic_irq_read(irq - mpic->irq_offset,MPIC_IRQ_VECTOR_PRI)
885 & ~MPIC_VECPRI_PRIORITY_MASK;
886 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
887 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
889 spin_unlock_irqrestore(&mpic_lock, flags);
892 unsigned int mpic_irq_get_priority(unsigned int irq)
895 struct mpic *mpic = mpic_find(irq, &is_ipi);
899 spin_lock_irqsave(&mpic_lock, flags);
901 reg = mpic_ipi_read(irq - mpic->ipi_offset);
903 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
904 spin_unlock_irqrestore(&mpic_lock, flags);
905 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
908 void mpic_setup_this_cpu(void)
911 struct mpic *mpic = mpic_primary;
913 u32 msk = 1 << hard_smp_processor_id();
916 BUG_ON(mpic == NULL);
918 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
920 spin_lock_irqsave(&mpic_lock, flags);
922 /* let the mpic know we want intrs. default affinity is 0xffffffff
923 * until changed via /proc. That's how it's done on x86. If we want
924 * it differently, then we should make sure we also change the default
925 * values of irq_desc[].affinity in irq.c.
927 if (distribute_irqs) {
928 for (i = 0; i < mpic->num_sources ; i++)
929 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
930 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
933 /* Set current processor priority to 0 */
934 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
936 spin_unlock_irqrestore(&mpic_lock, flags);
937 #endif /* CONFIG_SMP */
940 int mpic_cpu_get_priority(void)
942 struct mpic *mpic = mpic_primary;
944 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
947 void mpic_cpu_set_priority(int prio)
949 struct mpic *mpic = mpic_primary;
951 prio &= MPIC_CPU_TASKPRI_MASK;
952 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
956 * XXX: someone who knows mpic should check this.
957 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
958 * or can we reset the mpic in the new kernel?
960 void mpic_teardown_this_cpu(int secondary)
962 struct mpic *mpic = mpic_primary;
964 u32 msk = 1 << hard_smp_processor_id();
967 BUG_ON(mpic == NULL);
969 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
970 spin_lock_irqsave(&mpic_lock, flags);
972 /* let the mpic know we don't want intrs. */
973 for (i = 0; i < mpic->num_sources ; i++)
974 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
975 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
977 /* Set current processor priority to max */
978 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
980 spin_unlock_irqrestore(&mpic_lock, flags);
984 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
986 struct mpic *mpic = mpic_primary;
988 BUG_ON(mpic == NULL);
991 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
994 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
995 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
998 int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
1002 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
1004 DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
1006 if (unlikely(irq == MPIC_VEC_SPURRIOUS))
1008 if (irq < MPIC_VEC_IPI_0) {
1010 DBG("%s: irq %d\n", mpic->name, irq + mpic->irq_offset);
1012 return irq + mpic->irq_offset;
1015 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
1017 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
1020 int mpic_get_irq(struct pt_regs *regs)
1022 struct mpic *mpic = mpic_primary;
1024 BUG_ON(mpic == NULL);
1026 return mpic_get_one_irq(mpic, regs);
1031 void mpic_request_ipis(void)
1033 struct mpic *mpic = mpic_primary;
1035 BUG_ON(mpic == NULL);
1037 printk("requesting IPIs ... \n");
1040 * IPIs are marked IRQF_DISABLED as they must run with irqs
1043 request_irq(mpic->ipi_offset+0, mpic_ipi_action, IRQF_DISABLED,
1044 "IPI0 (call function)", mpic);
1045 request_irq(mpic->ipi_offset+1, mpic_ipi_action, IRQF_DISABLED,
1046 "IPI1 (reschedule)", mpic);
1047 request_irq(mpic->ipi_offset+2, mpic_ipi_action, IRQF_DISABLED,
1048 "IPI2 (unused)", mpic);
1049 request_irq(mpic->ipi_offset+3, mpic_ipi_action, IRQF_DISABLED,
1050 "IPI3 (debugger break)", mpic);
1052 printk("IPIs requested... \n");
1055 void smp_mpic_message_pass(int target, int msg)
1057 /* make sure we're sending something that translates to an IPI */
1058 if ((unsigned int)msg > 3) {
1059 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1060 smp_processor_id(), msg);
1065 mpic_send_ipi(msg, 0xffffffff);
1067 case MSG_ALL_BUT_SELF:
1068 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1071 mpic_send_ipi(msg, 1 << target);
1075 #endif /* CONFIG_SMP */