2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
17 #include <linux/config.h>
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/smp.h>
23 #include <linux/interrupt.h>
24 #include <linux/bootmem.h>
25 #include <linux/spinlock.h>
26 #include <linux/pci.h>
28 #include <asm/ptrace.h>
29 #include <asm/signal.h>
31 #include <asm/pgtable.h>
33 #include <asm/machdep.h>
38 #define DBG(fmt...) printk(fmt)
43 static struct mpic *mpics;
44 static struct mpic *mpic_primary;
45 static DEFINE_SPINLOCK(mpic_lock);
47 #ifdef CONFIG_PPC32 /* XXX for now */
48 #ifdef CONFIG_IRQ_ALL_CPUS
49 #define distribute_irqs (1)
51 #define distribute_irqs (0)
56 * Register accessor functions
60 static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
64 return in_be32(base + (reg >> 2));
66 return in_le32(base + (reg >> 2));
69 static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
70 unsigned int reg, u32 value)
73 out_be32(base + (reg >> 2), value);
75 out_le32(base + (reg >> 2), value);
78 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
80 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
81 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
83 if (mpic->flags & MPIC_BROKEN_IPI)
85 return _mpic_read(be, mpic->gregs, offset);
88 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
90 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
92 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
95 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
99 if (mpic->flags & MPIC_PRIMARY)
100 cpu = hard_smp_processor_id();
102 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg);
105 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
107 unsigned int cpu = 0;
109 if (mpic->flags & MPIC_PRIMARY)
110 cpu = hard_smp_processor_id();
112 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
115 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
117 unsigned int isu = src_no >> mpic->isu_shift;
118 unsigned int idx = src_no & mpic->isu_mask;
120 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
121 reg + (idx * MPIC_IRQ_STRIDE));
124 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
125 unsigned int reg, u32 value)
127 unsigned int isu = src_no >> mpic->isu_shift;
128 unsigned int idx = src_no & mpic->isu_mask;
130 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
131 reg + (idx * MPIC_IRQ_STRIDE), value);
134 #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
135 #define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
136 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
137 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
138 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
139 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
140 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
141 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
145 * Low level utility functions
150 /* Check if we have one of those nice broken MPICs with a flipped endian on
151 * reads from IPI registers
153 static void __init mpic_test_broken_ipi(struct mpic *mpic)
157 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
158 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
160 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
161 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
162 mpic->flags |= MPIC_BROKEN_IPI;
166 #ifdef CONFIG_MPIC_BROKEN_U3
168 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
169 * to force the edge setting on the MPIC and do the ack workaround.
171 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no)
173 if (source_no >= 128 || !mpic->fixups)
175 return mpic->fixups[source_no].base != NULL;
179 static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
181 struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
183 spin_lock(&mpic->fixup_lock);
184 writeb(0x11 + 2 * fixup->irq, fixup->base + 2);
185 writel(fixup->data, fixup->base + 4);
186 spin_unlock(&mpic->fixup_lock);
190 static void __init mpic_scan_ioapic(struct mpic *mpic, u8 __iomem *devbase)
196 for (pos = readb(devbase + 0x34); pos; pos = readb(devbase + pos + 1)) {
197 u8 id = readb(devbase + pos);
200 id = readb(devbase + pos + 3);
208 printk(KERN_INFO "mpic: - Workarounds @ %p, pos = 0x%02x\n", devbase, pos);
212 writeb(0x01, devbase + 2);
213 n = (readl(devbase + 4) >> 16) & 0xff;
215 for (i = 0; i <= n; i++) {
216 writeb(0x10 + 2 * i, devbase + 2);
217 tmp = readl(devbase + 4);
218 if ((tmp & 0x21) != 0x20)
220 irq = (tmp >> 16) & 0xff;
221 mpic->fixups[irq].irq = i;
222 mpic->fixups[irq].base = devbase;
223 writeb(0x11 + 2 * i, devbase + 2);
224 mpic->fixups[irq].data = readl(devbase + 4) | 0x80000000;
229 static void __init mpic_scan_ioapics(struct mpic *mpic)
232 u8 __iomem *cfgspace;
234 printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n");
236 /* Allocate fixups array */
237 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
238 BUG_ON(mpic->fixups == NULL);
239 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
242 spin_lock_init(&mpic->fixup_lock);
244 /* Map U3 config space. We assume all IO-APICs are on the primary bus
245 * so we only need to map 64kB.
247 cfgspace = ioremap(0xf2000000, 0x10000);
248 BUG_ON(cfgspace == NULL);
250 /* Now we scan all slots. We do a very quick scan, we read the header type,
251 * vendor ID and device ID only, that's plenty enough
253 for (devfn = 0; devfn < 0x100; devfn++) {
254 u8 __iomem *devbase = cfgspace + (devfn << 8);
255 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
256 u32 l = readl(devbase + PCI_VENDOR_ID);
258 DBG("devfn %x, l: %x\n", devfn, l);
260 /* If no device, skip */
261 if (l == 0xffffffff || l == 0x00000000 ||
262 l == 0x0000ffff || l == 0xffff0000)
265 mpic_scan_ioapic(mpic, devbase);
268 /* next device, if function 0 */
269 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
274 #endif /* CONFIG_MPIC_BROKEN_U3 */
277 /* Find an mpic associated with a given linux interrupt */
278 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
280 struct mpic *mpic = mpics;
283 /* search IPIs first since they may override the main interrupts */
284 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
289 if (irq >= mpic->irq_offset &&
290 irq < (mpic->irq_offset + mpic->irq_count)) {
300 /* Convert a cpu mask from logical to physical cpu numbers. */
301 static inline u32 mpic_physmask(u32 cpumask)
306 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
307 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
312 /* Get the mpic structure from the IPI number */
313 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
315 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
319 /* Get the mpic structure from the irq number */
320 static inline struct mpic * mpic_from_irq(unsigned int irq)
322 return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
326 static inline void mpic_eoi(struct mpic *mpic)
328 mpic_cpu_write(MPIC_CPU_EOI, 0);
329 (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
333 static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
335 struct mpic *mpic = dev_id;
337 smp_message_recv(irq - mpic->ipi_offset, regs);
340 #endif /* CONFIG_SMP */
343 * Linux descriptor level callbacks
347 static void mpic_enable_irq(unsigned int irq)
349 unsigned int loops = 100000;
350 struct mpic *mpic = mpic_from_irq(irq);
351 unsigned int src = irq - mpic->irq_offset;
353 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
355 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
356 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
359 /* make sure mask gets to controller before we return to user */
362 printk(KERN_ERR "mpic_enable_irq timeout\n");
365 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
368 static void mpic_disable_irq(unsigned int irq)
370 unsigned int loops = 100000;
371 struct mpic *mpic = mpic_from_irq(irq);
372 unsigned int src = irq - mpic->irq_offset;
374 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
376 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
377 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
380 /* make sure mask gets to controller before we return to user */
383 printk(KERN_ERR "mpic_enable_irq timeout\n");
386 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
389 static void mpic_end_irq(unsigned int irq)
391 struct mpic *mpic = mpic_from_irq(irq);
393 DBG("%s: end_irq: %d\n", mpic->name, irq);
395 /* We always EOI on end_irq() even for edge interrupts since that
396 * should only lower the priority, the MPIC should have properly
397 * latched another edge interrupt coming in anyway
400 #ifdef CONFIG_MPIC_BROKEN_U3
401 if (mpic->flags & MPIC_BROKEN_U3) {
402 unsigned int src = irq - mpic->irq_offset;
403 if (mpic_is_ht_interrupt(mpic, src))
404 mpic_apic_end_irq(mpic, src);
406 #endif /* CONFIG_MPIC_BROKEN_U3 */
413 static void mpic_enable_ipi(unsigned int irq)
415 struct mpic *mpic = mpic_from_ipi(irq);
416 unsigned int src = irq - mpic->ipi_offset;
418 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
419 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
422 static void mpic_disable_ipi(unsigned int irq)
424 /* NEVER disable an IPI... that's just plain wrong! */
427 static void mpic_end_ipi(unsigned int irq)
429 struct mpic *mpic = mpic_from_ipi(irq);
432 * IPIs are marked IRQ_PER_CPU. This has the side effect of
433 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
434 * applying to them. We EOI them late to avoid re-entering.
435 * We mark IPI's with SA_INTERRUPT as they must run with
441 #endif /* CONFIG_SMP */
443 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
445 struct mpic *mpic = mpic_from_irq(irq);
449 cpus_and(tmp, cpumask, cpu_online_map);
451 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
452 mpic_physmask(cpus_addr(tmp)[0]));
461 struct mpic * __init mpic_alloc(unsigned long phys_addr,
463 unsigned int isu_size,
464 unsigned int irq_offset,
465 unsigned int irq_count,
466 unsigned int ipi_offset,
467 unsigned char *senses,
468 unsigned int senses_count,
476 mpic = alloc_bootmem(sizeof(struct mpic));
481 memset(mpic, 0, sizeof(struct mpic));
484 mpic->hc_irq.typename = name;
485 mpic->hc_irq.enable = mpic_enable_irq;
486 mpic->hc_irq.disable = mpic_disable_irq;
487 mpic->hc_irq.end = mpic_end_irq;
488 if (flags & MPIC_PRIMARY)
489 mpic->hc_irq.set_affinity = mpic_set_affinity;
491 mpic->hc_ipi.typename = name;
492 mpic->hc_ipi.enable = mpic_enable_ipi;
493 mpic->hc_ipi.disable = mpic_disable_ipi;
494 mpic->hc_ipi.end = mpic_end_ipi;
495 #endif /* CONFIG_SMP */
498 mpic->isu_size = isu_size;
499 mpic->irq_offset = irq_offset;
500 mpic->irq_count = irq_count;
501 mpic->ipi_offset = ipi_offset;
502 mpic->num_sources = 0; /* so far */
503 mpic->senses = senses;
504 mpic->senses_count = senses_count;
506 /* Map the global registers */
507 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
508 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
509 BUG_ON(mpic->gregs == NULL);
512 if (flags & MPIC_WANTS_RESET) {
513 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
514 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
515 | MPIC_GREG_GCONF_RESET);
516 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
517 & MPIC_GREG_GCONF_RESET)
521 /* Read feature register, calculate num CPUs and, for non-ISU
522 * MPICs, num sources as well. On ISU MPICs, sources are counted
525 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
526 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
527 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
529 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
530 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
532 /* Map the per-CPU registers */
533 for (i = 0; i < mpic->num_cpus; i++) {
534 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
535 i * MPIC_CPU_STRIDE, 0x1000);
536 BUG_ON(mpic->cpuregs[i] == NULL);
539 /* Initialize main ISU if none provided */
540 if (mpic->isu_size == 0) {
541 mpic->isu_size = mpic->num_sources;
542 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
543 MPIC_IRQ_STRIDE * mpic->isu_size);
544 BUG_ON(mpic->isus[0] == NULL);
546 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
547 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
549 /* Display version */
550 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
564 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
565 name, vers, phys_addr, mpic->num_cpus);
566 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
567 mpic->isu_shift, mpic->isu_mask);
572 if (flags & MPIC_PRIMARY)
578 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
579 unsigned long phys_addr)
581 unsigned int isu_first = isu_num * mpic->isu_size;
583 BUG_ON(isu_num >= MPIC_MAX_ISU);
585 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
586 if ((isu_first + mpic->isu_size) > mpic->num_sources)
587 mpic->num_sources = isu_first + mpic->isu_size;
590 void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler,
593 struct mpic *mpic = mpic_find(irq, NULL);
596 /* Synchronization here is a bit dodgy, so don't try to replace cascade
597 * interrupts on the fly too often ... but normally it's set up at boot.
599 spin_lock_irqsave(&mpic_lock, flags);
601 mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset);
602 mpic->cascade = NULL;
604 mpic->cascade_vec = irq - mpic->irq_offset;
605 mpic->cascade_data = data;
607 mpic->cascade = handler;
608 mpic_enable_irq(irq);
609 spin_unlock_irqrestore(&mpic_lock, flags);
612 void __init mpic_init(struct mpic *mpic)
616 BUG_ON(mpic->num_sources == 0);
618 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
620 /* Set current processor priority to max */
621 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
623 /* Initialize timers: just disable them all */
624 for (i = 0; i < 4; i++) {
625 mpic_write(mpic->tmregs,
626 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
627 mpic_write(mpic->tmregs,
628 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
630 (MPIC_VEC_TIMER_0 + i));
633 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
634 mpic_test_broken_ipi(mpic);
635 for (i = 0; i < 4; i++) {
638 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
639 (MPIC_VEC_IPI_0 + i));
641 if (!(mpic->flags & MPIC_PRIMARY))
643 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
644 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
645 #endif /* CONFIG_SMP */
648 /* Initialize interrupt sources */
649 if (mpic->irq_count == 0)
650 mpic->irq_count = mpic->num_sources;
652 #ifdef CONFIG_MPIC_BROKEN_U3
653 /* Do the ioapic fixups on U3 broken mpic */
654 DBG("MPIC flags: %x\n", mpic->flags);
655 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
656 mpic_scan_ioapics(mpic);
657 #endif /* CONFIG_MPIC_BROKEN_U3 */
659 for (i = 0; i < mpic->num_sources; i++) {
660 /* start with vector = source number, and masked */
661 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
664 /* if it's an IPI, we skip it */
665 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
666 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
669 /* do senses munging */
670 if (mpic->senses && i < mpic->senses_count) {
671 if (mpic->senses[i] & IRQ_SENSE_LEVEL)
672 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
673 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
674 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
676 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
678 /* remember if it was a level interrupts */
679 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
681 /* deal with broken U3 */
682 if (mpic->flags & MPIC_BROKEN_U3) {
683 #ifdef CONFIG_MPIC_BROKEN_U3
684 if (mpic_is_ht_interrupt(mpic, i)) {
685 vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
686 MPIC_VECPRI_POLARITY_MASK);
687 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
690 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
694 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
698 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
699 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
700 1 << hard_smp_processor_id());
702 /* init linux descriptors */
703 if (i < mpic->irq_count) {
704 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
705 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
709 /* Init spurrious vector */
710 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
712 /* Disable 8259 passthrough */
713 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
714 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
715 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
717 /* Set current processor priority to 0 */
718 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
723 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
726 struct mpic *mpic = mpic_find(irq, &is_ipi);
730 spin_lock_irqsave(&mpic_lock, flags);
732 reg = mpic_ipi_read(irq - mpic->ipi_offset) &
733 ~MPIC_VECPRI_PRIORITY_MASK;
734 mpic_ipi_write(irq - mpic->ipi_offset,
735 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
737 reg = mpic_irq_read(irq - mpic->irq_offset,MPIC_IRQ_VECTOR_PRI)
738 & ~MPIC_VECPRI_PRIORITY_MASK;
739 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
740 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
742 spin_unlock_irqrestore(&mpic_lock, flags);
745 unsigned int mpic_irq_get_priority(unsigned int irq)
748 struct mpic *mpic = mpic_find(irq, &is_ipi);
752 spin_lock_irqsave(&mpic_lock, flags);
754 reg = mpic_ipi_read(irq - mpic->ipi_offset);
756 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
757 spin_unlock_irqrestore(&mpic_lock, flags);
758 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
761 void mpic_setup_this_cpu(void)
764 struct mpic *mpic = mpic_primary;
766 u32 msk = 1 << hard_smp_processor_id();
769 BUG_ON(mpic == NULL);
771 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
773 spin_lock_irqsave(&mpic_lock, flags);
775 /* let the mpic know we want intrs. default affinity is 0xffffffff
776 * until changed via /proc. That's how it's done on x86. If we want
777 * it differently, then we should make sure we also change the default
778 * values of irq_affinity in irq.c.
780 if (distribute_irqs) {
781 for (i = 0; i < mpic->num_sources ; i++)
782 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
783 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
786 /* Set current processor priority to 0 */
787 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
789 spin_unlock_irqrestore(&mpic_lock, flags);
790 #endif /* CONFIG_SMP */
793 int mpic_cpu_get_priority(void)
795 struct mpic *mpic = mpic_primary;
797 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
800 void mpic_cpu_set_priority(int prio)
802 struct mpic *mpic = mpic_primary;
804 prio &= MPIC_CPU_TASKPRI_MASK;
805 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
809 * XXX: someone who knows mpic should check this.
810 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
811 * or can we reset the mpic in the new kernel?
813 void mpic_teardown_this_cpu(int secondary)
815 struct mpic *mpic = mpic_primary;
817 u32 msk = 1 << hard_smp_processor_id();
820 BUG_ON(mpic == NULL);
822 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
823 spin_lock_irqsave(&mpic_lock, flags);
825 /* let the mpic know we don't want intrs. */
826 for (i = 0; i < mpic->num_sources ; i++)
827 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
828 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
830 /* Set current processor priority to max */
831 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
833 spin_unlock_irqrestore(&mpic_lock, flags);
837 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
839 struct mpic *mpic = mpic_primary;
841 BUG_ON(mpic == NULL);
843 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
845 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
846 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
849 int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
853 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
854 DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
856 if (mpic->cascade && irq == mpic->cascade_vec) {
857 DBG("%s: cascading ...\n", mpic->name);
858 irq = mpic->cascade(regs, mpic->cascade_data);
862 if (unlikely(irq == MPIC_VEC_SPURRIOUS))
864 if (irq < MPIC_VEC_IPI_0)
865 return irq + mpic->irq_offset;
866 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
867 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
870 int mpic_get_irq(struct pt_regs *regs)
872 struct mpic *mpic = mpic_primary;
874 BUG_ON(mpic == NULL);
876 return mpic_get_one_irq(mpic, regs);
881 void mpic_request_ipis(void)
883 struct mpic *mpic = mpic_primary;
885 BUG_ON(mpic == NULL);
887 printk("requesting IPIs ... \n");
889 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
890 request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT,
891 "IPI0 (call function)", mpic);
892 request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT,
893 "IPI1 (reschedule)", mpic);
894 request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT,
895 "IPI2 (unused)", mpic);
896 request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT,
897 "IPI3 (debugger break)", mpic);
899 printk("IPIs requested... \n");
902 void smp_mpic_message_pass(int target, int msg)
904 /* make sure we're sending something that translates to an IPI */
905 if ((unsigned int)msg > 3) {
906 printk("SMP %d: smp_message_pass: unknown msg %d\n",
907 smp_processor_id(), msg);
912 mpic_send_ipi(msg, 0xffffffff);
914 case MSG_ALL_BUT_SELF:
915 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
918 mpic_send_ipi(msg, 1 << target);
922 #endif /* CONFIG_SMP */