2 * arch/powerpc/sysdev/ipic.c
4 * IPIC routines implementations.
6 * Copyright 2005 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
32 static struct ipic * primary_ipic;
33 static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
34 static DEFINE_SPINLOCK(ipic_lock);
36 static struct ipic_info ipic_info[] = {
40 .force = IPIC_SIFCR_H,
47 .force = IPIC_SIFCR_H,
54 .force = IPIC_SIFCR_H,
61 .force = IPIC_SIFCR_H,
68 .force = IPIC_SIFCR_H,
75 .force = IPIC_SIFCR_H,
82 .force = IPIC_SIFCR_H,
89 .force = IPIC_SIFCR_H,
96 .force = IPIC_SIFCR_H,
101 .mask = IPIC_SIMSR_H,
102 .prio = IPIC_SIPRR_D,
103 .force = IPIC_SIFCR_H,
108 .mask = IPIC_SIMSR_H,
109 .prio = IPIC_SIPRR_D,
110 .force = IPIC_SIFCR_H,
115 .mask = IPIC_SIMSR_H,
116 .prio = IPIC_SIPRR_D,
117 .force = IPIC_SIFCR_H,
122 .mask = IPIC_SIMSR_H,
123 .prio = IPIC_SIPRR_D,
124 .force = IPIC_SIFCR_H,
129 .mask = IPIC_SIMSR_H,
130 .prio = IPIC_SIPRR_D,
131 .force = IPIC_SIFCR_H,
136 .mask = IPIC_SIMSR_H,
137 .prio = IPIC_SIPRR_D,
138 .force = IPIC_SIFCR_H,
143 .mask = IPIC_SIMSR_H,
144 .prio = IPIC_SIPRR_D,
145 .force = IPIC_SIFCR_H,
152 .prio = IPIC_SMPRR_A,
160 .prio = IPIC_SMPRR_A,
168 .prio = IPIC_SMPRR_A,
176 .prio = IPIC_SMPRR_B,
184 .prio = IPIC_SMPRR_B,
192 .prio = IPIC_SMPRR_B,
200 .prio = IPIC_SMPRR_B,
206 .mask = IPIC_SIMSR_H,
207 .prio = IPIC_SIPRR_A,
208 .force = IPIC_SIFCR_H,
213 .mask = IPIC_SIMSR_H,
214 .prio = IPIC_SIPRR_A,
215 .force = IPIC_SIFCR_H,
220 .mask = IPIC_SIMSR_H,
221 .prio = IPIC_SIPRR_A,
222 .force = IPIC_SIFCR_H,
227 .mask = IPIC_SIMSR_H,
228 .prio = IPIC_SIPRR_A,
229 .force = IPIC_SIFCR_H,
234 .mask = IPIC_SIMSR_H,
235 .prio = IPIC_SIPRR_A,
236 .force = IPIC_SIFCR_H,
241 .mask = IPIC_SIMSR_H,
242 .prio = IPIC_SIPRR_A,
243 .force = IPIC_SIFCR_H,
248 .mask = IPIC_SIMSR_H,
249 .prio = IPIC_SIPRR_A,
250 .force = IPIC_SIFCR_H,
255 .mask = IPIC_SIMSR_H,
256 .prio = IPIC_SIPRR_A,
257 .force = IPIC_SIFCR_H,
262 .mask = IPIC_SIMSR_H,
263 .prio = IPIC_SIPRR_B,
264 .force = IPIC_SIFCR_H,
269 .mask = IPIC_SIMSR_H,
270 .prio = IPIC_SIPRR_B,
271 .force = IPIC_SIFCR_H,
276 .mask = IPIC_SIMSR_H,
277 .prio = IPIC_SIPRR_B,
278 .force = IPIC_SIFCR_H,
283 .mask = IPIC_SIMSR_H,
284 .prio = IPIC_SIPRR_B,
285 .force = IPIC_SIFCR_H,
290 .mask = IPIC_SIMSR_H,
291 .prio = IPIC_SIPRR_B,
292 .force = IPIC_SIFCR_H,
297 .mask = IPIC_SIMSR_H,
298 .prio = IPIC_SIPRR_B,
299 .force = IPIC_SIFCR_H,
304 .mask = IPIC_SIMSR_H,
305 .prio = IPIC_SIPRR_B,
306 .force = IPIC_SIFCR_H,
311 .mask = IPIC_SIMSR_H,
312 .prio = IPIC_SIPRR_B,
313 .force = IPIC_SIFCR_H,
319 .prio = IPIC_SMPRR_A,
325 .mask = IPIC_SIMSR_L,
326 .prio = IPIC_SMPRR_A,
327 .force = IPIC_SIFCR_L,
332 .mask = IPIC_SIMSR_L,
333 .prio = IPIC_SMPRR_A,
334 .force = IPIC_SIFCR_L,
339 .mask = IPIC_SIMSR_L,
340 .prio = IPIC_SMPRR_A,
341 .force = IPIC_SIFCR_L,
346 .mask = IPIC_SIMSR_L,
347 .prio = IPIC_SMPRR_A,
348 .force = IPIC_SIFCR_L,
353 .mask = IPIC_SIMSR_L,
354 .prio = IPIC_SMPRR_B,
355 .force = IPIC_SIFCR_L,
360 .mask = IPIC_SIMSR_L,
361 .prio = IPIC_SMPRR_B,
362 .force = IPIC_SIFCR_L,
367 .mask = IPIC_SIMSR_L,
368 .prio = IPIC_SMPRR_B,
369 .force = IPIC_SIFCR_L,
374 .mask = IPIC_SIMSR_L,
375 .prio = IPIC_SMPRR_B,
376 .force = IPIC_SIFCR_L,
381 .mask = IPIC_SIMSR_L,
383 .force = IPIC_SIFCR_L,
387 .mask = IPIC_SIMSR_L,
389 .force = IPIC_SIFCR_L,
393 .mask = IPIC_SIMSR_L,
395 .force = IPIC_SIFCR_L,
399 .mask = IPIC_SIMSR_L,
401 .force = IPIC_SIFCR_L,
405 .mask = IPIC_SIMSR_L,
407 .force = IPIC_SIFCR_L,
411 .mask = IPIC_SIMSR_L,
413 .force = IPIC_SIFCR_L,
417 .mask = IPIC_SIMSR_L,
419 .force = IPIC_SIFCR_L,
423 .mask = IPIC_SIMSR_L,
425 .force = IPIC_SIFCR_L,
429 .mask = IPIC_SIMSR_L,
431 .force = IPIC_SIFCR_L,
435 .mask = IPIC_SIMSR_L,
437 .force = IPIC_SIFCR_L,
441 .mask = IPIC_SIMSR_L,
443 .force = IPIC_SIFCR_L,
447 .mask = IPIC_SIMSR_L,
449 .force = IPIC_SIFCR_L,
453 .mask = IPIC_SIMSR_L,
455 .force = IPIC_SIFCR_L,
459 .mask = IPIC_SIMSR_L,
461 .force = IPIC_SIFCR_L,
465 .mask = IPIC_SIMSR_L,
467 .force = IPIC_SIFCR_L,
471 .mask = IPIC_SIMSR_L,
473 .force = IPIC_SIFCR_L,
477 .mask = IPIC_SIMSR_L,
479 .force = IPIC_SIFCR_L,
483 .mask = IPIC_SIMSR_L,
485 .force = IPIC_SIFCR_L,
489 .mask = IPIC_SIMSR_L,
491 .force = IPIC_SIFCR_L,
495 .mask = IPIC_SIMSR_L,
497 .force = IPIC_SIFCR_L,
502 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
504 return in_be32(base + (reg >> 2));
507 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
509 out_be32(base + (reg >> 2), value);
512 static inline struct ipic * ipic_from_irq(unsigned int virq)
517 #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
519 static void ipic_unmask_irq(unsigned int virq)
521 struct ipic *ipic = ipic_from_irq(virq);
522 unsigned int src = ipic_irq_to_hw(virq);
526 spin_lock_irqsave(&ipic_lock, flags);
528 temp = ipic_read(ipic->regs, ipic_info[src].mask);
529 temp |= (1 << (31 - ipic_info[src].bit));
530 ipic_write(ipic->regs, ipic_info[src].mask, temp);
532 spin_unlock_irqrestore(&ipic_lock, flags);
535 static void ipic_mask_irq(unsigned int virq)
537 struct ipic *ipic = ipic_from_irq(virq);
538 unsigned int src = ipic_irq_to_hw(virq);
542 spin_lock_irqsave(&ipic_lock, flags);
544 temp = ipic_read(ipic->regs, ipic_info[src].mask);
545 temp &= ~(1 << (31 - ipic_info[src].bit));
546 ipic_write(ipic->regs, ipic_info[src].mask, temp);
548 /* mb() can't guarantee that masking is finished. But it does finish
549 * for nearly all cases. */
552 spin_unlock_irqrestore(&ipic_lock, flags);
555 static void ipic_ack_irq(unsigned int virq)
557 struct ipic *ipic = ipic_from_irq(virq);
558 unsigned int src = ipic_irq_to_hw(virq);
562 spin_lock_irqsave(&ipic_lock, flags);
564 temp = ipic_read(ipic->regs, ipic_info[src].ack);
565 temp |= (1 << (31 - ipic_info[src].bit));
566 ipic_write(ipic->regs, ipic_info[src].ack, temp);
568 /* mb() can't guarantee that ack is finished. But it does finish
569 * for nearly all cases. */
572 spin_unlock_irqrestore(&ipic_lock, flags);
575 static void ipic_mask_irq_and_ack(unsigned int virq)
577 struct ipic *ipic = ipic_from_irq(virq);
578 unsigned int src = ipic_irq_to_hw(virq);
582 spin_lock_irqsave(&ipic_lock, flags);
584 temp = ipic_read(ipic->regs, ipic_info[src].mask);
585 temp &= ~(1 << (31 - ipic_info[src].bit));
586 ipic_write(ipic->regs, ipic_info[src].mask, temp);
588 temp = ipic_read(ipic->regs, ipic_info[src].ack);
589 temp |= (1 << (31 - ipic_info[src].bit));
590 ipic_write(ipic->regs, ipic_info[src].ack, temp);
592 /* mb() can't guarantee that ack is finished. But it does finish
593 * for nearly all cases. */
596 spin_unlock_irqrestore(&ipic_lock, flags);
599 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
601 struct ipic *ipic = ipic_from_irq(virq);
602 unsigned int src = ipic_irq_to_hw(virq);
603 struct irq_desc *desc = get_irq_desc(virq);
604 unsigned int vold, vnew, edibit;
606 if (flow_type == IRQ_TYPE_NONE)
607 flow_type = IRQ_TYPE_LEVEL_LOW;
609 /* ipic supports only low assertion and high-to-low change senses
611 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
612 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
616 /* ipic supports only edge mode on external interrupts */
617 if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
618 printk(KERN_ERR "ipic: edge sense not supported on internal "
623 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
624 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
625 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
626 desc->status |= IRQ_LEVEL;
627 desc->handle_irq = handle_level_irq;
628 desc->chip = &ipic_level_irq_chip;
630 desc->handle_irq = handle_edge_irq;
631 desc->chip = &ipic_edge_irq_chip;
634 /* only EXT IRQ senses are programmable on ipic
635 * internal IRQ senses are LEVEL_LOW
637 if (src == IPIC_IRQ_EXT0)
640 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
641 edibit = (14 - (src - IPIC_IRQ_EXT1));
643 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
645 vold = ipic_read(ipic->regs, IPIC_SECNR);
646 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
647 vnew = vold | (1 << edibit);
649 vnew = vold & ~(1 << edibit);
652 ipic_write(ipic->regs, IPIC_SECNR, vnew);
656 /* level interrupts and edge interrupts have different ack operations */
657 static struct irq_chip ipic_level_irq_chip = {
658 .typename = " IPIC ",
659 .unmask = ipic_unmask_irq,
660 .mask = ipic_mask_irq,
661 .mask_ack = ipic_mask_irq,
662 .set_type = ipic_set_irq_type,
665 static struct irq_chip ipic_edge_irq_chip = {
666 .typename = " IPIC ",
667 .unmask = ipic_unmask_irq,
668 .mask = ipic_mask_irq,
669 .mask_ack = ipic_mask_irq_and_ack,
671 .set_type = ipic_set_irq_type,
674 static int ipic_host_match(struct irq_host *h, struct device_node *node)
676 /* Exact match, unless ipic node is NULL */
677 return h->of_node == NULL || h->of_node == node;
680 static int ipic_host_map(struct irq_host *h, unsigned int virq,
683 struct ipic *ipic = h->host_data;
685 set_irq_chip_data(virq, ipic);
686 set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
688 /* Set default irq type */
689 set_irq_type(virq, IRQ_TYPE_NONE);
694 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
695 u32 *intspec, unsigned int intsize,
696 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
699 /* interrupt sense values coming from the device tree equal either
700 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
702 *out_hwirq = intspec[0];
704 *out_flags = intspec[1];
706 *out_flags = IRQ_TYPE_NONE;
710 static struct irq_host_ops ipic_host_ops = {
711 .match = ipic_host_match,
712 .map = ipic_host_map,
713 .xlate = ipic_host_xlate,
716 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
722 ipic = alloc_bootmem(sizeof(struct ipic));
726 memset(ipic, 0, sizeof(struct ipic));
728 ipic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
731 if (ipic->irqhost == NULL) {
736 ret = of_address_to_resource(node, 0, &res);
742 ipic->regs = ioremap(res.start, res.end - res.start + 1);
744 ipic->irqhost->host_data = ipic;
747 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
749 /* default priority scheme is grouped. If spread mode is required
750 * configure SICFR accordingly */
751 if (flags & IPIC_SPREADMODE_GRP_A)
753 if (flags & IPIC_SPREADMODE_GRP_B)
755 if (flags & IPIC_SPREADMODE_GRP_C)
757 if (flags & IPIC_SPREADMODE_GRP_D)
759 if (flags & IPIC_SPREADMODE_MIX_A)
761 if (flags & IPIC_SPREADMODE_MIX_B)
764 ipic_write(ipic->regs, IPIC_SICFR, temp);
766 /* handle MCP route */
768 if (flags & IPIC_DISABLE_MCP_OUT)
770 ipic_write(ipic->regs, IPIC_SERCR, temp);
772 /* handle routing of IRQ0 to MCP */
773 temp = ipic_read(ipic->regs, IPIC_SEMSR);
775 if (flags & IPIC_IRQ0_MCP)
778 temp &= ~SEMSR_SIRQ0;
780 ipic_write(ipic->regs, IPIC_SEMSR, temp);
783 irq_set_default_host(primary_ipic->irqhost);
785 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
791 int ipic_set_priority(unsigned int virq, unsigned int priority)
793 struct ipic *ipic = ipic_from_irq(virq);
794 unsigned int src = ipic_irq_to_hw(virq);
801 if (ipic_info[src].prio == 0)
804 temp = ipic_read(ipic->regs, ipic_info[src].prio);
807 temp &= ~(0x7 << (20 + (3 - priority) * 3));
808 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
810 temp &= ~(0x7 << (4 + (7 - priority) * 3));
811 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
814 ipic_write(ipic->regs, ipic_info[src].prio, temp);
819 void ipic_set_highest_priority(unsigned int virq)
821 struct ipic *ipic = ipic_from_irq(virq);
822 unsigned int src = ipic_irq_to_hw(virq);
825 temp = ipic_read(ipic->regs, IPIC_SICFR);
827 /* clear and set HPI */
829 temp |= (src & 0x7f) << 24;
831 ipic_write(ipic->regs, IPIC_SICFR, temp);
834 void ipic_set_default_priority(void)
836 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
837 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
838 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
839 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
840 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
841 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
844 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
846 struct ipic *ipic = primary_ipic;
849 temp = ipic_read(ipic->regs, IPIC_SERMR);
850 temp |= (1 << (31 - mcp_irq));
851 ipic_write(ipic->regs, IPIC_SERMR, temp);
854 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
856 struct ipic *ipic = primary_ipic;
859 temp = ipic_read(ipic->regs, IPIC_SERMR);
860 temp &= (1 << (31 - mcp_irq));
861 ipic_write(ipic->regs, IPIC_SERMR, temp);
864 u32 ipic_get_mcp_status(void)
866 return ipic_read(primary_ipic->regs, IPIC_SERMR);
869 void ipic_clear_mcp_status(u32 mask)
871 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
874 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
875 unsigned int ipic_get_irq(void)
879 BUG_ON(primary_ipic == NULL);
881 #define IPIC_SIVCR_VECTOR_MASK 0x7f
882 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
884 if (irq == 0) /* 0 --> no irq is pending */
887 return irq_linear_revmap(primary_ipic->irqhost, irq);
890 static struct sysdev_class ipic_sysclass = {
891 set_kset_name("ipic"),
894 static struct sys_device device_ipic = {
896 .cls = &ipic_sysclass,
899 static int __init init_ipic_sysfs(void)
903 if (!primary_ipic->regs)
905 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
907 rc = sysdev_class_register(&ipic_sysclass);
909 printk(KERN_ERR "Failed registering ipic sys class\n");
912 rc = sysdev_register(&device_ipic);
914 printk(KERN_ERR "Failed registering ipic sys device\n");
920 subsys_initcall(init_ipic_sysfs);