2 * arch/powerpc/sysdev/ipic.c
4 * IPIC routines implementations.
6 * Copyright 2005 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
32 static struct ipic * primary_ipic;
33 static DEFINE_SPINLOCK(ipic_lock);
35 static struct ipic_info ipic_info[] = {
40 .force = IPIC_SIFCR_H,
48 .force = IPIC_SIFCR_H,
56 .force = IPIC_SIFCR_H,
64 .force = IPIC_SIFCR_H,
72 .force = IPIC_SIFCR_H,
80 .force = IPIC_SIFCR_H,
88 .force = IPIC_SIFCR_H,
96 .force = IPIC_SIFCR_H,
101 .pend = IPIC_SIPNR_H,
102 .mask = IPIC_SIMSR_H,
103 .prio = IPIC_SIPRR_D,
104 .force = IPIC_SIFCR_H,
109 .pend = IPIC_SIPNR_H,
110 .mask = IPIC_SIMSR_H,
111 .prio = IPIC_SIPRR_D,
112 .force = IPIC_SIFCR_H,
117 .pend = IPIC_SIPNR_H,
118 .mask = IPIC_SIMSR_H,
119 .prio = IPIC_SIPRR_D,
120 .force = IPIC_SIFCR_H,
127 .prio = IPIC_SMPRR_A,
135 .prio = IPIC_SMPRR_A,
143 .prio = IPIC_SMPRR_A,
151 .prio = IPIC_SMPRR_B,
159 .prio = IPIC_SMPRR_B,
167 .prio = IPIC_SMPRR_B,
175 .prio = IPIC_SMPRR_B,
181 .pend = IPIC_SIPNR_H,
182 .mask = IPIC_SIMSR_H,
183 .prio = IPIC_SIPRR_A,
184 .force = IPIC_SIFCR_H,
189 .pend = IPIC_SIPNR_H,
190 .mask = IPIC_SIMSR_H,
191 .prio = IPIC_SIPRR_A,
192 .force = IPIC_SIFCR_H,
197 .pend = IPIC_SIPNR_H,
198 .mask = IPIC_SIMSR_H,
199 .prio = IPIC_SIPRR_A,
200 .force = IPIC_SIFCR_H,
205 .pend = IPIC_SIPNR_H,
206 .mask = IPIC_SIMSR_H,
207 .prio = IPIC_SIPRR_A,
208 .force = IPIC_SIFCR_H,
213 .pend = IPIC_SIPNR_H,
214 .mask = IPIC_SIMSR_H,
215 .prio = IPIC_SIPRR_A,
216 .force = IPIC_SIFCR_H,
221 .pend = IPIC_SIPNR_H,
222 .mask = IPIC_SIMSR_H,
223 .prio = IPIC_SIPRR_A,
224 .force = IPIC_SIFCR_H,
229 .pend = IPIC_SIPNR_H,
230 .mask = IPIC_SIMSR_H,
231 .prio = IPIC_SIPRR_A,
232 .force = IPIC_SIFCR_H,
237 .pend = IPIC_SIPNR_H,
238 .mask = IPIC_SIMSR_H,
239 .prio = IPIC_SIPRR_A,
240 .force = IPIC_SIFCR_H,
245 .pend = IPIC_SIPNR_H,
246 .mask = IPIC_SIMSR_H,
247 .prio = IPIC_SIPRR_B,
248 .force = IPIC_SIFCR_H,
253 .pend = IPIC_SIPNR_H,
254 .mask = IPIC_SIMSR_H,
255 .prio = IPIC_SIPRR_B,
256 .force = IPIC_SIFCR_H,
261 .pend = IPIC_SIPNR_H,
262 .mask = IPIC_SIMSR_H,
263 .prio = IPIC_SIPRR_B,
264 .force = IPIC_SIFCR_H,
269 .pend = IPIC_SIPNR_H,
270 .mask = IPIC_SIMSR_H,
271 .prio = IPIC_SIPRR_B,
272 .force = IPIC_SIFCR_H,
277 .pend = IPIC_SIPNR_H,
278 .mask = IPIC_SIMSR_H,
279 .prio = IPIC_SIPRR_B,
280 .force = IPIC_SIFCR_H,
287 .prio = IPIC_SMPRR_A,
293 .pend = IPIC_SIPNR_L,
294 .mask = IPIC_SIMSR_L,
295 .prio = IPIC_SMPRR_A,
296 .force = IPIC_SIFCR_L,
301 .pend = IPIC_SIPNR_L,
302 .mask = IPIC_SIMSR_L,
303 .prio = IPIC_SMPRR_A,
304 .force = IPIC_SIFCR_L,
309 .pend = IPIC_SIPNR_L,
310 .mask = IPIC_SIMSR_L,
311 .prio = IPIC_SMPRR_A,
312 .force = IPIC_SIFCR_L,
317 .pend = IPIC_SIPNR_L,
318 .mask = IPIC_SIMSR_L,
319 .prio = IPIC_SMPRR_A,
320 .force = IPIC_SIFCR_L,
325 .pend = IPIC_SIPNR_L,
326 .mask = IPIC_SIMSR_L,
327 .prio = IPIC_SMPRR_B,
328 .force = IPIC_SIFCR_L,
333 .pend = IPIC_SIPNR_L,
334 .mask = IPIC_SIMSR_L,
335 .prio = IPIC_SMPRR_B,
336 .force = IPIC_SIFCR_L,
341 .pend = IPIC_SIPNR_L,
342 .mask = IPIC_SIMSR_L,
343 .prio = IPIC_SMPRR_B,
344 .force = IPIC_SIFCR_L,
349 .pend = IPIC_SIPNR_L,
350 .mask = IPIC_SIMSR_L,
351 .prio = IPIC_SMPRR_B,
352 .force = IPIC_SIFCR_L,
357 .pend = IPIC_SIPNR_L,
358 .mask = IPIC_SIMSR_L,
360 .force = IPIC_SIFCR_L,
364 .pend = IPIC_SIPNR_L,
365 .mask = IPIC_SIMSR_L,
367 .force = IPIC_SIFCR_L,
371 .pend = IPIC_SIPNR_L,
372 .mask = IPIC_SIMSR_L,
374 .force = IPIC_SIFCR_L,
378 .pend = IPIC_SIPNR_L,
379 .mask = IPIC_SIMSR_L,
381 .force = IPIC_SIFCR_L,
385 .pend = IPIC_SIPNR_L,
386 .mask = IPIC_SIMSR_L,
388 .force = IPIC_SIFCR_L,
392 .pend = IPIC_SIPNR_L,
393 .mask = IPIC_SIMSR_L,
395 .force = IPIC_SIFCR_L,
399 .pend = IPIC_SIPNR_L,
400 .mask = IPIC_SIMSR_L,
402 .force = IPIC_SIFCR_L,
406 .pend = IPIC_SIPNR_L,
407 .mask = IPIC_SIMSR_L,
409 .force = IPIC_SIFCR_L,
413 .pend = IPIC_SIPNR_L,
414 .mask = IPIC_SIMSR_L,
416 .force = IPIC_SIFCR_L,
420 .pend = IPIC_SIPNR_L,
421 .mask = IPIC_SIMSR_L,
423 .force = IPIC_SIFCR_L,
427 .pend = IPIC_SIPNR_L,
428 .mask = IPIC_SIMSR_L,
430 .force = IPIC_SIFCR_L,
434 .pend = IPIC_SIPNR_L,
435 .mask = IPIC_SIMSR_L,
437 .force = IPIC_SIFCR_L,
441 .pend = IPIC_SIPNR_L,
442 .mask = IPIC_SIMSR_L,
444 .force = IPIC_SIFCR_L,
448 .pend = IPIC_SIPNR_L,
449 .mask = IPIC_SIMSR_L,
451 .force = IPIC_SIFCR_L,
455 .pend = IPIC_SIPNR_L,
456 .mask = IPIC_SIMSR_L,
458 .force = IPIC_SIFCR_L,
462 .pend = IPIC_SIPNR_L,
463 .mask = IPIC_SIMSR_L,
465 .force = IPIC_SIFCR_L,
469 .pend = IPIC_SIPNR_L,
470 .mask = IPIC_SIMSR_L,
472 .force = IPIC_SIFCR_L,
476 .pend = IPIC_SIPNR_L,
477 .mask = IPIC_SIMSR_L,
479 .force = IPIC_SIFCR_L,
483 .pend = IPIC_SIPNR_L,
484 .mask = IPIC_SIMSR_L,
486 .force = IPIC_SIFCR_L,
491 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
493 return in_be32(base + (reg >> 2));
496 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
498 out_be32(base + (reg >> 2), value);
501 static inline struct ipic * ipic_from_irq(unsigned int virq)
506 #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
508 static void ipic_unmask_irq(unsigned int virq)
510 struct ipic *ipic = ipic_from_irq(virq);
511 unsigned int src = ipic_irq_to_hw(virq);
515 spin_lock_irqsave(&ipic_lock, flags);
517 temp = ipic_read(ipic->regs, ipic_info[src].mask);
518 temp |= (1 << (31 - ipic_info[src].bit));
519 ipic_write(ipic->regs, ipic_info[src].mask, temp);
521 spin_unlock_irqrestore(&ipic_lock, flags);
524 static void ipic_mask_irq(unsigned int virq)
526 struct ipic *ipic = ipic_from_irq(virq);
527 unsigned int src = ipic_irq_to_hw(virq);
531 spin_lock_irqsave(&ipic_lock, flags);
533 temp = ipic_read(ipic->regs, ipic_info[src].mask);
534 temp &= ~(1 << (31 - ipic_info[src].bit));
535 ipic_write(ipic->regs, ipic_info[src].mask, temp);
537 spin_unlock_irqrestore(&ipic_lock, flags);
540 static void ipic_ack_irq(unsigned int virq)
542 struct ipic *ipic = ipic_from_irq(virq);
543 unsigned int src = ipic_irq_to_hw(virq);
547 spin_lock_irqsave(&ipic_lock, flags);
549 temp = ipic_read(ipic->regs, ipic_info[src].pend);
550 temp |= (1 << (31 - ipic_info[src].bit));
551 ipic_write(ipic->regs, ipic_info[src].pend, temp);
553 spin_unlock_irqrestore(&ipic_lock, flags);
556 static void ipic_mask_irq_and_ack(unsigned int virq)
558 struct ipic *ipic = ipic_from_irq(virq);
559 unsigned int src = ipic_irq_to_hw(virq);
563 spin_lock_irqsave(&ipic_lock, flags);
565 temp = ipic_read(ipic->regs, ipic_info[src].mask);
566 temp &= ~(1 << (31 - ipic_info[src].bit));
567 ipic_write(ipic->regs, ipic_info[src].mask, temp);
569 temp = ipic_read(ipic->regs, ipic_info[src].pend);
570 temp |= (1 << (31 - ipic_info[src].bit));
571 ipic_write(ipic->regs, ipic_info[src].pend, temp);
573 spin_unlock_irqrestore(&ipic_lock, flags);
576 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
578 struct ipic *ipic = ipic_from_irq(virq);
579 unsigned int src = ipic_irq_to_hw(virq);
580 struct irq_desc *desc = get_irq_desc(virq);
581 unsigned int vold, vnew, edibit;
583 if (flow_type == IRQ_TYPE_NONE)
584 flow_type = IRQ_TYPE_LEVEL_LOW;
586 /* ipic supports only low assertion and high-to-low change senses
588 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
589 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
594 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
595 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
596 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
597 desc->status |= IRQ_LEVEL;
598 desc->handle_irq = handle_level_irq;
600 desc->handle_irq = handle_edge_irq;
603 /* only EXT IRQ senses are programmable on ipic
604 * internal IRQ senses are LEVEL_LOW
606 if (src == IPIC_IRQ_EXT0)
609 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
610 edibit = (14 - (src - IPIC_IRQ_EXT1));
612 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
614 vold = ipic_read(ipic->regs, IPIC_SECNR);
615 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
616 vnew = vold | (1 << edibit);
618 vnew = vold & ~(1 << edibit);
621 ipic_write(ipic->regs, IPIC_SECNR, vnew);
625 static struct irq_chip ipic_irq_chip = {
626 .typename = " IPIC ",
627 .unmask = ipic_unmask_irq,
628 .mask = ipic_mask_irq,
629 .mask_ack = ipic_mask_irq_and_ack,
631 .set_type = ipic_set_irq_type,
634 static int ipic_host_match(struct irq_host *h, struct device_node *node)
636 /* Exact match, unless ipic node is NULL */
637 return h->of_node == NULL || h->of_node == node;
640 static int ipic_host_map(struct irq_host *h, unsigned int virq,
643 struct ipic *ipic = h->host_data;
644 struct irq_chip *chip;
647 chip = &ipic->hc_irq;
649 set_irq_chip_data(virq, ipic);
650 set_irq_chip_and_handler(virq, chip, handle_level_irq);
652 /* Set default irq type */
653 set_irq_type(virq, IRQ_TYPE_NONE);
658 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
659 u32 *intspec, unsigned int intsize,
660 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
663 /* interrupt sense values coming from the device tree equal either
664 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
666 *out_hwirq = intspec[0];
668 *out_flags = intspec[1];
670 *out_flags = IRQ_TYPE_NONE;
674 static struct irq_host_ops ipic_host_ops = {
675 .match = ipic_host_match,
676 .map = ipic_host_map,
677 .xlate = ipic_host_xlate,
680 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
686 ipic = alloc_bootmem(sizeof(struct ipic));
690 memset(ipic, 0, sizeof(struct ipic));
692 ipic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
695 if (ipic->irqhost == NULL) {
700 ret = of_address_to_resource(node, 0, &res);
706 ipic->regs = ioremap(res.start, res.end - res.start + 1);
708 ipic->irqhost->host_data = ipic;
709 ipic->hc_irq = ipic_irq_chip;
712 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
714 /* default priority scheme is grouped. If spread mode is required
715 * configure SICFR accordingly */
716 if (flags & IPIC_SPREADMODE_GRP_A)
718 if (flags & IPIC_SPREADMODE_GRP_B)
720 if (flags & IPIC_SPREADMODE_GRP_C)
722 if (flags & IPIC_SPREADMODE_GRP_D)
724 if (flags & IPIC_SPREADMODE_MIX_A)
726 if (flags & IPIC_SPREADMODE_MIX_B)
729 ipic_write(ipic->regs, IPIC_SICFR, temp);
731 /* handle MCP route */
733 if (flags & IPIC_DISABLE_MCP_OUT)
735 ipic_write(ipic->regs, IPIC_SERCR, temp);
737 /* handle routing of IRQ0 to MCP */
738 temp = ipic_read(ipic->regs, IPIC_SEMSR);
740 if (flags & IPIC_IRQ0_MCP)
743 temp &= ~SEMSR_SIRQ0;
745 ipic_write(ipic->regs, IPIC_SEMSR, temp);
748 irq_set_default_host(primary_ipic->irqhost);
750 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
756 int ipic_set_priority(unsigned int virq, unsigned int priority)
758 struct ipic *ipic = ipic_from_irq(virq);
759 unsigned int src = ipic_irq_to_hw(virq);
766 if (ipic_info[src].prio == 0)
769 temp = ipic_read(ipic->regs, ipic_info[src].prio);
772 temp &= ~(0x7 << (20 + (3 - priority) * 3));
773 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
775 temp &= ~(0x7 << (4 + (7 - priority) * 3));
776 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
779 ipic_write(ipic->regs, ipic_info[src].prio, temp);
784 void ipic_set_highest_priority(unsigned int virq)
786 struct ipic *ipic = ipic_from_irq(virq);
787 unsigned int src = ipic_irq_to_hw(virq);
790 temp = ipic_read(ipic->regs, IPIC_SICFR);
792 /* clear and set HPI */
794 temp |= (src & 0x7f) << 24;
796 ipic_write(ipic->regs, IPIC_SICFR, temp);
799 void ipic_set_default_priority(void)
801 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
802 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
803 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
804 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
805 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
806 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
809 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
811 struct ipic *ipic = primary_ipic;
814 temp = ipic_read(ipic->regs, IPIC_SERMR);
815 temp |= (1 << (31 - mcp_irq));
816 ipic_write(ipic->regs, IPIC_SERMR, temp);
819 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
821 struct ipic *ipic = primary_ipic;
824 temp = ipic_read(ipic->regs, IPIC_SERMR);
825 temp &= (1 << (31 - mcp_irq));
826 ipic_write(ipic->regs, IPIC_SERMR, temp);
829 u32 ipic_get_mcp_status(void)
831 return ipic_read(primary_ipic->regs, IPIC_SERMR);
834 void ipic_clear_mcp_status(u32 mask)
836 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
839 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
840 unsigned int ipic_get_irq(void)
844 BUG_ON(primary_ipic == NULL);
846 #define IPIC_SIVCR_VECTOR_MASK 0x7f
847 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
849 if (irq == 0) /* 0 --> no irq is pending */
852 return irq_linear_revmap(primary_ipic->irqhost, irq);
855 static struct sysdev_class ipic_sysclass = {
856 set_kset_name("ipic"),
859 static struct sys_device device_ipic = {
861 .cls = &ipic_sysclass,
864 static int __init init_ipic_sysfs(void)
868 if (!primary_ipic->regs)
870 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
872 rc = sysdev_class_register(&ipic_sysclass);
874 printk(KERN_ERR "Failed registering ipic sys class\n");
877 rc = sysdev_register(&device_ipic);
879 printk(KERN_ERR "Failed registering ipic sys device\n");
885 subsys_initcall(init_ipic_sysfs);