err.no Git - linux-2.6/blob - arch/powerpc/platforms/powermac/pic.c

   1 /*
   2  *  Support for the interrupt controllers found on Power Macintosh,
   3  *  currently Apple's "Grand Central" interrupt controller in all
   4  *  it's incarnations. OpenPIC support used on newer machines is
   5  *  in a separate file
   6  *
   7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
   8  *
   9  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  *
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/stddef.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/signal.h>
  23 #include <linux/pci.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/adb.h>
  27 #include <linux/pmu.h>
  28 #include <linux/module.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/smp.h>
  33 #include <asm/prom.h>
  34 #include <asm/pci-bridge.h>
  35 #include <asm/time.h>
  36 #include <asm/xmon.h>
  37 #include <asm/pmac_feature.h>
  38 #include <asm/mpic.h>
  39
  40 #include "pmac.h"
  41
  42 /*
  43  * XXX this should be in xmon.h, but putting it there means xmon.h
  44  * has to include <linux/interrupt.h> (to get irqreturn_t), which
  45  * causes all sorts of problems.  -- paulus
  46  */
  47 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
  48
  49 #ifdef CONFIG_PPC32
  50 struct pmac_irq_hw {
  51         unsigned int    event;
  52         unsigned int    enable;
  53         unsigned int    ack;
  54         unsigned int    level;
  55 };
  56
  57 /* Default addresses */
  58 static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
  59         (struct pmac_irq_hw *) 0xf3000020,
  60         (struct pmac_irq_hw *) 0xf3000010,
  61         (struct pmac_irq_hw *) 0xf4000020,
  62         (struct pmac_irq_hw *) 0xf4000010,
  63 };
  64
  65 #define GC_LEVEL_MASK           0x3ff00000
  66 #define OHARE_LEVEL_MASK        0x1ff00000
  67 #define HEATHROW_LEVEL_MASK     0x1ff00000
  68
  69 static int max_irqs;
  70 static int max_real_irqs;
  71 static u32 level_mask[4];
  72
  73 static DEFINE_SPINLOCK(pmac_pic_lock);
  74
  75 /* XXX here for now, should move to arch/powerpc/kernel/irq.c */
  76 int ppc_do_canonicalize_irqs;
  77 EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
  78
  79 #define GATWICK_IRQ_POOL_SIZE        10
  80 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
  81
  82 /*
  83  * Mark an irq as "lost".  This is only used on the pmac
  84  * since it can lose interrupts (see pmac_set_irq_mask).
  85  * -- Cort
  86  */
  87 void
  88 __set_lost(unsigned long irq_nr, int nokick)
  89 {
  90         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  91                 atomic_inc(&ppc_n_lost_interrupts);
  92                 if (!nokick)
  93                         set_dec(1);
  94         }
  95 }
  96
  97 static void
  98 pmac_mask_and_ack_irq(unsigned int irq_nr)
  99 {
 100         unsigned long bit = 1UL << (irq_nr & 0x1f);
 101         int i = irq_nr >> 5;
 102         unsigned long flags;
 103
 104         if ((unsigned)irq_nr >= max_irqs)
 105                 return;
 106
 107         clear_bit(irq_nr, ppc_cached_irq_mask);
 108         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
 109                 atomic_dec(&ppc_n_lost_interrupts);
 110         spin_lock_irqsave(&pmac_pic_lock, flags);
 111         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 112         out_le32(&pmac_irq_hw[i]->ack, bit);
 113         do {
 114                 /* make sure ack gets to controller before we enable
 115                    interrupts */
 116                 mb();
 117         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 118                 != (ppc_cached_irq_mask[i] & bit));
 119         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 120 }
 121
 122 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
 123 {
 124         unsigned long bit = 1UL << (irq_nr & 0x1f);
 125         int i = irq_nr >> 5;
 126         unsigned long flags;
 127
 128         if ((unsigned)irq_nr >= max_irqs)
 129                 return;
 130
 131         spin_lock_irqsave(&pmac_pic_lock, flags);
 132         /* enable unmasked interrupts */
 133         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 134
 135         do {
 136                 /* make sure mask gets to controller before we
 137                    return to user */
 138                 mb();
 139         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 140                 != (ppc_cached_irq_mask[i] & bit));
 141
 142         /*
 143          * Unfortunately, setting the bit in the enable register
 144          * when the device interrupt is already on *doesn't* set
 145          * the bit in the flag register or request another interrupt.
 146          */
 147         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 148                 __set_lost((ulong)irq_nr, nokicklost);
 149         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 150 }
 151
 152 /* When an irq gets requested for the first client, if it's an
 153  * edge interrupt, we clear any previous one on the controller
 154  */
 155 static unsigned int pmac_startup_irq(unsigned int irq_nr)
 156 {
 157         unsigned long bit = 1UL << (irq_nr & 0x1f);
 158         int i = irq_nr >> 5;
 159
 160         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 161                 out_le32(&pmac_irq_hw[i]->ack, bit);
 162         set_bit(irq_nr, ppc_cached_irq_mask);
 163         pmac_set_irq_mask(irq_nr, 0);
 164
 165         return 0;
 166 }
 167
 168 static void pmac_mask_irq(unsigned int irq_nr)
 169 {
 170         clear_bit(irq_nr, ppc_cached_irq_mask);
 171         pmac_set_irq_mask(irq_nr, 0);
 172         mb();
 173 }
 174
 175 static void pmac_unmask_irq(unsigned int irq_nr)
 176 {
 177         set_bit(irq_nr, ppc_cached_irq_mask);
 178         pmac_set_irq_mask(irq_nr, 0);
 179 }
 180
 181 static void pmac_end_irq(unsigned int irq_nr)
 182 {
 183         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 184             && irq_desc[irq_nr].action) {
 185                 set_bit(irq_nr, ppc_cached_irq_mask);
 186                 pmac_set_irq_mask(irq_nr, 1);
 187         }
 188 }
 189
 190
 191 struct hw_interrupt_type pmac_pic = {
 192         .typename       = " PMAC-PIC ",
 193         .startup        = pmac_startup_irq,
 194         .enable         = pmac_unmask_irq,
 195         .disable        = pmac_mask_irq,
 196         .ack            = pmac_mask_and_ack_irq,
 197         .end            = pmac_end_irq,
 198 };
 199
 200 struct hw_interrupt_type gatwick_pic = {
 201         .typename       = " GATWICK  ",
 202         .startup        = pmac_startup_irq,
 203         .enable         = pmac_unmask_irq,
 204         .disable        = pmac_mask_irq,
 205         .ack            = pmac_mask_and_ack_irq,
 206         .end            = pmac_end_irq,
 207 };
 208
 209 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
 210 {
 211         int irq, bits;
 212
 213         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 214                 int i = irq >> 5;
 215                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 216                 /* We must read level interrupts from the level register */
 217                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 218                 bits &= ppc_cached_irq_mask[i];
 219                 if (bits == 0)
 220                         continue;
 221                 irq += __ilog2(bits);
 222                 __do_IRQ(irq, regs);
 223                 return IRQ_HANDLED;
 224         }
 225         printk("gatwick irq not from gatwick pic\n");
 226         return IRQ_NONE;
 227 }
 228
 229 int
 230 pmac_get_irq(struct pt_regs *regs)
 231 {
 232         int irq;
 233         unsigned long bits = 0;
 234
 235 #ifdef CONFIG_SMP
 236         void psurge_smp_message_recv(struct pt_regs *);
 237
 238         /* IPI's are a hack on the powersurge -- Cort */
 239         if ( smp_processor_id() != 0 ) {
 240                 psurge_smp_message_recv(regs);
 241                 return -2;      /* ignore, already handled */
 242         }
 243 #endif /* CONFIG_SMP */
 244         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 245                 int i = irq >> 5;
 246                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 247                 /* We must read level interrupts from the level register */
 248                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 249                 bits &= ppc_cached_irq_mask[i];
 250                 if (bits == 0)
 251                         continue;
 252                 irq += __ilog2(bits);
 253                 break;
 254         }
 255
 256         return irq;
 257 }
 258
 259 /* This routine will fix some missing interrupt values in the device tree
 260  * on the gatwick mac-io controller used by some PowerBooks
 261  */
 262 static void __init
 263 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
 264 {
 265         struct device_node *node;
 266         int count;
 267
 268         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
 269         node = gw->child;
 270         count = 0;
 271         while(node)
 272         {
 273                 /* Fix SCC */
 274                 if (strcasecmp(node->name, "escc") == 0)
 275                         if (node->child) {
 276                                 if (node->child->n_intrs < 3) {
 277                                         node->child->intrs = &gatwick_int_pool[count];
 278                                         count += 3;
 279                                 }
 280                                 node->child->n_intrs = 3;
 281                                 node->child->intrs[0].line = 15+irq_base;
 282                                 node->child->intrs[1].line =  4+irq_base;
 283                                 node->child->intrs[2].line =  5+irq_base;
 284                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
 285                                         node->child->intrs[0].line,
 286                                         node->child->intrs[1].line,
 287                                         node->child->intrs[2].line);
 288                         }
 289                 /* Fix media-bay & left SWIM */
 290                 if (strcasecmp(node->name, "media-bay") == 0) {
 291                         struct device_node* ya_node;
 292
 293                         if (node->n_intrs == 0)
 294                                 node->intrs = &gatwick_int_pool[count++];
 295                         node->n_intrs = 1;
 296                         node->intrs[0].line = 29+irq_base;
 297                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
 298                                         node->intrs[0].line);
 299
 300                         ya_node = node->child;
 301                         while(ya_node)
 302                         {
 303                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
 304                                         if (ya_node->n_intrs < 2) {
 305                                                 ya_node->intrs = &gatwick_int_pool[count];
 306                                                 count += 2;
 307                                         }
 308                                         ya_node->n_intrs = 2;
 309                                         ya_node->intrs[0].line = 19+irq_base;
 310                                         ya_node->intrs[1].line =  1+irq_base;
 311                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
 312                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 313                                 }
 314                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
 315                                         if (ya_node->n_intrs < 2) {
 316                                                 ya_node->intrs = &gatwick_int_pool[count];
 317                                                 count += 2;
 318                                         }
 319                                         ya_node->n_intrs = 2;
 320                                         ya_node->intrs[0].line = 14+irq_base;
 321                                         ya_node->intrs[1].line =  3+irq_base;
 322                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
 323                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 324                                 }
 325                                 ya_node = ya_node->sibling;
 326                         }
 327                 }
 328                 node = node->sibling;
 329         }
 330         if (count > 10) {
 331                 printk("WARNING !! Gatwick interrupt pool overflow\n");
 332                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
 333                 printk("              requested = %d\n", count);
 334         }
 335 }
 336
 337 /*
 338  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
 339  * card which includes an ohare chip that acts as a second interrupt
 340  * controller.  If we find this second ohare, set it up and fix the
 341  * interrupt value in the device tree for the ethernet chip.
 342  */
 343 static int __init enable_second_ohare(void)
 344 {
 345         unsigned char bus, devfn;
 346         unsigned short cmd;
 347         unsigned long addr;
 348         struct device_node *irqctrler = find_devices("pci106b,7");
 349         struct device_node *ether;
 350
 351         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
 352                 return -1;
 353         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
 354         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
 355         max_irqs = 64;
 356         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
 357                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
 358                 if (!hose)
 359                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
 360                 else {
 361                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
 362                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 363                     cmd &= ~PCI_COMMAND_IO;
 364                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
 365                 }
 366         }
 367
 368         /* Fix interrupt for the modem/ethernet combo controller. The number
 369            in the device tree (27) is bogus (correct for the ethernet-only
 370            board but not the combo ethernet/modem board).
 371            The real interrupt is 28 on the second controller -> 28+32 = 60.
 372         */
 373         ether = find_devices("pci1011,14");
 374         if (ether && ether->n_intrs > 0) {
 375                 ether->intrs[0].line = 60;
 376                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
 377                        ether->intrs[0].line);
 378         }
 379
 380         /* Return the interrupt number of the cascade */
 381         return irqctrler->intrs[0].line;
 382 }
 383
 384 #ifdef CONFIG_XMON
 385 static struct irqaction xmon_action = {
 386         .handler        = xmon_irq,
 387         .flags          = 0,
 388         .mask           = CPU_MASK_NONE,
 389         .name           = "NMI - XMON"
 390 };
 391 #endif
 392
 393 static struct irqaction gatwick_cascade_action = {
 394         .handler        = gatwick_action,
 395         .flags          = SA_INTERRUPT,
 396         .mask           = CPU_MASK_NONE,
 397         .name           = "cascade",
 398 };
 399 #endif /* CONFIG_PPC32 */
 400
 401 static int pmac_u3_cascade(struct pt_regs *regs, void *data)
 402 {
 403         return mpic_get_one_irq((struct mpic *)data, regs);
 404 }
 405
 406 void __init pmac_pic_init(void)
 407 {
 408         struct device_node *irqctrler  = NULL;
 409         struct device_node *irqctrler2 = NULL;
 410         struct device_node *np;
 411 #ifdef CONFIG_PPC32
 412         int i;
 413         unsigned long addr;
 414         int irq_cascade = -1;
 415 #endif
 416         struct mpic *mpic1, *mpic2;
 417
 418         /* We first try to detect Apple's new Core99 chipset, since mac-io
 419          * is quite different on those machines and contains an IBM MPIC2.
 420          */
 421         np = find_type_devices("open-pic");
 422         while (np) {
 423                 if (np->parent && !strcmp(np->parent->name, "u3"))
 424                         irqctrler2 = np;
 425                 else
 426                         irqctrler = np;
 427                 np = np->next;
 428         }
 429         if (irqctrler != NULL && irqctrler->n_addrs > 0) {
 430                 unsigned char senses[128];
 431
 432                 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
 433                        (unsigned int)irqctrler->addrs[0].address);
 434                 ppc_md.get_irq = mpic_get_irq;
 435                 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
 436
 437                 prom_get_irq_senses(senses, 0, 128);
 438                 mpic1 = mpic_alloc(irqctrler->addrs[0].address,
 439                                    MPIC_PRIMARY | MPIC_WANTS_RESET,
 440                                    0, 0, 128, 252, senses, 128, " OpenPIC  ");
 441                 BUG_ON(mpic1 == NULL);
 442                 mpic_init(mpic1);
 443
 444                 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
 445                     irqctrler2->n_addrs > 0) {
 446                         printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
 447                                (u32)irqctrler2->addrs[0].address,
 448                                irqctrler2->intrs[0].line);
 449
 450                         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
 451                         prom_get_irq_senses(senses, 128, 128 + 124);
 452
 453                         /* We don't need to set MPIC_BROKEN_U3 here since we don't have
 454                          * hypertransport interrupts routed to it
 455                          */
 456                         mpic2 = mpic_alloc(irqctrler2->addrs[0].address,
 457                                            MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
 458                                            0, 128, 124, 0, senses, 124,
 459                                            " U3-MPIC  ");
 460                         BUG_ON(mpic2 == NULL);
 461                         mpic_init(mpic2);
 462                         mpic_setup_cascade(irqctrler2->intrs[0].line,
 463                                            pmac_u3_cascade, mpic2);
 464                 }
 465 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
 466                 {
 467                         struct device_node* pswitch;
 468                         int nmi_irq;
 469
 470                         pswitch = find_devices("programmer-switch");
 471                         if (pswitch && pswitch->n_intrs) {
 472                                 nmi_irq = pswitch->intrs[0].line;
 473                                 mpic_irq_set_priority(nmi_irq, 9);
 474                                 setup_irq(nmi_irq, &xmon_action);
 475                         }
 476                 }
 477 #endif  /* CONFIG_XMON */
 478                 return;
 479         }
 480         irqctrler = NULL;
 481
 482 #ifdef CONFIG_PPC32
 483         /* Get the level/edge settings, assume if it's not
 484          * a Grand Central nor an OHare, then it's an Heathrow
 485          * (or Paddington).
 486          */
 487         if (find_devices("gc"))
 488                 level_mask[0] = GC_LEVEL_MASK;
 489         else if (find_devices("ohare")) {
 490                 level_mask[0] = OHARE_LEVEL_MASK;
 491                 /* We might have a second cascaded ohare */
 492                 level_mask[1] = OHARE_LEVEL_MASK;
 493         } else {
 494                 level_mask[0] = HEATHROW_LEVEL_MASK;
 495                 level_mask[1] = 0;
 496                 /* We might have a second cascaded heathrow */
 497                 level_mask[2] = HEATHROW_LEVEL_MASK;
 498                 level_mask[3] = 0;
 499         }
 500
 501         /*
 502          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
 503          * 1998 G3 Series PowerBooks have 128,
 504          * other powermacs have 32.
 505          * The combo ethernet/modem card for the Powerstar powerbooks
 506          * (2400/3400/3500, ohare based) has a second ohare chip
 507          * effectively making a total of 64.
 508          */
 509         max_irqs = max_real_irqs = 32;
 510         irqctrler = find_devices("mac-io");
 511         if (irqctrler)
 512         {
 513                 max_real_irqs = 64;
 514                 if (irqctrler->next)
 515                         max_irqs = 128;
 516                 else
 517                         max_irqs = 64;
 518         }
 519         for ( i = 0; i < max_real_irqs ; i++ )
 520                 irq_desc[i].handler = &pmac_pic;
 521
 522         /* get addresses of first controller */
 523         if (irqctrler) {
 524                 if  (irqctrler->n_addrs > 0) {
 525                         addr = (unsigned long)
 526                                 ioremap(irqctrler->addrs[0].address, 0x40);
 527                         for (i = 0; i < 2; ++i)
 528                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 529                                         (addr + (2 - i) * 0x10);
 530                 }
 531
 532                 /* get addresses of second controller */
 533                 irqctrler = irqctrler->next;
 534                 if (irqctrler && irqctrler->n_addrs > 0) {
 535                         addr = (unsigned long)
 536                                 ioremap(irqctrler->addrs[0].address, 0x40);
 537                         for (i = 2; i < 4; ++i)
 538                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 539                                         (addr + (4 - i) * 0x10);
 540                         irq_cascade = irqctrler->intrs[0].line;
 541                         if (device_is_compatible(irqctrler, "gatwick"))
 542                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
 543                 }
 544         } else {
 545                 /* older powermacs have a GC (grand central) or ohare at
 546                    f3000000, with interrupt control registers at f3000020. */
 547                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
 548                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
 549         }
 550
 551         /* PowerBooks 3400 and 3500 can have a second controller in a second
 552            ohare chip, on the combo ethernet/modem card */
 553         if (machine_is_compatible("AAPL,3400/2400")
 554              || machine_is_compatible("AAPL,3500"))
 555                 irq_cascade = enable_second_ohare();
 556
 557         /* disable all interrupts in all controllers */
 558         for (i = 0; i * 32 < max_irqs; ++i)
 559                 out_le32(&pmac_irq_hw[i]->enable, 0);
 560         /* mark level interrupts */
 561         for (i = 0; i < max_irqs; i++)
 562                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
 563                         irq_desc[i].status = IRQ_LEVEL;
 564
 565         /* get interrupt line of secondary interrupt controller */
 566         if (irq_cascade >= 0) {
 567                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
 568                         (int)irq_cascade);
 569                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
 570                         irq_desc[i].handler = &gatwick_pic;
 571                 setup_irq(irq_cascade, &gatwick_cascade_action);
 572         }
 573         printk("System has %d possible interrupts\n", max_irqs);
 574         if (max_irqs != max_real_irqs)
 575                 printk(KERN_DEBUG "%d interrupts on main controller\n",
 576                         max_real_irqs);
 577
 578 #ifdef CONFIG_XMON
 579         setup_irq(20, &xmon_action);
 580 #endif  /* CONFIG_XMON */
 581 #endif  /* CONFIG_PPC32 */
 582 }
 583
 584 #ifdef CONFIG_PM
 585 /*
 586  * These procedures are used in implementing sleep on the powerbooks.
 587  * sleep_save_intrs() saves the states of all interrupt enables
 588  * and disables all interrupts except for the nominated one.
 589  * sleep_restore_intrs() restores the states of all interrupt enables.
 590  */
 591 unsigned long sleep_save_mask[2];
 592
 593 /* This used to be passed by the PMU driver but that link got
 594  * broken with the new driver model. We use this tweak for now...
 595  */
 596 static int pmacpic_find_viaint(void)
 597 {
 598         int viaint = -1;
 599
 600 #ifdef CONFIG_ADB_PMU
 601         struct device_node *np;
 602
 603         if (pmu_get_model() != PMU_OHARE_BASED)
 604                 goto not_found;
 605         np = of_find_node_by_name(NULL, "via-pmu");
 606         if (np == NULL)
 607                 goto not_found;
 608         viaint = np->intrs[0].line;
 609 #endif /* CONFIG_ADB_PMU */
 610
 611 not_found:
 612         return viaint;
 613 }
 614
 615 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
 616 {
 617         int viaint = pmacpic_find_viaint();
 618
 619         sleep_save_mask[0] = ppc_cached_irq_mask[0];
 620         sleep_save_mask[1] = ppc_cached_irq_mask[1];
 621         ppc_cached_irq_mask[0] = 0;
 622         ppc_cached_irq_mask[1] = 0;
 623         if (viaint > 0)
 624                 set_bit(viaint, ppc_cached_irq_mask);
 625         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 626         if (max_real_irqs > 32)
 627                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 628         (void)in_le32(&pmac_irq_hw[0]->event);
 629         /* make sure mask gets to controller before we return to caller */
 630         mb();
 631         (void)in_le32(&pmac_irq_hw[0]->enable);
 632
 633         return 0;
 634 }
 635
 636 static int pmacpic_resume(struct sys_device *sysdev)
 637 {
 638         int i;
 639
 640         out_le32(&pmac_irq_hw[0]->enable, 0);
 641         if (max_real_irqs > 32)
 642                 out_le32(&pmac_irq_hw[1]->enable, 0);
 643         mb();
 644         for (i = 0; i < max_real_irqs; ++i)
 645                 if (test_bit(i, sleep_save_mask))
 646                         pmac_unmask_irq(i);
 647
 648         return 0;
 649 }
 650
 651 #endif /* CONFIG_PM */
 652
 653 static struct sysdev_class pmacpic_sysclass = {
 654         set_kset_name("pmac_pic"),
 655 };
 656
 657 static struct sys_device device_pmacpic = {
 658         .id             = 0,
 659         .cls            = &pmacpic_sysclass,
 660 };
 661
 662 static struct sysdev_driver driver_pmacpic = {
 663 #ifdef CONFIG_PM
 664         .suspend        = &pmacpic_suspend,
 665         .resume         = &pmacpic_resume,
 666 #endif /* CONFIG_PM */
 667 };
 668
 669 static int __init init_pmacpic_sysfs(void)
 670 {
 671 #ifdef CONFIG_PPC32
 672         if (max_irqs == 0)
 673                 return -ENODEV;
 674 #endif
 675         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
 676         sysdev_class_register(&pmacpic_sysclass);
 677         sysdev_register(&device_pmacpic);
 678         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
 679         return 0;
 680 }
 681
 682 subsys_initcall(init_pmacpic_sysfs);
 683