err.no Git - linux-2.6/blob - arch/powerpc/platforms/powermac/pic.c

   1 /*
   2  *  Support for the interrupt controllers found on Power Macintosh,
   3  *  currently Apple's "Grand Central" interrupt controller in all
   4  *  it's incarnations. OpenPIC support used on newer machines is
   5  *  in a separate file
   6  *
   7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
   8  *
   9  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  *
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/stddef.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/signal.h>
  23 #include <linux/pci.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/adb.h>
  27 #include <linux/pmu.h>
  28 #include <linux/module.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/smp.h>
  33 #include <asm/prom.h>
  34 #include <asm/pci-bridge.h>
  35 #include <asm/time.h>
  36 #include <asm/pmac_feature.h>
  37 #include <asm/mpic.h>
  38
  39 #include "pmac.h"
  40
  41 /*
  42  * XXX this should be in xmon.h, but putting it there means xmon.h
  43  * has to include <linux/interrupt.h> (to get irqreturn_t), which
  44  * causes all sorts of problems.  -- paulus
  45  */
  46 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
  47
  48 #ifdef CONFIG_PPC32
  49 struct pmac_irq_hw {
  50         unsigned int    event;
  51         unsigned int    enable;
  52         unsigned int    ack;
  53         unsigned int    level;
  54 };
  55
  56 /* Default addresses */
  57 static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
  58         (struct pmac_irq_hw *) 0xf3000020,
  59         (struct pmac_irq_hw *) 0xf3000010,
  60         (struct pmac_irq_hw *) 0xf4000020,
  61         (struct pmac_irq_hw *) 0xf4000010,
  62 };
  63
  64 #define GC_LEVEL_MASK           0x3ff00000
  65 #define OHARE_LEVEL_MASK        0x1ff00000
  66 #define HEATHROW_LEVEL_MASK     0x1ff00000
  67
  68 static int max_irqs;
  69 static int max_real_irqs;
  70 static u32 level_mask[4];
  71
  72 static DEFINE_SPINLOCK(pmac_pic_lock);
  73
  74 /* XXX here for now, should move to arch/powerpc/kernel/irq.c */
  75 int ppc_do_canonicalize_irqs;
  76 EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
  77
  78 #define GATWICK_IRQ_POOL_SIZE        10
  79 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
  80
  81 /*
  82  * Mark an irq as "lost".  This is only used on the pmac
  83  * since it can lose interrupts (see pmac_set_irq_mask).
  84  * -- Cort
  85  */
  86 void
  87 __set_lost(unsigned long irq_nr, int nokick)
  88 {
  89         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  90                 atomic_inc(&ppc_n_lost_interrupts);
  91                 if (!nokick)
  92                         set_dec(1);
  93         }
  94 }
  95
  96 static void
  97 pmac_mask_and_ack_irq(unsigned int irq_nr)
  98 {
  99         unsigned long bit = 1UL << (irq_nr & 0x1f);
 100         int i = irq_nr >> 5;
 101         unsigned long flags;
 102
 103         if ((unsigned)irq_nr >= max_irqs)
 104                 return;
 105
 106         clear_bit(irq_nr, ppc_cached_irq_mask);
 107         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
 108                 atomic_dec(&ppc_n_lost_interrupts);
 109         spin_lock_irqsave(&pmac_pic_lock, flags);
 110         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 111         out_le32(&pmac_irq_hw[i]->ack, bit);
 112         do {
 113                 /* make sure ack gets to controller before we enable
 114                    interrupts */
 115                 mb();
 116         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 117                 != (ppc_cached_irq_mask[i] & bit));
 118         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 119 }
 120
 121 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
 122 {
 123         unsigned long bit = 1UL << (irq_nr & 0x1f);
 124         int i = irq_nr >> 5;
 125         unsigned long flags;
 126
 127         if ((unsigned)irq_nr >= max_irqs)
 128                 return;
 129
 130         spin_lock_irqsave(&pmac_pic_lock, flags);
 131         /* enable unmasked interrupts */
 132         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 133
 134         do {
 135                 /* make sure mask gets to controller before we
 136                    return to user */
 137                 mb();
 138         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 139                 != (ppc_cached_irq_mask[i] & bit));
 140
 141         /*
 142          * Unfortunately, setting the bit in the enable register
 143          * when the device interrupt is already on *doesn't* set
 144          * the bit in the flag register or request another interrupt.
 145          */
 146         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 147                 __set_lost((ulong)irq_nr, nokicklost);
 148         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 149 }
 150
 151 /* When an irq gets requested for the first client, if it's an
 152  * edge interrupt, we clear any previous one on the controller
 153  */
 154 static unsigned int pmac_startup_irq(unsigned int irq_nr)
 155 {
 156         unsigned long bit = 1UL << (irq_nr & 0x1f);
 157         int i = irq_nr >> 5;
 158
 159         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 160                 out_le32(&pmac_irq_hw[i]->ack, bit);
 161         set_bit(irq_nr, ppc_cached_irq_mask);
 162         pmac_set_irq_mask(irq_nr, 0);
 163
 164         return 0;
 165 }
 166
 167 static void pmac_mask_irq(unsigned int irq_nr)
 168 {
 169         clear_bit(irq_nr, ppc_cached_irq_mask);
 170         pmac_set_irq_mask(irq_nr, 0);
 171         mb();
 172 }
 173
 174 static void pmac_unmask_irq(unsigned int irq_nr)
 175 {
 176         set_bit(irq_nr, ppc_cached_irq_mask);
 177         pmac_set_irq_mask(irq_nr, 0);
 178 }
 179
 180 static void pmac_end_irq(unsigned int irq_nr)
 181 {
 182         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 183             && irq_desc[irq_nr].action) {
 184                 set_bit(irq_nr, ppc_cached_irq_mask);
 185                 pmac_set_irq_mask(irq_nr, 1);
 186         }
 187 }
 188
 189
 190 struct hw_interrupt_type pmac_pic = {
 191         .typename       = " PMAC-PIC ",
 192         .startup        = pmac_startup_irq,
 193         .enable         = pmac_unmask_irq,
 194         .disable        = pmac_mask_irq,
 195         .ack            = pmac_mask_and_ack_irq,
 196         .end            = pmac_end_irq,
 197 };
 198
 199 struct hw_interrupt_type gatwick_pic = {
 200         .typename       = " GATWICK  ",
 201         .startup        = pmac_startup_irq,
 202         .enable         = pmac_unmask_irq,
 203         .disable        = pmac_mask_irq,
 204         .ack            = pmac_mask_and_ack_irq,
 205         .end            = pmac_end_irq,
 206 };
 207
 208 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
 209 {
 210         int irq, bits;
 211
 212         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 213                 int i = irq >> 5;
 214                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 215                 /* We must read level interrupts from the level register */
 216                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 217                 bits &= ppc_cached_irq_mask[i];
 218                 if (bits == 0)
 219                         continue;
 220                 irq += __ilog2(bits);
 221                 __do_IRQ(irq, regs);
 222                 return IRQ_HANDLED;
 223         }
 224         printk("gatwick irq not from gatwick pic\n");
 225         return IRQ_NONE;
 226 }
 227
 228 int
 229 pmac_get_irq(struct pt_regs *regs)
 230 {
 231         int irq;
 232         unsigned long bits = 0;
 233
 234 #ifdef CONFIG_SMP
 235         void psurge_smp_message_recv(struct pt_regs *);
 236
 237         /* IPI's are a hack on the powersurge -- Cort */
 238         if ( smp_processor_id() != 0 ) {
 239                 psurge_smp_message_recv(regs);
 240                 return -2;      /* ignore, already handled */
 241         }
 242 #endif /* CONFIG_SMP */
 243         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 244                 int i = irq >> 5;
 245                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 246                 /* We must read level interrupts from the level register */
 247                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 248                 bits &= ppc_cached_irq_mask[i];
 249                 if (bits == 0)
 250                         continue;
 251                 irq += __ilog2(bits);
 252                 break;
 253         }
 254
 255         return irq;
 256 }
 257
 258 /* This routine will fix some missing interrupt values in the device tree
 259  * on the gatwick mac-io controller used by some PowerBooks
 260  */
 261 static void __init
 262 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
 263 {
 264         struct device_node *node;
 265         int count;
 266
 267         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
 268         node = gw->child;
 269         count = 0;
 270         while(node)
 271         {
 272                 /* Fix SCC */
 273                 if (strcasecmp(node->name, "escc") == 0)
 274                         if (node->child) {
 275                                 if (node->child->n_intrs < 3) {
 276                                         node->child->intrs = &gatwick_int_pool[count];
 277                                         count += 3;
 278                                 }
 279                                 node->child->n_intrs = 3;
 280                                 node->child->intrs[0].line = 15+irq_base;
 281                                 node->child->intrs[1].line =  4+irq_base;
 282                                 node->child->intrs[2].line =  5+irq_base;
 283                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
 284                                         node->child->intrs[0].line,
 285                                         node->child->intrs[1].line,
 286                                         node->child->intrs[2].line);
 287                         }
 288                 /* Fix media-bay & left SWIM */
 289                 if (strcasecmp(node->name, "media-bay") == 0) {
 290                         struct device_node* ya_node;
 291
 292                         if (node->n_intrs == 0)
 293                                 node->intrs = &gatwick_int_pool[count++];
 294                         node->n_intrs = 1;
 295                         node->intrs[0].line = 29+irq_base;
 296                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
 297                                         node->intrs[0].line);
 298
 299                         ya_node = node->child;
 300                         while(ya_node)
 301                         {
 302                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
 303                                         if (ya_node->n_intrs < 2) {
 304                                                 ya_node->intrs = &gatwick_int_pool[count];
 305                                                 count += 2;
 306                                         }
 307                                         ya_node->n_intrs = 2;
 308                                         ya_node->intrs[0].line = 19+irq_base;
 309                                         ya_node->intrs[1].line =  1+irq_base;
 310                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
 311                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 312                                 }
 313                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
 314                                         if (ya_node->n_intrs < 2) {
 315                                                 ya_node->intrs = &gatwick_int_pool[count];
 316                                                 count += 2;
 317                                         }
 318                                         ya_node->n_intrs = 2;
 319                                         ya_node->intrs[0].line = 14+irq_base;
 320                                         ya_node->intrs[1].line =  3+irq_base;
 321                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
 322                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 323                                 }
 324                                 ya_node = ya_node->sibling;
 325                         }
 326                 }
 327                 node = node->sibling;
 328         }
 329         if (count > 10) {
 330                 printk("WARNING !! Gatwick interrupt pool overflow\n");
 331                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
 332                 printk("              requested = %d\n", count);
 333         }
 334 }
 335
 336 /*
 337  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
 338  * card which includes an ohare chip that acts as a second interrupt
 339  * controller.  If we find this second ohare, set it up and fix the
 340  * interrupt value in the device tree for the ethernet chip.
 341  */
 342 static int __init enable_second_ohare(void)
 343 {
 344         unsigned char bus, devfn;
 345         unsigned short cmd;
 346         unsigned long addr;
 347         struct device_node *irqctrler = find_devices("pci106b,7");
 348         struct device_node *ether;
 349
 350         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
 351                 return -1;
 352         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
 353         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
 354         max_irqs = 64;
 355         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
 356                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
 357                 if (!hose)
 358                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
 359                 else {
 360                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
 361                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 362                     cmd &= ~PCI_COMMAND_IO;
 363                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
 364                 }
 365         }
 366
 367         /* Fix interrupt for the modem/ethernet combo controller. The number
 368            in the device tree (27) is bogus (correct for the ethernet-only
 369            board but not the combo ethernet/modem board).
 370            The real interrupt is 28 on the second controller -> 28+32 = 60.
 371         */
 372         ether = find_devices("pci1011,14");
 373         if (ether && ether->n_intrs > 0) {
 374                 ether->intrs[0].line = 60;
 375                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
 376                        ether->intrs[0].line);
 377         }
 378
 379         /* Return the interrupt number of the cascade */
 380         return irqctrler->intrs[0].line;
 381 }
 382
 383 #ifdef CONFIG_XMON
 384 static struct irqaction xmon_action = {
 385         .handler        = xmon_irq,
 386         .flags          = 0,
 387         .mask           = CPU_MASK_NONE,
 388         .name           = "NMI - XMON"
 389 };
 390 #endif
 391
 392 static struct irqaction gatwick_cascade_action = {
 393         .handler        = gatwick_action,
 394         .flags          = SA_INTERRUPT,
 395         .mask           = CPU_MASK_NONE,
 396         .name           = "cascade",
 397 };
 398 #endif /* CONFIG_PPC32 */
 399
 400 static int pmac_u3_cascade(struct pt_regs *regs, void *data)
 401 {
 402         return mpic_get_one_irq((struct mpic *)data, regs);
 403 }
 404
 405 void __init pmac_pic_init(void)
 406 {
 407         struct device_node *irqctrler  = NULL;
 408         struct device_node *irqctrler2 = NULL;
 409         struct device_node *np;
 410 #ifdef CONFIG_PPC32
 411         int i;
 412         unsigned long addr;
 413         int irq_cascade = -1;
 414 #endif
 415         struct mpic *mpic1, *mpic2;
 416
 417         /* We first try to detect Apple's new Core99 chipset, since mac-io
 418          * is quite different on those machines and contains an IBM MPIC2.
 419          */
 420         np = find_type_devices("open-pic");
 421         while (np) {
 422                 if (np->parent && !strcmp(np->parent->name, "u3"))
 423                         irqctrler2 = np;
 424                 else
 425                         irqctrler = np;
 426                 np = np->next;
 427         }
 428         if (irqctrler != NULL && irqctrler->n_addrs > 0) {
 429                 unsigned char senses[128];
 430
 431                 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
 432                        (unsigned int)irqctrler->addrs[0].address);
 433                 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
 434
 435                 prom_get_irq_senses(senses, 0, 128);
 436                 mpic1 = mpic_alloc(irqctrler->addrs[0].address,
 437                                    MPIC_PRIMARY | MPIC_WANTS_RESET,
 438                                    0, 0, 128, 252, senses, 128, " OpenPIC  ");
 439                 BUG_ON(mpic1 == NULL);
 440                 mpic_init(mpic1);
 441
 442                 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
 443                     irqctrler2->n_addrs > 0) {
 444                         printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
 445                                (u32)irqctrler2->addrs[0].address,
 446                                irqctrler2->intrs[0].line);
 447
 448                         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
 449                         prom_get_irq_senses(senses, 128, 128 + 124);
 450
 451                         /* We don't need to set MPIC_BROKEN_U3 here since we don't have
 452                          * hypertransport interrupts routed to it
 453                          */
 454                         mpic2 = mpic_alloc(irqctrler2->addrs[0].address,
 455                                            MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
 456                                            0, 128, 124, 0, senses, 124,
 457                                            " U3-MPIC  ");
 458                         BUG_ON(mpic2 == NULL);
 459                         mpic_init(mpic2);
 460                         mpic_setup_cascade(irqctrler2->intrs[0].line,
 461                                            pmac_u3_cascade, mpic2);
 462                 }
 463 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
 464                 {
 465                         struct device_node* pswitch;
 466                         int nmi_irq;
 467
 468                         pswitch = find_devices("programmer-switch");
 469                         if (pswitch && pswitch->n_intrs) {
 470                                 nmi_irq = pswitch->intrs[0].line;
 471                                 mpic_irq_set_priority(nmi_irq, 9);
 472                                 setup_irq(nmi_irq, &xmon_action);
 473                         }
 474                 }
 475 #endif  /* CONFIG_XMON */
 476                 return;
 477         }
 478         irqctrler = NULL;
 479
 480 #ifdef CONFIG_PPC32
 481         /* Get the level/edge settings, assume if it's not
 482          * a Grand Central nor an OHare, then it's an Heathrow
 483          * (or Paddington).
 484          */
 485         ppc_md.get_irq = pmac_get_irq;
 486         if (find_devices("gc"))
 487                 level_mask[0] = GC_LEVEL_MASK;
 488         else if (find_devices("ohare")) {
 489                 level_mask[0] = OHARE_LEVEL_MASK;
 490                 /* We might have a second cascaded ohare */
 491                 level_mask[1] = OHARE_LEVEL_MASK;
 492         } else {
 493                 level_mask[0] = HEATHROW_LEVEL_MASK;
 494                 level_mask[1] = 0;
 495                 /* We might have a second cascaded heathrow */
 496                 level_mask[2] = HEATHROW_LEVEL_MASK;
 497                 level_mask[3] = 0;
 498         }
 499
 500         /*
 501          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
 502          * 1998 G3 Series PowerBooks have 128,
 503          * other powermacs have 32.
 504          * The combo ethernet/modem card for the Powerstar powerbooks
 505          * (2400/3400/3500, ohare based) has a second ohare chip
 506          * effectively making a total of 64.
 507          */
 508         max_irqs = max_real_irqs = 32;
 509         irqctrler = find_devices("mac-io");
 510         if (irqctrler)
 511         {
 512                 max_real_irqs = 64;
 513                 if (irqctrler->next)
 514                         max_irqs = 128;
 515                 else
 516                         max_irqs = 64;
 517         }
 518         for ( i = 0; i < max_real_irqs ; i++ )
 519                 irq_desc[i].handler = &pmac_pic;
 520
 521         /* get addresses of first controller */
 522         if (irqctrler) {
 523                 if  (irqctrler->n_addrs > 0) {
 524                         addr = (unsigned long)
 525                                 ioremap(irqctrler->addrs[0].address, 0x40);
 526                         for (i = 0; i < 2; ++i)
 527                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 528                                         (addr + (2 - i) * 0x10);
 529                 }
 530
 531                 /* get addresses of second controller */
 532                 irqctrler = irqctrler->next;
 533                 if (irqctrler && irqctrler->n_addrs > 0) {
 534                         addr = (unsigned long)
 535                                 ioremap(irqctrler->addrs[0].address, 0x40);
 536                         for (i = 2; i < 4; ++i)
 537                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 538                                         (addr + (4 - i) * 0x10);
 539                         irq_cascade = irqctrler->intrs[0].line;
 540                         if (device_is_compatible(irqctrler, "gatwick"))
 541                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
 542                 }
 543         } else {
 544                 /* older powermacs have a GC (grand central) or ohare at
 545                    f3000000, with interrupt control registers at f3000020. */
 546                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
 547                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
 548         }
 549
 550         /* PowerBooks 3400 and 3500 can have a second controller in a second
 551            ohare chip, on the combo ethernet/modem card */
 552         if (machine_is_compatible("AAPL,3400/2400")
 553              || machine_is_compatible("AAPL,3500"))
 554                 irq_cascade = enable_second_ohare();
 555
 556         /* disable all interrupts in all controllers */
 557         for (i = 0; i * 32 < max_irqs; ++i)
 558                 out_le32(&pmac_irq_hw[i]->enable, 0);
 559         /* mark level interrupts */
 560         for (i = 0; i < max_irqs; i++)
 561                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
 562                         irq_desc[i].status = IRQ_LEVEL;
 563
 564         /* get interrupt line of secondary interrupt controller */
 565         if (irq_cascade >= 0) {
 566                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
 567                         (int)irq_cascade);
 568                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
 569                         irq_desc[i].handler = &gatwick_pic;
 570                 setup_irq(irq_cascade, &gatwick_cascade_action);
 571         }
 572         printk("System has %d possible interrupts\n", max_irqs);
 573         if (max_irqs != max_real_irqs)
 574                 printk(KERN_DEBUG "%d interrupts on main controller\n",
 575                         max_real_irqs);
 576
 577 #ifdef CONFIG_XMON
 578         setup_irq(20, &xmon_action);
 579 #endif  /* CONFIG_XMON */
 580 #endif  /* CONFIG_PPC32 */
 581 }
 582
 583 #ifdef CONFIG_PM
 584 /*
 585  * These procedures are used in implementing sleep on the powerbooks.
 586  * sleep_save_intrs() saves the states of all interrupt enables
 587  * and disables all interrupts except for the nominated one.
 588  * sleep_restore_intrs() restores the states of all interrupt enables.
 589  */
 590 unsigned long sleep_save_mask[2];
 591
 592 /* This used to be passed by the PMU driver but that link got
 593  * broken with the new driver model. We use this tweak for now...
 594  */
 595 static int pmacpic_find_viaint(void)
 596 {
 597         int viaint = -1;
 598
 599 #ifdef CONFIG_ADB_PMU
 600         struct device_node *np;
 601
 602         if (pmu_get_model() != PMU_OHARE_BASED)
 603                 goto not_found;
 604         np = of_find_node_by_name(NULL, "via-pmu");
 605         if (np == NULL)
 606                 goto not_found;
 607         viaint = np->intrs[0].line;
 608 #endif /* CONFIG_ADB_PMU */
 609
 610 not_found:
 611         return viaint;
 612 }
 613
 614 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
 615 {
 616         int viaint = pmacpic_find_viaint();
 617
 618         sleep_save_mask[0] = ppc_cached_irq_mask[0];
 619         sleep_save_mask[1] = ppc_cached_irq_mask[1];
 620         ppc_cached_irq_mask[0] = 0;
 621         ppc_cached_irq_mask[1] = 0;
 622         if (viaint > 0)
 623                 set_bit(viaint, ppc_cached_irq_mask);
 624         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 625         if (max_real_irqs > 32)
 626                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 627         (void)in_le32(&pmac_irq_hw[0]->event);
 628         /* make sure mask gets to controller before we return to caller */
 629         mb();
 630         (void)in_le32(&pmac_irq_hw[0]->enable);
 631
 632         return 0;
 633 }
 634
 635 static int pmacpic_resume(struct sys_device *sysdev)
 636 {
 637         int i;
 638
 639         out_le32(&pmac_irq_hw[0]->enable, 0);
 640         if (max_real_irqs > 32)
 641                 out_le32(&pmac_irq_hw[1]->enable, 0);
 642         mb();
 643         for (i = 0; i < max_real_irqs; ++i)
 644                 if (test_bit(i, sleep_save_mask))
 645                         pmac_unmask_irq(i);
 646
 647         return 0;
 648 }
 649
 650 #endif /* CONFIG_PM */
 651
 652 static struct sysdev_class pmacpic_sysclass = {
 653         set_kset_name("pmac_pic"),
 654 };
 655
 656 static struct sys_device device_pmacpic = {
 657         .id             = 0,
 658         .cls            = &pmacpic_sysclass,
 659 };
 660
 661 static struct sysdev_driver driver_pmacpic = {
 662 #ifdef CONFIG_PM
 663         .suspend        = &pmacpic_suspend,
 664         .resume         = &pmacpic_resume,
 665 #endif /* CONFIG_PM */
 666 };
 667
 668 static int __init init_pmacpic_sysfs(void)
 669 {
 670 #ifdef CONFIG_PPC32
 671         if (max_irqs == 0)
 672                 return -ENODEV;
 673 #endif
 674         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
 675         sysdev_class_register(&pmacpic_sysclass);
 676         sysdev_register(&device_pmacpic);
 677         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
 678         return 0;
 679 }
 680
 681 subsys_initcall(init_pmacpic_sysfs);
 682