2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/signal.h>
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/adb.h>
27 #include <linux/pmu.h>
28 #include <linux/module.h>
30 #include <asm/sections.h>
34 #include <asm/pci-bridge.h>
37 #include <asm/pmac_feature.h>
43 * XXX this should be in xmon.h, but putting it there means xmon.h
44 * has to include <linux/interrupt.h> (to get irqreturn_t), which
45 * causes all sorts of problems. -- paulus
47 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
57 /* Default addresses */
58 static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
59 (struct pmac_irq_hw *) 0xf3000020,
60 (struct pmac_irq_hw *) 0xf3000010,
61 (struct pmac_irq_hw *) 0xf4000020,
62 (struct pmac_irq_hw *) 0xf4000010,
65 #define GC_LEVEL_MASK 0x3ff00000
66 #define OHARE_LEVEL_MASK 0x1ff00000
67 #define HEATHROW_LEVEL_MASK 0x1ff00000
70 static int max_real_irqs;
71 static u32 level_mask[4];
73 static DEFINE_SPINLOCK(pmac_pic_lock);
75 /* XXX here for now, should move to arch/powerpc/kernel/irq.c */
76 int ppc_do_canonicalize_irqs;
77 EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
79 #define GATWICK_IRQ_POOL_SIZE 10
80 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
83 * Mark an irq as "lost". This is only used on the pmac
84 * since it can lose interrupts (see pmac_set_irq_mask).
88 __set_lost(unsigned long irq_nr, int nokick)
90 if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
91 atomic_inc(&ppc_n_lost_interrupts);
98 pmac_mask_and_ack_irq(unsigned int irq_nr)
100 unsigned long bit = 1UL << (irq_nr & 0x1f);
104 if ((unsigned)irq_nr >= max_irqs)
107 clear_bit(irq_nr, ppc_cached_irq_mask);
108 if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
109 atomic_dec(&ppc_n_lost_interrupts);
110 spin_lock_irqsave(&pmac_pic_lock, flags);
111 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
112 out_le32(&pmac_irq_hw[i]->ack, bit);
114 /* make sure ack gets to controller before we enable
117 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
118 != (ppc_cached_irq_mask[i] & bit));
119 spin_unlock_irqrestore(&pmac_pic_lock, flags);
122 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
124 unsigned long bit = 1UL << (irq_nr & 0x1f);
128 if ((unsigned)irq_nr >= max_irqs)
131 spin_lock_irqsave(&pmac_pic_lock, flags);
132 /* enable unmasked interrupts */
133 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
136 /* make sure mask gets to controller before we
139 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
140 != (ppc_cached_irq_mask[i] & bit));
143 * Unfortunately, setting the bit in the enable register
144 * when the device interrupt is already on *doesn't* set
145 * the bit in the flag register or request another interrupt.
147 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
148 __set_lost((ulong)irq_nr, nokicklost);
149 spin_unlock_irqrestore(&pmac_pic_lock, flags);
152 /* When an irq gets requested for the first client, if it's an
153 * edge interrupt, we clear any previous one on the controller
155 static unsigned int pmac_startup_irq(unsigned int irq_nr)
157 unsigned long bit = 1UL << (irq_nr & 0x1f);
160 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
161 out_le32(&pmac_irq_hw[i]->ack, bit);
162 set_bit(irq_nr, ppc_cached_irq_mask);
163 pmac_set_irq_mask(irq_nr, 0);
168 static void pmac_mask_irq(unsigned int irq_nr)
170 clear_bit(irq_nr, ppc_cached_irq_mask);
171 pmac_set_irq_mask(irq_nr, 0);
175 static void pmac_unmask_irq(unsigned int irq_nr)
177 set_bit(irq_nr, ppc_cached_irq_mask);
178 pmac_set_irq_mask(irq_nr, 0);
181 static void pmac_end_irq(unsigned int irq_nr)
183 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
184 && irq_desc[irq_nr].action) {
185 set_bit(irq_nr, ppc_cached_irq_mask);
186 pmac_set_irq_mask(irq_nr, 1);
191 struct hw_interrupt_type pmac_pic = {
192 .typename = " PMAC-PIC ",
193 .startup = pmac_startup_irq,
194 .enable = pmac_unmask_irq,
195 .disable = pmac_mask_irq,
196 .ack = pmac_mask_and_ack_irq,
200 struct hw_interrupt_type gatwick_pic = {
201 .typename = " GATWICK ",
202 .startup = pmac_startup_irq,
203 .enable = pmac_unmask_irq,
204 .disable = pmac_mask_irq,
205 .ack = pmac_mask_and_ack_irq,
209 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
213 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
215 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
216 /* We must read level interrupts from the level register */
217 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
218 bits &= ppc_cached_irq_mask[i];
221 irq += __ilog2(bits);
225 printk("gatwick irq not from gatwick pic\n");
230 pmac_get_irq(struct pt_regs *regs)
233 unsigned long bits = 0;
236 void psurge_smp_message_recv(struct pt_regs *);
238 /* IPI's are a hack on the powersurge -- Cort */
239 if ( smp_processor_id() != 0 ) {
240 psurge_smp_message_recv(regs);
241 return -2; /* ignore, already handled */
243 #endif /* CONFIG_SMP */
244 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
246 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
247 /* We must read level interrupts from the level register */
248 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
249 bits &= ppc_cached_irq_mask[i];
252 irq += __ilog2(bits);
259 /* This routine will fix some missing interrupt values in the device tree
260 * on the gatwick mac-io controller used by some PowerBooks
263 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
265 struct device_node *node;
268 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
274 if (strcasecmp(node->name, "escc") == 0)
276 if (node->child->n_intrs < 3) {
277 node->child->intrs = &gatwick_int_pool[count];
280 node->child->n_intrs = 3;
281 node->child->intrs[0].line = 15+irq_base;
282 node->child->intrs[1].line = 4+irq_base;
283 node->child->intrs[2].line = 5+irq_base;
284 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
285 node->child->intrs[0].line,
286 node->child->intrs[1].line,
287 node->child->intrs[2].line);
289 /* Fix media-bay & left SWIM */
290 if (strcasecmp(node->name, "media-bay") == 0) {
291 struct device_node* ya_node;
293 if (node->n_intrs == 0)
294 node->intrs = &gatwick_int_pool[count++];
296 node->intrs[0].line = 29+irq_base;
297 printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
298 node->intrs[0].line);
300 ya_node = node->child;
303 if (strcasecmp(ya_node->name, "floppy") == 0) {
304 if (ya_node->n_intrs < 2) {
305 ya_node->intrs = &gatwick_int_pool[count];
308 ya_node->n_intrs = 2;
309 ya_node->intrs[0].line = 19+irq_base;
310 ya_node->intrs[1].line = 1+irq_base;
311 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
312 ya_node->intrs[0].line, ya_node->intrs[1].line);
314 if (strcasecmp(ya_node->name, "ata4") == 0) {
315 if (ya_node->n_intrs < 2) {
316 ya_node->intrs = &gatwick_int_pool[count];
319 ya_node->n_intrs = 2;
320 ya_node->intrs[0].line = 14+irq_base;
321 ya_node->intrs[1].line = 3+irq_base;
322 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
323 ya_node->intrs[0].line, ya_node->intrs[1].line);
325 ya_node = ya_node->sibling;
328 node = node->sibling;
331 printk("WARNING !! Gatwick interrupt pool overflow\n");
332 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
333 printk(" requested = %d\n", count);
338 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
339 * card which includes an ohare chip that acts as a second interrupt
340 * controller. If we find this second ohare, set it up and fix the
341 * interrupt value in the device tree for the ethernet chip.
343 static int __init enable_second_ohare(void)
345 unsigned char bus, devfn;
348 struct device_node *irqctrler = find_devices("pci106b,7");
349 struct device_node *ether;
351 if (irqctrler == NULL || irqctrler->n_addrs <= 0)
353 addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
354 pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
356 if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
357 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
359 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
361 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
362 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
363 cmd &= ~PCI_COMMAND_IO;
364 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
368 /* Fix interrupt for the modem/ethernet combo controller. The number
369 in the device tree (27) is bogus (correct for the ethernet-only
370 board but not the combo ethernet/modem board).
371 The real interrupt is 28 on the second controller -> 28+32 = 60.
373 ether = find_devices("pci1011,14");
374 if (ether && ether->n_intrs > 0) {
375 ether->intrs[0].line = 60;
376 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
377 ether->intrs[0].line);
380 /* Return the interrupt number of the cascade */
381 return irqctrler->intrs[0].line;
385 static struct irqaction xmon_action = {
388 .mask = CPU_MASK_NONE,
393 static struct irqaction gatwick_cascade_action = {
394 .handler = gatwick_action,
395 .flags = SA_INTERRUPT,
396 .mask = CPU_MASK_NONE,
399 #endif /* CONFIG_PPC32 */
401 static int pmac_u3_cascade(struct pt_regs *regs, void *data)
403 return mpic_get_one_irq((struct mpic *)data, regs);
406 void __init pmac_pic_init(void)
408 struct device_node *irqctrler = NULL;
409 struct device_node *irqctrler2 = NULL;
410 struct device_node *np;
414 int irq_cascade = -1;
416 struct mpic *mpic1, *mpic2;
418 /* We first try to detect Apple's new Core99 chipset, since mac-io
419 * is quite different on those machines and contains an IBM MPIC2.
421 np = find_type_devices("open-pic");
423 if (np->parent && !strcmp(np->parent->name, "u3"))
429 if (irqctrler != NULL && irqctrler->n_addrs > 0) {
430 unsigned char senses[128];
432 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
433 (unsigned int)irqctrler->addrs[0].address);
434 ppc_md.get_irq = mpic_get_irq;
435 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
437 prom_get_irq_senses(senses, 0, 128);
438 mpic1 = mpic_alloc(irqctrler->addrs[0].address,
439 MPIC_PRIMARY | MPIC_WANTS_RESET,
440 0, 0, 128, 252, senses, 128, " OpenPIC ");
441 BUG_ON(mpic1 == NULL);
444 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
445 irqctrler2->n_addrs > 0) {
446 printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
447 (u32)irqctrler2->addrs[0].address,
448 irqctrler2->intrs[0].line);
450 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
451 prom_get_irq_senses(senses, 128, 128 + 124);
453 /* We don't need to set MPIC_BROKEN_U3 here since we don't have
454 * hypertransport interrupts routed to it
456 mpic2 = mpic_alloc(irqctrler2->addrs[0].address,
457 MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
458 0, 128, 124, 0, senses, 124,
460 BUG_ON(mpic2 == NULL);
462 mpic_setup_cascade(irqctrler2->intrs[0].line,
463 pmac_u3_cascade, mpic2);
465 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
467 struct device_node* pswitch;
470 pswitch = find_devices("programmer-switch");
471 if (pswitch && pswitch->n_intrs) {
472 nmi_irq = pswitch->intrs[0].line;
473 mpic_irq_set_priority(nmi_irq, 9);
474 setup_irq(nmi_irq, &xmon_action);
477 #endif /* CONFIG_XMON */
483 /* Get the level/edge settings, assume if it's not
484 * a Grand Central nor an OHare, then it's an Heathrow
487 if (find_devices("gc"))
488 level_mask[0] = GC_LEVEL_MASK;
489 else if (find_devices("ohare")) {
490 level_mask[0] = OHARE_LEVEL_MASK;
491 /* We might have a second cascaded ohare */
492 level_mask[1] = OHARE_LEVEL_MASK;
494 level_mask[0] = HEATHROW_LEVEL_MASK;
496 /* We might have a second cascaded heathrow */
497 level_mask[2] = HEATHROW_LEVEL_MASK;
502 * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
503 * 1998 G3 Series PowerBooks have 128,
504 * other powermacs have 32.
505 * The combo ethernet/modem card for the Powerstar powerbooks
506 * (2400/3400/3500, ohare based) has a second ohare chip
507 * effectively making a total of 64.
509 max_irqs = max_real_irqs = 32;
510 irqctrler = find_devices("mac-io");
519 for ( i = 0; i < max_real_irqs ; i++ )
520 irq_desc[i].handler = &pmac_pic;
522 /* get addresses of first controller */
524 if (irqctrler->n_addrs > 0) {
525 addr = (unsigned long)
526 ioremap(irqctrler->addrs[0].address, 0x40);
527 for (i = 0; i < 2; ++i)
528 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
529 (addr + (2 - i) * 0x10);
532 /* get addresses of second controller */
533 irqctrler = irqctrler->next;
534 if (irqctrler && irqctrler->n_addrs > 0) {
535 addr = (unsigned long)
536 ioremap(irqctrler->addrs[0].address, 0x40);
537 for (i = 2; i < 4; ++i)
538 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
539 (addr + (4 - i) * 0x10);
540 irq_cascade = irqctrler->intrs[0].line;
541 if (device_is_compatible(irqctrler, "gatwick"))
542 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
545 /* older powermacs have a GC (grand central) or ohare at
546 f3000000, with interrupt control registers at f3000020. */
547 addr = (unsigned long) ioremap(0xf3000000, 0x40);
548 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
551 /* PowerBooks 3400 and 3500 can have a second controller in a second
552 ohare chip, on the combo ethernet/modem card */
553 if (machine_is_compatible("AAPL,3400/2400")
554 || machine_is_compatible("AAPL,3500"))
555 irq_cascade = enable_second_ohare();
557 /* disable all interrupts in all controllers */
558 for (i = 0; i * 32 < max_irqs; ++i)
559 out_le32(&pmac_irq_hw[i]->enable, 0);
560 /* mark level interrupts */
561 for (i = 0; i < max_irqs; i++)
562 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
563 irq_desc[i].status = IRQ_LEVEL;
565 /* get interrupt line of secondary interrupt controller */
566 if (irq_cascade >= 0) {
567 printk(KERN_INFO "irq: secondary controller on irq %d\n",
569 for ( i = max_real_irqs ; i < max_irqs ; i++ )
570 irq_desc[i].handler = &gatwick_pic;
571 setup_irq(irq_cascade, &gatwick_cascade_action);
573 printk("System has %d possible interrupts\n", max_irqs);
574 if (max_irqs != max_real_irqs)
575 printk(KERN_DEBUG "%d interrupts on main controller\n",
579 setup_irq(20, &xmon_action);
580 #endif /* CONFIG_XMON */
581 #endif /* CONFIG_PPC32 */
586 * These procedures are used in implementing sleep on the powerbooks.
587 * sleep_save_intrs() saves the states of all interrupt enables
588 * and disables all interrupts except for the nominated one.
589 * sleep_restore_intrs() restores the states of all interrupt enables.
591 unsigned long sleep_save_mask[2];
593 /* This used to be passed by the PMU driver but that link got
594 * broken with the new driver model. We use this tweak for now...
596 static int pmacpic_find_viaint(void)
600 #ifdef CONFIG_ADB_PMU
601 struct device_node *np;
603 if (pmu_get_model() != PMU_OHARE_BASED)
605 np = of_find_node_by_name(NULL, "via-pmu");
608 viaint = np->intrs[0].line;
609 #endif /* CONFIG_ADB_PMU */
615 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
617 int viaint = pmacpic_find_viaint();
619 sleep_save_mask[0] = ppc_cached_irq_mask[0];
620 sleep_save_mask[1] = ppc_cached_irq_mask[1];
621 ppc_cached_irq_mask[0] = 0;
622 ppc_cached_irq_mask[1] = 0;
624 set_bit(viaint, ppc_cached_irq_mask);
625 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
626 if (max_real_irqs > 32)
627 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
628 (void)in_le32(&pmac_irq_hw[0]->event);
629 /* make sure mask gets to controller before we return to caller */
631 (void)in_le32(&pmac_irq_hw[0]->enable);
636 static int pmacpic_resume(struct sys_device *sysdev)
640 out_le32(&pmac_irq_hw[0]->enable, 0);
641 if (max_real_irqs > 32)
642 out_le32(&pmac_irq_hw[1]->enable, 0);
644 for (i = 0; i < max_real_irqs; ++i)
645 if (test_bit(i, sleep_save_mask))
651 #endif /* CONFIG_PM */
653 static struct sysdev_class pmacpic_sysclass = {
654 set_kset_name("pmac_pic"),
657 static struct sys_device device_pmacpic = {
659 .cls = &pmacpic_sysclass,
662 static struct sysdev_driver driver_pmacpic = {
664 .suspend = &pmacpic_suspend,
665 .resume = &pmacpic_resume,
666 #endif /* CONFIG_PM */
669 static int __init init_pmacpic_sysfs(void)
675 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
676 sysdev_class_register(&pmacpic_sysclass);
677 sysdev_register(&device_pmacpic);
678 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
682 subsys_initcall(init_pmacpic_sysfs);