2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/sysdev.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 #include <linux/module.h>
29 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
35 #include <asm/pmac_feature.h>
41 * XXX this should be in xmon.h, but putting it there means xmon.h
42 * has to include <linux/interrupt.h> (to get irqreturn_t), which
43 * causes all sorts of problems. -- paulus
45 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
55 /* Default addresses */
56 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
58 #define GC_LEVEL_MASK 0x3ff00000
59 #define OHARE_LEVEL_MASK 0x1ff00000
60 #define HEATHROW_LEVEL_MASK 0x1ff00000
63 static int max_real_irqs;
64 static u32 level_mask[4];
66 static DEFINE_SPINLOCK(pmac_pic_lock);
68 #define GATWICK_IRQ_POOL_SIZE 10
69 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
71 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
72 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
73 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
74 static int pmac_irq_cascade = -1;
76 static void __pmac_retrigger(unsigned int irq_nr)
78 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
79 __set_bit(irq_nr, ppc_lost_interrupts);
80 irq_nr = pmac_irq_cascade;
83 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
84 atomic_inc(&ppc_n_lost_interrupts);
89 static void pmac_mask_and_ack_irq(unsigned int irq_nr)
91 unsigned long bit = 1UL << (irq_nr & 0x1f);
95 if ((unsigned)irq_nr >= max_irqs)
98 spin_lock_irqsave(&pmac_pic_lock, flags);
99 __clear_bit(irq_nr, ppc_cached_irq_mask);
100 if (__test_and_clear_bit(irq_nr, ppc_lost_interrupts))
101 atomic_dec(&ppc_n_lost_interrupts);
102 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
103 out_le32(&pmac_irq_hw[i]->ack, bit);
105 /* make sure ack gets to controller before we enable
108 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
109 != (ppc_cached_irq_mask[i] & bit));
110 spin_unlock_irqrestore(&pmac_pic_lock, flags);
113 static void pmac_ack_irq(unsigned int irq_nr)
115 unsigned long bit = 1UL << (irq_nr & 0x1f);
119 if ((unsigned)irq_nr >= max_irqs)
122 spin_lock_irqsave(&pmac_pic_lock, flags);
123 if (__test_and_clear_bit(irq_nr, ppc_lost_interrupts))
124 atomic_dec(&ppc_n_lost_interrupts);
125 out_le32(&pmac_irq_hw[i]->ack, bit);
126 (void)in_le32(&pmac_irq_hw[i]->ack);
127 spin_unlock_irqrestore(&pmac_pic_lock, flags);
130 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
132 unsigned long bit = 1UL << (irq_nr & 0x1f);
135 if ((unsigned)irq_nr >= max_irqs)
138 /* enable unmasked interrupts */
139 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
142 /* make sure mask gets to controller before we
145 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
146 != (ppc_cached_irq_mask[i] & bit));
149 * Unfortunately, setting the bit in the enable register
150 * when the device interrupt is already on *doesn't* set
151 * the bit in the flag register or request another interrupt.
153 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
154 __pmac_retrigger(irq_nr);
157 /* When an irq gets requested for the first client, if it's an
158 * edge interrupt, we clear any previous one on the controller
160 static unsigned int pmac_startup_irq(unsigned int irq_nr)
163 unsigned long bit = 1UL << (irq_nr & 0x1f);
166 spin_lock_irqsave(&pmac_pic_lock, flags);
167 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
168 out_le32(&pmac_irq_hw[i]->ack, bit);
169 __set_bit(irq_nr, ppc_cached_irq_mask);
170 __pmac_set_irq_mask(irq_nr, 0);
171 spin_unlock_irqrestore(&pmac_pic_lock, flags);
176 static void pmac_mask_irq(unsigned int irq_nr)
180 spin_lock_irqsave(&pmac_pic_lock, flags);
181 __clear_bit(irq_nr, ppc_cached_irq_mask);
182 __pmac_set_irq_mask(irq_nr, 0);
183 spin_unlock_irqrestore(&pmac_pic_lock, flags);
186 static void pmac_unmask_irq(unsigned int irq_nr)
190 spin_lock_irqsave(&pmac_pic_lock, flags);
191 __set_bit(irq_nr, ppc_cached_irq_mask);
192 __pmac_set_irq_mask(irq_nr, 0);
193 spin_unlock_irqrestore(&pmac_pic_lock, flags);
196 static int pmac_retrigger(unsigned int irq_nr)
200 spin_lock_irqsave(&pmac_pic_lock, flags);
201 __pmac_retrigger(irq_nr);
202 spin_unlock_irqrestore(&pmac_pic_lock, flags);
206 static struct irq_chip pmac_pic = {
207 .typename = " PMAC-PIC ",
208 .startup = pmac_startup_irq,
209 .mask = pmac_mask_irq,
211 .mask_ack = pmac_mask_and_ack_irq,
212 .unmask = pmac_unmask_irq,
213 .retrigger = pmac_retrigger,
216 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
222 spin_lock_irqsave(&pmac_pic_lock, flags);
223 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
225 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
226 /* We must read level interrupts from the level register */
227 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
228 bits &= ppc_cached_irq_mask[i];
231 irq += __ilog2(bits);
232 spin_unlock_irqrestore(&pmac_pic_lock, flags);
234 spin_lock_irqsave(&pmac_pic_lock, flags);
237 spin_unlock_irqrestore(&pmac_pic_lock, flags);
241 static int pmac_get_irq(struct pt_regs *regs)
244 unsigned long bits = 0;
248 void psurge_smp_message_recv(struct pt_regs *);
250 /* IPI's are a hack on the powersurge -- Cort */
251 if ( smp_processor_id() != 0 ) {
252 psurge_smp_message_recv(regs);
253 return -2; /* ignore, already handled */
255 #endif /* CONFIG_SMP */
256 spin_lock_irqsave(&pmac_pic_lock, flags);
257 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
259 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
260 /* We must read level interrupts from the level register */
261 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
262 bits &= ppc_cached_irq_mask[i];
265 irq += __ilog2(bits);
268 spin_unlock_irqrestore(&pmac_pic_lock, flags);
273 /* This routine will fix some missing interrupt values in the device tree
274 * on the gatwick mac-io controller used by some PowerBooks
276 * Walking of OF nodes could use a bit more fixing up here, but it's not
277 * very important as this is all boot time code on static portions of the
280 * However, the modifications done to "intrs" will have to be removed and
281 * replaced with proper updates of the "interrupts" properties or
282 * AAPL,interrupts, yet to be decided, once the dynamic parsing is there.
284 static void __init pmac_fix_gatwick_interrupts(struct device_node *gw,
287 struct device_node *node;
290 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
292 for (node = NULL; (node = of_get_next_child(gw, node)) != NULL;) {
294 if ((strcasecmp(node->name, "escc") == 0) && node->child) {
295 if (node->child->n_intrs < 3) {
296 node->child->intrs = &gatwick_int_pool[count];
299 node->child->n_intrs = 3;
300 node->child->intrs[0].line = 15+irq_base;
301 node->child->intrs[1].line = 4+irq_base;
302 node->child->intrs[2].line = 5+irq_base;
303 printk(KERN_INFO "irq: fixed SCC on gatwick"
305 node->child->intrs[0].line,
306 node->child->intrs[1].line,
307 node->child->intrs[2].line);
309 /* Fix media-bay & left SWIM */
310 if (strcasecmp(node->name, "media-bay") == 0) {
311 struct device_node* ya_node;
313 if (node->n_intrs == 0)
314 node->intrs = &gatwick_int_pool[count++];
316 node->intrs[0].line = 29+irq_base;
317 printk(KERN_INFO "irq: fixed media-bay on gatwick"
318 " (%d)\n", node->intrs[0].line);
320 ya_node = node->child;
322 if (strcasecmp(ya_node->name, "floppy") == 0) {
323 if (ya_node->n_intrs < 2) {
324 ya_node->intrs = &gatwick_int_pool[count];
327 ya_node->n_intrs = 2;
328 ya_node->intrs[0].line = 19+irq_base;
329 ya_node->intrs[1].line = 1+irq_base;
330 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
331 ya_node->intrs[0].line, ya_node->intrs[1].line);
333 if (strcasecmp(ya_node->name, "ata4") == 0) {
334 if (ya_node->n_intrs < 2) {
335 ya_node->intrs = &gatwick_int_pool[count];
338 ya_node->n_intrs = 2;
339 ya_node->intrs[0].line = 14+irq_base;
340 ya_node->intrs[1].line = 3+irq_base;
341 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
342 ya_node->intrs[0].line, ya_node->intrs[1].line);
344 ya_node = ya_node->sibling;
349 printk("WARNING !! Gatwick interrupt pool overflow\n");
350 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
351 printk(" requested = %d\n", count);
356 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
357 * card which includes an ohare chip that acts as a second interrupt
358 * controller. If we find this second ohare, set it up and fix the
359 * interrupt value in the device tree for the ethernet chip.
361 static void __init enable_second_ohare(struct device_node *np)
363 unsigned char bus, devfn;
365 struct device_node *ether;
367 /* This code doesn't strictly belong here, it could be part of
368 * either the PCI initialisation or the feature code. It's kept
369 * here for historical reasons.
371 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
372 struct pci_controller* hose =
373 pci_find_hose_for_OF_device(np);
375 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
378 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
379 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
380 cmd &= ~PCI_COMMAND_IO;
381 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
384 /* Fix interrupt for the modem/ethernet combo controller. The number
385 * in the device tree (27) is bogus (correct for the ethernet-only
386 * board but not the combo ethernet/modem board).
387 * The real interrupt is 28 on the second controller -> 28+32 = 60.
389 ether = of_find_node_by_name(NULL, "pci1011,14");
390 if (ether && ether->n_intrs > 0) {
391 ether->intrs[0].line = 60;
392 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
393 ether->intrs[0].line);
399 static struct irqaction xmon_action = {
402 .mask = CPU_MASK_NONE,
407 static struct irqaction gatwick_cascade_action = {
408 .handler = gatwick_action,
409 .flags = IRQF_DISABLED,
410 .mask = CPU_MASK_NONE,
414 static void __init pmac_pic_probe_oldstyle(void)
417 struct device_node *master = NULL;
418 struct device_node *slave = NULL;
422 /* Set our get_irq function */
423 ppc_md.get_irq = pmac_get_irq;
426 * Find the interrupt controller type & node
429 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
430 max_irqs = max_real_irqs = 32;
431 level_mask[0] = GC_LEVEL_MASK;
432 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
433 max_irqs = max_real_irqs = 32;
434 level_mask[0] = OHARE_LEVEL_MASK;
436 /* We might have a second cascaded ohare */
437 slave = of_find_node_by_name(NULL, "pci106b,7");
440 level_mask[1] = OHARE_LEVEL_MASK;
441 enable_second_ohare(slave);
443 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
444 max_irqs = max_real_irqs = 64;
445 level_mask[0] = HEATHROW_LEVEL_MASK;
448 /* We might have a second cascaded heathrow */
449 slave = of_find_node_by_name(master, "mac-io");
451 /* Check ordering of master & slave */
452 if (device_is_compatible(master, "gatwick")) {
453 struct device_node *tmp;
454 BUG_ON(slave == NULL);
460 /* We found a slave */
463 level_mask[2] = HEATHROW_LEVEL_MASK;
465 pmac_fix_gatwick_interrupts(slave, max_real_irqs);
468 BUG_ON(master == NULL);
470 /* Mark level interrupts and set handlers */
471 for (i = 0; i < max_irqs; i++) {
472 int level = !!(level_mask[i >> 5] & (1UL << (i & 0x1f)));
474 irq_desc[i].status |= IRQ_LEVEL;
476 irq_desc[i].status |= IRQ_DELAYED_DISABLE;
477 set_irq_chip_and_handler(i, &pmac_pic, level ?
478 handle_level_irq : handle_edge_irq);
481 /* Get addresses of first controller if we have a node for it */
482 BUG_ON(of_address_to_resource(master, 0, &r));
484 /* Map interrupts of primary controller */
485 addr = (u8 __iomem *) ioremap(r.start, 0x40);
487 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
489 if (max_real_irqs > 32)
490 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
494 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
495 master->full_name, max_real_irqs);
497 /* Map interrupts of cascaded controller */
498 if (slave && !of_address_to_resource(slave, 0, &r)) {
499 addr = (u8 __iomem *)ioremap(r.start, 0x40);
500 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
504 (volatile struct pmac_irq_hw __iomem *)
506 pmac_irq_cascade = slave->intrs[0].line;
508 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
509 " cascade: %d\n", slave->full_name,
510 max_irqs - max_real_irqs, pmac_irq_cascade);
514 /* Disable all interrupts in all controllers */
515 for (i = 0; i * 32 < max_irqs; ++i)
516 out_le32(&pmac_irq_hw[i]->enable, 0);
518 /* Hookup cascade irq */
520 setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
522 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
524 setup_irq(20, &xmon_action);
527 #endif /* CONFIG_PPC32 */
529 static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc,
530 struct pt_regs *regs)
532 struct mpic *mpic = desc->handler_data;
533 unsigned int max = 100;
536 int cascade_irq = mpic_get_one_irq(mpic, regs);
538 desc->chip->eoi(irq);
541 generic_handle_irq(cascade_irq, regs);
545 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
547 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
548 struct device_node* pswitch;
551 pswitch = of_find_node_by_name(NULL, "programmer-switch");
552 if (pswitch && pswitch->n_intrs) {
553 nmi_irq = pswitch->intrs[0].line;
554 mpic_irq_set_priority(nmi_irq, 9);
555 setup_irq(nmi_irq, &xmon_action);
557 of_node_put(pswitch);
558 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
561 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
564 unsigned char senses[128];
565 int offset = master ? 0 : 128;
566 int count = master ? 128 : 124;
567 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
570 unsigned int flags = master ? MPIC_PRIMARY : 0;
573 rc = of_address_to_resource(np, 0, &r);
577 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
579 prom_get_irq_senses(senses, offset, offset + count);
581 flags |= MPIC_WANTS_RESET;
582 if (get_property(np, "big-endian", NULL))
583 flags |= MPIC_BIG_ENDIAN;
585 /* Primary Big Endian means HT interrupts. This is quite dodgy
586 * but works until I find a better way
588 if (master && (flags & MPIC_BIG_ENDIAN))
589 flags |= MPIC_BROKEN_U3;
591 mpic = mpic_alloc(r.start, flags, 0, offset, count, master ? 252 : 0,
592 senses, count, name);
601 static int __init pmac_pic_probe_mpic(void)
603 struct mpic *mpic1, *mpic2;
604 struct device_node *np, *master = NULL, *slave = NULL;
606 /* We can have up to 2 MPICs cascaded */
607 for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
609 if (master == NULL &&
610 get_property(np, "interrupts", NULL) == NULL)
611 master = of_node_get(np);
612 else if (slave == NULL)
613 slave = of_node_get(np);
618 /* Check for bogus setups */
619 if (master == NULL && slave != NULL) {
624 /* Not found, default to good old pmac pic */
628 /* Set master handler */
629 ppc_md.get_irq = mpic_get_irq;
632 mpic1 = pmac_setup_one_mpic(master, 1);
633 BUG_ON(mpic1 == NULL);
635 /* Install NMI if any */
636 pmac_pic_setup_mpic_nmi(mpic1);
640 /* No slave, let's go out */
641 if (slave == NULL || slave->n_intrs < 1)
644 mpic2 = pmac_setup_one_mpic(slave, 0);
646 printk(KERN_ERR "Failed to setup slave MPIC\n");
650 set_irq_data(slave->intrs[0].line, mpic2);
651 set_irq_chained_handler(slave->intrs[0].line, pmac_u3_cascade);
658 void __init pmac_pic_init(void)
660 /* We first try to detect Apple's new Core99 chipset, since mac-io
661 * is quite different on those machines and contains an IBM MPIC2.
663 if (pmac_pic_probe_mpic() == 0)
667 pmac_pic_probe_oldstyle();
671 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
673 * These procedures are used in implementing sleep on the powerbooks.
674 * sleep_save_intrs() saves the states of all interrupt enables
675 * and disables all interrupts except for the nominated one.
676 * sleep_restore_intrs() restores the states of all interrupt enables.
678 unsigned long sleep_save_mask[2];
680 /* This used to be passed by the PMU driver but that link got
681 * broken with the new driver model. We use this tweak for now...
683 static int pmacpic_find_viaint(void)
687 #ifdef CONFIG_ADB_PMU
688 struct device_node *np;
690 if (pmu_get_model() != PMU_OHARE_BASED)
692 np = of_find_node_by_name(NULL, "via-pmu");
695 viaint = np->intrs[0].line;
696 #endif /* CONFIG_ADB_PMU */
702 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
704 int viaint = pmacpic_find_viaint();
706 sleep_save_mask[0] = ppc_cached_irq_mask[0];
707 sleep_save_mask[1] = ppc_cached_irq_mask[1];
708 ppc_cached_irq_mask[0] = 0;
709 ppc_cached_irq_mask[1] = 0;
711 set_bit(viaint, ppc_cached_irq_mask);
712 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
713 if (max_real_irqs > 32)
714 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
715 (void)in_le32(&pmac_irq_hw[0]->event);
716 /* make sure mask gets to controller before we return to caller */
718 (void)in_le32(&pmac_irq_hw[0]->enable);
723 static int pmacpic_resume(struct sys_device *sysdev)
727 out_le32(&pmac_irq_hw[0]->enable, 0);
728 if (max_real_irqs > 32)
729 out_le32(&pmac_irq_hw[1]->enable, 0);
731 for (i = 0; i < max_real_irqs; ++i)
732 if (test_bit(i, sleep_save_mask))
738 #endif /* CONFIG_PM && CONFIG_PPC32 */
740 static struct sysdev_class pmacpic_sysclass = {
741 set_kset_name("pmac_pic"),
744 static struct sys_device device_pmacpic = {
746 .cls = &pmacpic_sysclass,
749 static struct sysdev_driver driver_pmacpic = {
750 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
751 .suspend = &pmacpic_suspend,
752 .resume = &pmacpic_resume,
753 #endif /* CONFIG_PM && CONFIG_PPC32 */
756 static int __init init_pmacpic_sysfs(void)
762 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
763 sysdev_class_register(&pmacpic_sysclass);
764 sysdev_register(&device_pmacpic);
765 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
769 subsys_initcall(init_pmacpic_sysfs);