2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/pmac_feature.h>
27 #include <asm/iommu.h>
28 #include <asm/ppc-pci.h>
34 #define DBG(x...) printk(x)
39 static int add_bridge(struct device_node *dev);
40 extern void pmac_check_ht_link(void);
42 /* XXX Could be per-controller, but I don't think we risk anything by
43 * assuming we won't have both UniNorth and Bandit */
44 static int has_uninorth;
46 static struct pci_controller *u3_agp;
47 #endif /* CONFIG_POWER4 */
49 extern u8 pci_cache_line_size;
50 extern int pcibios_assign_bus_offset;
52 struct device_node *k2_skiplist[2];
55 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
57 #define BANDIT_DEVID_2 8
58 #define BANDIT_REVID 3
60 #define BANDIT_DEVNUM 11
61 #define BANDIT_MAGIC 0x50
62 #define BANDIT_COHERENT 0x40
64 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
66 for (; node != 0;node = node->sibling) {
68 unsigned int *class_code;
71 /* For PCI<->PCI bridges or CardBus bridges, we go down */
72 class_code = (unsigned int *) get_property(node, "class-code", NULL);
73 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
74 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
76 bus_range = (int *) get_property(node, "bus-range", &len);
77 if (bus_range != NULL && len > 2 * sizeof(int)) {
78 if (bus_range[1] > higher)
79 higher = bus_range[1];
81 higher = fixup_one_level_bus_range(node->child, higher);
86 /* This routine fixes the "bus-range" property of all bridges in the
87 * system since they tend to have their "last" member wrong on macs
89 * Note that the bus numbers manipulated here are OF bus numbers, they
90 * are not Linux bus numbers.
92 static void __init fixup_bus_range(struct device_node *bridge)
97 /* Lookup the "bus-range" property for the hose */
98 bus_range = (int *) get_property(bridge, "bus-range", &len);
99 if (bus_range == NULL || len < 2 * sizeof(int)) {
100 printk(KERN_WARNING "Can't get bus-range for %s\n",
104 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
108 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
110 * The "Bandit" version is present in all early PCI PowerMacs,
111 * and up to the first ones using Grackle. Some machines may
112 * have 2 bandit controllers (2 PCI busses).
114 * "Chaos" is used in some "Bandit"-type machines as a bridge
115 * for the separate display bus. It is accessed the same
116 * way as bandit, but cannot be probed for devices. It therefore
117 * has its own config access functions.
119 * The "UniNorth" version is present in all Core99 machines
120 * (iBook, G4, new IMacs, and all the recent Apple machines).
121 * It contains 3 controllers in one ASIC.
123 * The U3 is the bridge used on G5 machines. It contains an
124 * AGP bus which is dealt with the old UniNorth access routines
125 * and a HyperTransport bus which uses its own set of access
129 #define MACRISC_CFA0(devfn, off) \
130 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
131 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
132 | (((unsigned long)(off)) & 0xFCUL))
134 #define MACRISC_CFA1(bus, devfn, off) \
135 ((((unsigned long)(bus)) << 16) \
136 |(((unsigned long)(devfn)) << 8) \
137 |(((unsigned long)(off)) & 0xFCUL) \
140 static unsigned long macrisc_cfg_access(struct pci_controller* hose,
141 u8 bus, u8 dev_fn, u8 offset)
145 if (bus == hose->first_busno) {
146 if (dev_fn < (11 << 3))
148 caddr = MACRISC_CFA0(dev_fn, offset);
150 caddr = MACRISC_CFA1(bus, dev_fn, offset);
152 /* Uninorth will return garbage if we don't read back the value ! */
154 out_le32(hose->cfg_addr, caddr);
155 } while (in_le32(hose->cfg_addr) != caddr);
157 offset &= has_uninorth ? 0x07 : 0x03;
158 return ((unsigned long)hose->cfg_data) + offset;
161 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
162 int offset, int len, u32 *val)
164 struct pci_controller *hose;
167 hose = pci_bus_to_host(bus);
169 return PCIBIOS_DEVICE_NOT_FOUND;
171 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 return PCIBIOS_DEVICE_NOT_FOUND;
175 * Note: the caller has already checked that offset is
176 * suitably aligned and that len is 1, 2 or 4.
180 *val = in_8((u8 *)addr);
183 *val = in_le16((u16 *)addr);
186 *val = in_le32((u32 *)addr);
189 return PCIBIOS_SUCCESSFUL;
192 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
193 int offset, int len, u32 val)
195 struct pci_controller *hose;
198 hose = pci_bus_to_host(bus);
200 return PCIBIOS_DEVICE_NOT_FOUND;
202 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
204 return PCIBIOS_DEVICE_NOT_FOUND;
206 * Note: the caller has already checked that offset is
207 * suitably aligned and that len is 1, 2 or 4.
211 out_8((u8 *)addr, val);
212 (void) in_8((u8 *)addr);
215 out_le16((u16 *)addr, val);
216 (void) in_le16((u16 *)addr);
219 out_le32((u32 *)addr, val);
220 (void) in_le32((u32 *)addr);
223 return PCIBIOS_SUCCESSFUL;
226 static struct pci_ops macrisc_pci_ops =
233 * Verify that a specific (bus, dev_fn) exists on chaos
236 chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
238 struct device_node *np;
239 u32 *vendor, *device;
241 np = pci_busdev_to_OF_node(bus, devfn);
243 return PCIBIOS_DEVICE_NOT_FOUND;
245 vendor = (u32 *)get_property(np, "vendor-id", NULL);
246 device = (u32 *)get_property(np, "device-id", NULL);
247 if (vendor == NULL || device == NULL)
248 return PCIBIOS_DEVICE_NOT_FOUND;
250 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
251 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
252 return PCIBIOS_BAD_REGISTER_NUMBER;
254 return PCIBIOS_SUCCESSFUL;
258 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
261 int result = chaos_validate_dev(bus, devfn, offset);
262 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
264 if (result != PCIBIOS_SUCCESSFUL)
266 return macrisc_read_config(bus, devfn, offset, len, val);
270 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
273 int result = chaos_validate_dev(bus, devfn, offset);
274 if (result != PCIBIOS_SUCCESSFUL)
276 return macrisc_write_config(bus, devfn, offset, len, val);
279 static struct pci_ops chaos_pci_ops =
287 * These versions of U3 HyperTransport config space access ops do not
288 * implement self-view of the HT host yet
292 * This function deals with some "special cases" devices.
294 * 0 -> No special case
295 * 1 -> Skip the device but act as if the access was successfull
296 * (return 0xff's on reads, eventually, cache config space
297 * accesses in a later version)
298 * -1 -> Hide the device (unsuccessful acess)
300 static int u3_ht_skip_device(struct pci_controller *hose,
301 struct pci_bus *bus, unsigned int devfn)
303 struct device_node *busdn, *dn;
306 /* We only allow config cycles to devices that are in OF device-tree
307 * as we are apparently having some weird things going on with some
308 * revs of K2 on recent G5s
311 busdn = pci_device_to_OF_node(bus->self);
313 busdn = hose->arch_data;
314 for (dn = busdn->child; dn; dn = dn->sibling)
315 if (dn->data && PCI_DN(dn)->devfn == devfn)
321 * When a device in K2 is powered down, we die on config
322 * cycle accesses. Fix that here.
325 if (k2_skiplist[i] == dn)
331 #define U3_HT_CFA0(devfn, off) \
332 ((((unsigned long)devfn) << 8) | offset)
333 #define U3_HT_CFA1(bus, devfn, off) \
334 (U3_HT_CFA0(devfn, off) \
335 + (((unsigned long)bus) << 16) \
338 static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
339 u8 bus, u8 devfn, u8 offset)
341 if (bus == hose->first_busno) {
342 /* For now, we don't self probe U3 HT bridge */
343 if (PCI_SLOT(devfn) == 0)
345 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
347 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
350 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
351 int offset, int len, u32 *val)
353 struct pci_controller *hose;
356 hose = pci_bus_to_host(bus);
358 return PCIBIOS_DEVICE_NOT_FOUND;
360 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
362 return PCIBIOS_DEVICE_NOT_FOUND;
364 switch (u3_ht_skip_device(hose, bus, devfn)) {
372 *val = 0xffff; break;
374 *val = 0xfffffffful; break;
376 return PCIBIOS_SUCCESSFUL;
378 return PCIBIOS_DEVICE_NOT_FOUND;
382 * Note: the caller has already checked that offset is
383 * suitably aligned and that len is 1, 2 or 4.
387 *val = in_8((u8 *)addr);
390 *val = in_le16((u16 *)addr);
393 *val = in_le32((u32 *)addr);
396 return PCIBIOS_SUCCESSFUL;
399 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
400 int offset, int len, u32 val)
402 struct pci_controller *hose;
405 hose = pci_bus_to_host(bus);
407 return PCIBIOS_DEVICE_NOT_FOUND;
409 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
411 return PCIBIOS_DEVICE_NOT_FOUND;
413 switch (u3_ht_skip_device(hose, bus, devfn)) {
417 return PCIBIOS_SUCCESSFUL;
419 return PCIBIOS_DEVICE_NOT_FOUND;
423 * Note: the caller has already checked that offset is
424 * suitably aligned and that len is 1, 2 or 4.
428 out_8((u8 *)addr, val);
429 (void) in_8((u8 *)addr);
432 out_le16((u16 *)addr, val);
433 (void) in_le16((u16 *)addr);
436 out_le32((u32 *)addr, val);
437 (void) in_le32((u32 *)addr);
440 return PCIBIOS_SUCCESSFUL;
443 static struct pci_ops u3_ht_pci_ops =
448 #endif /* CONFIG_POWER4 */
451 * For a bandit bridge, turn on cache coherency if necessary.
452 * N.B. we could clean this up using the hose ops directly.
454 static void __init init_bandit(struct pci_controller *bp)
456 unsigned int vendev, magic;
459 /* read the word at offset 0 in config space for device 11 */
460 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
462 vendev = in_le32(bp->cfg_data);
463 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
464 PCI_VENDOR_ID_APPLE) {
465 /* read the revision id */
466 out_le32(bp->cfg_addr,
467 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
469 rev = in_8(bp->cfg_data);
470 if (rev != BANDIT_REVID)
472 "Unknown revision %d for bandit\n", rev);
473 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
474 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
478 /* read the word at offset 0x50 */
479 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
481 magic = in_le32(bp->cfg_data);
482 if ((magic & BANDIT_COHERENT) != 0)
484 magic |= BANDIT_COHERENT;
486 out_le32(bp->cfg_data, magic);
487 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
492 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
494 static void __init init_p2pbridge(void)
496 struct device_node *p2pbridge;
497 struct pci_controller* hose;
501 /* XXX it would be better here to identify the specific
502 PCI-PCI bridge chip we have. */
503 if ((p2pbridge = find_devices("pci-bridge")) == 0
504 || p2pbridge->parent == NULL
505 || strcmp(p2pbridge->parent->name, "pci") != 0)
507 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
508 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
511 /* Warning: At this point, we have not yet renumbered all busses.
512 * So we must use OF walking to find out hose
514 hose = pci_find_hose_for_OF_device(p2pbridge);
516 DBG("Can't find hose for PCI<->PCI bridge\n");
519 if (early_read_config_word(hose, bus, devfn,
520 PCI_BRIDGE_CONTROL, &val) < 0) {
521 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
524 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
525 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
529 * Some Apple desktop machines have a NEC PD720100A USB2 controller
530 * on the motherboard. Open Firmware, on these, will disable the
531 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
532 * code re-enables it ;)
534 static void __init fixup_nec_usb2(void)
536 struct device_node *nec;
538 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
539 struct pci_controller *hose;
543 prop = (u32 *)get_property(nec, "vendor-id", NULL);
548 prop = (u32 *)get_property(nec, "device-id", NULL);
553 prop = (u32 *)get_property(nec, "reg", NULL);
556 devfn = (prop[0] >> 8) & 0xff;
557 bus = (prop[0] >> 16) & 0xff;
558 if (PCI_FUNC(devfn) != 0)
560 hose = pci_find_hose_for_OF_device(nec);
563 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
565 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
567 early_write_config_dword(hose, bus, devfn, 0xe4, data);
568 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
574 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
575 | (((o) & ~3) << 24))
577 #define GRACKLE_PICR1_STG 0x00000040
578 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
580 /* N.B. this is called before bridges is initialized, so we can't
581 use grackle_pcibios_{read,write}_config_dword. */
582 static inline void grackle_set_stg(struct pci_controller* bp, int enable)
586 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
587 val = in_le32(bp->cfg_data);
588 val = enable? (val | GRACKLE_PICR1_STG) :
589 (val & ~GRACKLE_PICR1_STG);
590 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
591 out_le32(bp->cfg_data, val);
592 (void)in_le32(bp->cfg_data);
595 static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
599 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
600 val = in_le32(bp->cfg_data);
601 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
602 (val & ~GRACKLE_PICR1_LOOPSNOOP);
603 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
604 out_le32(bp->cfg_data, val);
605 (void)in_le32(bp->cfg_data);
609 setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
611 pci_assign_all_busses = 1;
613 hose->ops = ¯isc_pci_ops;
614 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
615 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
616 /* We "know" that the bridge at f2000000 has the PCI slots. */
617 return addr->address == 0xf2000000;
621 setup_bandit(struct pci_controller* hose, struct reg_property* addr)
623 hose->ops = ¯isc_pci_ops;
624 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
625 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
630 setup_chaos(struct pci_controller* hose, struct reg_property* addr)
632 /* assume a `chaos' bridge */
633 hose->ops = &chaos_pci_ops;
634 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
635 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
639 static void __init setup_u3_agp(struct pci_controller* hose)
641 /* On G5, we move AGP up to high bus number so we don't need
642 * to reassign bus numbers for HT. If we ever have P2P bridges
643 * on AGP, we'll have to move pci_assign_all_busses to the
644 * pci_controller structure so we enable it for AGP and not for
646 * We hard code the address because of the different size of
647 * the reg address cell, we shall fix that by killing struct
648 * reg_property and using some accessor functions instead
650 hose->first_busno = 0xf0;
651 hose->last_busno = 0xff;
653 hose->ops = ¯isc_pci_ops;
654 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
655 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
660 static void __init setup_u3_ht(struct pci_controller* hose)
662 struct device_node *np = (struct device_node *)hose->arch_data;
665 hose->ops = &u3_ht_pci_ops;
667 /* We hard code the address because of the different size of
668 * the reg address cell, we shall fix that by killing struct
669 * reg_property and using some accessor functions instead
671 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
674 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
675 * have been allocated to AGP. So far, this version of the code doesn't assign
676 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
677 * We need to fix that sooner or later by either parsing all child "ranges"
678 * properties or figuring out the U3 address space decoding logic and
679 * then read its configuration register (if any).
681 hose->io_base_phys = 0xf4000000;
682 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
683 isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
684 hose->io_resource.name = np->full_name;
685 hose->io_resource.start = 0;
686 hose->io_resource.end = 0x003fffff;
687 hose->io_resource.flags = IORESOURCE_IO;
688 hose->pci_mem_offset = 0;
689 hose->first_busno = 0;
690 hose->last_busno = 0xef;
691 hose->mem_resources[0].name = np->full_name;
692 hose->mem_resources[0].start = 0x80000000;
693 hose->mem_resources[0].end = 0xefffffff;
694 hose->mem_resources[0].flags = IORESOURCE_MEM;
696 if (u3_agp == NULL) {
697 DBG("U3 has no AGP, using full resource range\n");
701 /* We "remove" the AGP resources from the resources allocated to HT, that
702 * is we create "holes". However, that code does assumptions that so far
703 * happen to be true (cross fingers...), typically that resources in the
704 * AGP node are properly ordered
707 for (i=0; i<3; i++) {
708 struct resource *res = &u3_agp->mem_resources[i];
709 if (res->flags != IORESOURCE_MEM)
711 /* We don't care about "fine" resources */
712 if (res->start >= 0xf0000000)
714 /* Check if it's just a matter of "shrinking" us in one direction */
715 if (hose->mem_resources[cur].start == res->start) {
716 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
717 cur, hose->mem_resources[cur].start, res->end + 1);
718 hose->mem_resources[cur].start = res->end + 1;
721 if (hose->mem_resources[cur].end == res->end) {
722 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
723 cur, hose->mem_resources[cur].end, res->start - 1);
724 hose->mem_resources[cur].end = res->start - 1;
727 /* No, it's not the case, we need a hole */
729 /* not enough resources for a hole, we drop part of the range */
730 printk(KERN_WARNING "Running out of resources for /ht host !\n");
731 hose->mem_resources[cur].end = res->start - 1;
735 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
736 cur-1, res->start - 1, cur, res->end + 1);
737 hose->mem_resources[cur].name = np->full_name;
738 hose->mem_resources[cur].flags = IORESOURCE_MEM;
739 hose->mem_resources[cur].start = res->end + 1;
740 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
741 hose->mem_resources[cur-1].end = res->start - 1;
745 #endif /* CONFIG_POWER4 */
748 setup_grackle(struct pci_controller *hose)
750 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
751 if (machine_is_compatible("AAPL,PowerBook1998"))
752 grackle_set_loop_snoop(hose, 1);
753 #if 0 /* Disabled for now, HW problems ??? */
754 grackle_set_stg(hose, 1);
758 static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose,
759 struct device_node *dev, int primary)
761 static unsigned int static_lc_ranges[2024];
762 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
764 int rlen = 0, orig_rlen;
766 struct resource *res;
767 int np, na = prom_n_addr_cells(dev);
771 /* First we try to merge ranges to fix a problem with some pmacs
772 * that can have more than 3 ranges, fortunately using contiguous
775 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
778 /* lc_ranges = alloc_bootmem(rlen);*/
779 lc_ranges = static_lc_ranges;
781 return; /* what can we do here ? */
782 memcpy(lc_ranges, dt_ranges, rlen);
785 /* Let's work on a copy of the "ranges" property instead of damaging
786 * the device-tree image in memory
790 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
792 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
793 (prev[2] + prev[na+4]) == ranges[2] &&
794 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
795 prev[na+4] += ranges[na+4];
806 * The ranges property is laid out as an array of elements,
807 * each of which comprises:
808 * cells 0 - 2: a PCI address
809 * cells 3 or 3+4: a CPU physical address
810 * (size depending on dev->n_addr_cells)
811 * cells 4+5 or 5+6: the size of the range
815 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
818 switch (ranges[0] >> 24) {
819 case 1: /* I/O space */
822 hose->io_base_phys = ranges[na+2];
823 /* limit I/O space to 16MB */
824 if (size > 0x01000000)
826 hose->io_base_virt = ioremap(ranges[na+2], size);
828 isa_io_base = (unsigned long) hose->io_base_virt;
829 res = &hose->io_resource;
830 res->flags = IORESOURCE_IO;
831 res->start = ranges[2];
833 case 2: /* memory space */
835 if (ranges[1] == 0 && ranges[2] == 0
836 && ranges[na+4] <= (16 << 20)) {
837 /* 1st 16MB, i.e. ISA memory area */
840 isa_mem_base = ranges[na+2];
844 while (memno < 3 && hose->mem_resources[memno].flags)
847 hose->pci_mem_offset = ranges[na+2] - ranges[2];
849 res = &hose->mem_resources[memno];
850 res->flags = IORESOURCE_MEM;
851 res->start = ranges[na+2];
856 res->name = dev->full_name;
857 res->end = res->start + size - 1;
867 * We assume that if we have a G3 powermac, we have one bridge called
868 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
869 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
871 static int __init add_bridge(struct device_node *dev)
874 struct pci_controller *hose;
875 struct reg_property *addr;
880 DBG("Adding PCI host bridge %s\n", dev->full_name);
882 addr = (struct reg_property *) get_property(dev, "reg", &len);
883 if (addr == NULL || len < sizeof(*addr)) {
884 printk(KERN_WARNING "Can't use %s: no address\n",
888 bus_range = (int *) get_property(dev, "bus-range", &len);
889 if (bus_range == NULL || len < 2 * sizeof(int)) {
890 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
894 hose = pcibios_alloc_controller();
897 hose->arch_data = dev;
898 hose->first_busno = bus_range ? bus_range[0] : 0;
899 hose->last_busno = bus_range ? bus_range[1] : 0xff;
903 if (device_is_compatible(dev, "u3-agp")) {
904 setup_u3_agp(hose, addr);
905 disp_name = "U3-AGP";
907 } else if (device_is_compatible(dev, "u3-ht")) {
908 setup_u3_ht(hose, addr);
912 #endif /* CONFIG_POWER4 */
913 if (device_is_compatible(dev, "uni-north")) {
914 primary = setup_uninorth(hose, addr);
915 disp_name = "UniNorth";
916 } else if (strcmp(dev->name, "pci") == 0) {
917 /* XXX assume this is a mpc106 (grackle) */
919 disp_name = "Grackle (MPC106)";
920 } else if (strcmp(dev->name, "bandit") == 0) {
921 setup_bandit(hose, addr);
922 disp_name = "Bandit";
923 } else if (strcmp(dev->name, "chaos") == 0) {
924 setup_chaos(hose, addr);
928 printk(KERN_INFO "Found %s PCI host bridge at 0x%08lx. Firmware bus number: %d->%d\n",
929 disp_name, addr->address, hose->first_busno, hose->last_busno);
930 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
931 hose, hose->cfg_addr, hose->cfg_data);
933 /* Interpret the "ranges" property */
934 /* This also maps the I/O region and sets isa_io/mem_base */
935 pci_process_bridge_OF_ranges(hose, dev, primary);
937 /* Fixup "bus-range" OF property */
938 fixup_bus_range(dev);
944 pcibios_fixup_OF_interrupts(void)
946 struct pci_dev* dev = NULL;
949 * Open Firmware often doesn't initialize the
950 * PCI_INTERRUPT_LINE config register properly, so we
951 * should find the device node and apply the interrupt
952 * obtained from the OF device-tree
954 for_each_pci_dev(dev) {
955 struct device_node *node;
956 node = pci_device_to_OF_node(dev);
957 /* this is the node, see if it has interrupts */
958 if (node && node->n_intrs > 0)
959 dev->irq = node->intrs[0].line;
960 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
965 pmac_pcibios_fixup(void)
967 /* Fixup interrupts according to OF tree */
968 pcibios_fixup_OF_interrupts();
971 void __init pmac_find_bridges(void)
973 struct device_node *np, *root;
974 struct device_node *ht = NULL;
976 root = of_find_node_by_path("/");
978 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
981 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
982 if (np->name == NULL)
984 if (strcmp(np->name, "bandit") == 0
985 || strcmp(np->name, "chaos") == 0
986 || strcmp(np->name, "pci") == 0) {
987 if (add_bridge(np) == 0)
990 if (strcmp(np->name, "ht") == 0) {
997 /* Probe HT last as it relies on the agp resources to be already
1000 if (ht && add_bridge(ht) != 0)
1006 /* We are still having some issues with the Xserve G4, enabling
1007 * some offset between bus number and domains for now when we
1008 * assign all busses should help for now
1010 if (pci_assign_all_busses)
1011 pcibios_assign_bus_offset = 0x10;
1016 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
1018 struct device_node* node;
1022 node = pci_device_to_OF_node(dev);
1024 /* We don't want to enable USB controllers absent from the OF tree
1025 * (iBook second controller)
1027 if (dev->vendor == PCI_VENDOR_ID_APPLE
1028 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
1030 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1038 uninorth_child = node->parent &&
1039 device_is_compatible(node->parent, "uni-north");
1041 /* Firewire & GMAC were disabled after PCI probe, the driver is
1042 * claiming them, we must re-enable them now.
1044 if (uninorth_child && !strcmp(node->name, "firewire") &&
1045 (device_is_compatible(node, "pci106b,18") ||
1046 device_is_compatible(node, "pci106b,30") ||
1047 device_is_compatible(node, "pci11c1,5811"))) {
1048 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1049 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1052 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1053 device_is_compatible(node, "gmac")) {
1054 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1062 * Make sure PCI is correctly configured
1064 * We use old pci_bios versions of the function since, by
1065 * default, gmac is not powered up, and so will be absent
1066 * from the kernel initial PCI lookup.
1068 * Should be replaced by 2.4 new PCI mechanisms and really
1069 * register the device.
1071 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1072 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
1073 pci_write_config_word(dev, PCI_COMMAND, cmd);
1074 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1075 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1081 /* We power down some devices after they have been probed. They'll
1082 * be powered back on later on
1085 pmac_pcibios_after_init(void)
1087 struct device_node* nd;
1089 #ifdef CONFIG_BLK_DEV_IDE
1090 struct pci_dev *dev = NULL;
1092 /* OF fails to initialize IDE controllers on macs
1093 * (and maybe other machines)
1095 * Ideally, this should be moved to the IDE layer, but we need
1096 * to check specifically with Andre Hedrick how to do it cleanly
1097 * since the common IDE code seem to care about the fact that the
1098 * BIOS may have disabled a controller.
1102 for_each_pci_dev(dev) {
1103 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
1104 pci_enable_device(dev);
1106 #endif /* CONFIG_BLK_DEV_IDE */
1108 nd = find_devices("firewire");
1110 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
1111 device_is_compatible(nd, "pci106b,30") ||
1112 device_is_compatible(nd, "pci11c1,5811"))
1113 && device_is_compatible(nd->parent, "uni-north")) {
1114 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1115 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1119 nd = find_devices("ethernet");
1121 if (nd->parent && device_is_compatible(nd, "gmac")
1122 && device_is_compatible(nd->parent, "uni-north"))
1123 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1129 static void __init pmac_fixup_phb_resources(void)
1131 struct pci_controller *hose, *tmp;
1133 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1134 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
1135 hose->io_resource.start += offset;
1136 hose->io_resource.end += offset;
1137 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
1138 hose->global_number,
1139 hose->io_resource.start, hose->io_resource.end);
1143 void __init pmac_pci_init(void)
1145 struct device_node *np, *root;
1146 struct device_node *ht = NULL;
1148 /* Probe root PCI hosts, that is on U3 the AGP host and the
1149 * HyperTransport host. That one is actually "kept" around
1150 * and actually added last as it's resource management relies
1151 * on the AGP resources to have been setup first
1153 root = of_find_node_by_path("/");
1155 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
1158 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1159 if (np->name == NULL)
1161 if (strcmp(np->name, "pci") == 0) {
1162 if (add_bridge(np) == 0)
1165 if (strcmp(np->name, "ht") == 0) {
1172 /* Now setup the HyperTransport host if we found any
1174 if (ht && add_bridge(ht) != 0)
1177 /* Fixup the IO resources on our host bridges as the common code
1178 * does it only for childs of the host bridges
1180 pmac_fixup_phb_resources();
1182 /* Setup the linkage between OF nodes and PHBs */
1183 pci_devs_phb_init();
1185 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1186 * assume there is no P2P bridge on the AGP bus, which should be a
1187 * safe assumptions hopefully.
1190 struct device_node *np = u3_agp->arch_data;
1191 PCI_DN(np)->busno = 0xf0;
1192 for (np = np->child; np; np = np->sibling)
1193 PCI_DN(np)->busno = 0xf0;
1196 pmac_check_ht_link();
1198 /* Tell pci.c to not use the common resource allocation mecanism */
1207 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1209 if (_machine != _MACH_Pmac)
1212 * Fix the interrupt routing on the various cardbus bridges
1213 * used on powerbooks
1215 if (dev->vendor != PCI_VENDOR_ID_TI)
1217 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1218 dev->device == PCI_DEVICE_ID_TI_1131) {
1220 /* Enable PCI interrupt */
1221 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1222 pci_write_config_byte(dev, 0x91, val | 0x30);
1223 /* Disable ISA interrupt mode */
1224 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1225 pci_write_config_byte(dev, 0x92, val & ~0x06);
1227 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1228 dev->device == PCI_DEVICE_ID_TI_1211 ||
1229 dev->device == PCI_DEVICE_ID_TI_1410 ||
1230 dev->device == PCI_DEVICE_ID_TI_1510) {
1232 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1233 signal out the MFUNC0 pin */
1234 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1235 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1236 /* Disable ISA interrupt mode */
1237 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1238 pci_write_config_byte(dev, 0x92, val & ~0x06);
1242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1244 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1249 * On PowerMacs, we try to switch any PCI ATA controller to
1252 if (_machine != _MACH_Pmac)
1254 /* Some controllers don't have the class IDE */
1255 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1256 switch(dev->device) {
1257 case PCI_DEVICE_ID_PROMISE_20246:
1258 case PCI_DEVICE_ID_PROMISE_20262:
1259 case PCI_DEVICE_ID_PROMISE_20263:
1260 case PCI_DEVICE_ID_PROMISE_20265:
1261 case PCI_DEVICE_ID_PROMISE_20267:
1262 case PCI_DEVICE_ID_PROMISE_20268:
1263 case PCI_DEVICE_ID_PROMISE_20269:
1264 case PCI_DEVICE_ID_PROMISE_20270:
1265 case PCI_DEVICE_ID_PROMISE_20271:
1266 case PCI_DEVICE_ID_PROMISE_20275:
1267 case PCI_DEVICE_ID_PROMISE_20276:
1268 case PCI_DEVICE_ID_PROMISE_20277:
1271 /* Others, check PCI class */
1272 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1275 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1276 if ((progif & 5) != 5) {
1277 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1278 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1279 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1281 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1284 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1288 * Disable second function on K2-SATA, it's broken
1289 * and disable IO BARs on first one
1291 static void fixup_k2_sata(struct pci_dev* dev)
1296 if (PCI_FUNC(dev->devfn) > 0) {
1297 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1298 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1299 pci_write_config_word(dev, PCI_COMMAND, cmd);
1300 for (i = 0; i < 6; i++) {
1301 dev->resource[i].start = dev->resource[i].end = 0;
1302 dev->resource[i].flags = 0;
1303 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1306 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1307 cmd &= ~PCI_COMMAND_IO;
1308 pci_write_config_word(dev, PCI_COMMAND, cmd);
1309 for (i = 0; i < 5; i++) {
1310 dev->resource[i].start = dev->resource[i].end = 0;
1311 dev->resource[i].flags = 0;
1312 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);