2 * arch/powerpc/platforms/powermac/low_i2c.c
4 * Copyright (C) 2003-2005 Ben. Herrenschmidt (benh@kernel.crashing.org)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * The linux i2c layer isn't completely suitable for our needs for various
12 * reasons ranging from too late initialisation to semantics not perfectly
13 * matching some requirements of the apple platform functions etc...
15 * This file thus provides a simple low level unified i2c interface for
16 * powermac that covers the various types of i2c busses used in Apple machines.
17 * For now, keywest, PMU and SMU, though we could add Cuda, or other bit
18 * banging busses found on older chipstes in earlier machines if we ever need
21 * The drivers in this file are synchronous/blocking. In addition, the
22 * keywest one is fairly slow due to the use of msleep instead of interrupts
23 * as the interrupt is currently used by i2c-keywest. In the long run, we
24 * might want to get rid of those high-level interfaces to linux i2c layer
25 * either completely (converting all drivers) or replacing them all with a
26 * single stub driver on top of this one. Once done, the interrupt will be
27 * available for our use.
33 #include <linux/config.h>
34 #include <linux/types.h>
35 #include <linux/sched.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/adb.h>
39 #include <linux/pmu.h>
40 #include <linux/delay.h>
41 #include <linux/completion.h>
42 #include <asm/keylargo.h>
43 #include <asm/uninorth.h>
46 #include <asm/machdep.h>
48 #include <asm/pmac_low_i2c.h>
51 #define DBG(x...) do {\
52 printk(KERN_DEBUG "low_i2c:" x); \
59 #define DBG_LOW(x...) do {\
60 printk(KERN_DEBUG "low_i2c:" x); \
67 * A bus structure. Each bus in the system has such a structure associated.
71 struct list_head link;
72 struct device_node *controller;
73 struct device_node *busnode;
76 struct i2c_adapter *adapter;
78 int channel; /* some hosts have multiple */
79 int mode; /* current mode */
82 int polled; /* open mode */
85 int (*open)(struct pmac_i2c_bus *bus);
86 void (*close)(struct pmac_i2c_bus *bus);
87 int (*xfer)(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
88 u32 subaddr, u8 *data, int len);
91 static LIST_HEAD(pmac_i2c_busses);
94 * Keywest implementation
97 struct pmac_i2c_host_kw
99 struct semaphore mutex; /* Access mutex for use by
101 void __iomem *base; /* register base address */
102 int bsteps; /* register stepping */
103 int speed; /* speed */
106 /* Register indices */
120 #define KW_I2C_MODE_100KHZ 0x00
121 #define KW_I2C_MODE_50KHZ 0x01
122 #define KW_I2C_MODE_25KHZ 0x02
123 #define KW_I2C_MODE_DUMB 0x00
124 #define KW_I2C_MODE_STANDARD 0x04
125 #define KW_I2C_MODE_STANDARDSUB 0x08
126 #define KW_I2C_MODE_COMBINED 0x0C
127 #define KW_I2C_MODE_MODE_MASK 0x0C
128 #define KW_I2C_MODE_CHAN_MASK 0xF0
130 /* Control register */
131 #define KW_I2C_CTL_AAK 0x01
132 #define KW_I2C_CTL_XADDR 0x02
133 #define KW_I2C_CTL_STOP 0x04
134 #define KW_I2C_CTL_START 0x08
136 /* Status register */
137 #define KW_I2C_STAT_BUSY 0x01
138 #define KW_I2C_STAT_LAST_AAK 0x02
139 #define KW_I2C_STAT_LAST_RW 0x04
140 #define KW_I2C_STAT_SDA 0x08
141 #define KW_I2C_STAT_SCL 0x10
143 /* IER & ISR registers */
144 #define KW_I2C_IRQ_DATA 0x01
145 #define KW_I2C_IRQ_ADDR 0x02
146 #define KW_I2C_IRQ_STOP 0x04
147 #define KW_I2C_IRQ_START 0x08
148 #define KW_I2C_IRQ_MASK 0x0F
150 /* State machine states */
160 #define WRONG_STATE(name) do {\
161 printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
162 name, __kw_state_names[state], isr); \
165 static const char *__kw_state_names[] = {
174 static inline u8 __kw_read_reg(struct pmac_i2c_bus *bus, reg_t reg)
176 struct pmac_i2c_host_kw *host = bus->hostdata;
177 return readb(host->base + (((unsigned int)reg) << host->bsteps));
180 static inline void __kw_write_reg(struct pmac_i2c_bus *bus, reg_t reg, u8 val)
182 struct pmac_i2c_host_kw *host = bus->hostdata;
183 writeb(val, host->base + (((unsigned)reg) << host->bsteps));
184 (void)__kw_read_reg(bus, reg_subaddr);
187 #define kw_write_reg(reg, val) __kw_write_reg(bus, reg, val)
188 #define kw_read_reg(reg) __kw_read_reg(bus, reg)
190 static u8 kw_i2c_wait_interrupt(struct pmac_i2c_bus* bus)
195 for (i = 0; i < 1000; i++) {
196 isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
200 /* This code is used with the timebase frozen, we cannot rely
201 * on udelay nor schedule when in polled mode !
202 * For now, just use a bogus loop....
205 for (j = 1; j < 1000000; j++)
213 static int kw_i2c_handle_interrupt(struct pmac_i2c_bus *bus, int state, int rw,
214 int *rc, u8 **data, int *len, u8 isr)
218 DBG_LOW("kw_handle_interrupt(%s, isr: %x)\n",
219 __kw_state_names[state], isr);
222 if (state != state_stop) {
223 DBG_LOW("KW: Timeout !\n");
227 if (state == state_stop) {
228 ack = kw_read_reg(reg_status);
229 if (!(ack & KW_I2C_STAT_BUSY)) {
231 kw_write_reg(reg_ier, 0x00);
237 if (isr & KW_I2C_IRQ_ADDR) {
238 ack = kw_read_reg(reg_status);
239 if (state != state_addr) {
240 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
241 WRONG_STATE("KW_I2C_IRQ_ADDR");
245 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
247 DBG_LOW("KW: NAK on address\n");
253 kw_write_reg(reg_control,
257 kw_write_reg(reg_data, **data);
261 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
264 if (isr & KW_I2C_IRQ_DATA) {
265 if (state == state_read) {
266 **data = kw_read_reg(reg_data);
268 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
271 else if ((*len) == 1)
272 kw_write_reg(reg_control, 0);
273 } else if (state == state_write) {
274 ack = kw_read_reg(reg_status);
275 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
276 DBG_LOW("KW: nack on data write\n");
280 kw_write_reg(reg_data, **data);
283 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
287 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
289 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
290 WRONG_STATE("KW_I2C_IRQ_DATA");
291 if (state != state_stop) {
298 if (isr & KW_I2C_IRQ_STOP) {
299 kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
300 if (state != state_stop) {
301 WRONG_STATE("KW_I2C_IRQ_STOP");
307 if (isr & KW_I2C_IRQ_START)
308 kw_write_reg(reg_isr, KW_I2C_IRQ_START);
313 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
317 static int kw_i2c_open(struct pmac_i2c_bus *bus)
319 struct pmac_i2c_host_kw *host = bus->hostdata;
324 static void kw_i2c_close(struct pmac_i2c_bus *bus)
326 struct pmac_i2c_host_kw *host = bus->hostdata;
330 static int kw_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
331 u32 subaddr, u8 *data, int len)
333 struct pmac_i2c_host_kw *host = bus->hostdata;
334 u8 mode_reg = host->speed;
335 int state = state_addr;
338 /* Setup mode & subaddress if any */
340 case pmac_i2c_mode_dumb:
342 case pmac_i2c_mode_std:
343 mode_reg |= KW_I2C_MODE_STANDARD;
347 case pmac_i2c_mode_stdsub:
348 mode_reg |= KW_I2C_MODE_STANDARDSUB;
352 case pmac_i2c_mode_combined:
353 mode_reg |= KW_I2C_MODE_COMBINED;
359 /* Setup channel & clear pending irqs */
360 kw_write_reg(reg_isr, kw_read_reg(reg_isr));
361 kw_write_reg(reg_mode, mode_reg | (bus->channel << 4));
362 kw_write_reg(reg_status, 0);
364 /* Set up address and r/w bit, strip possible stale bus number from
367 kw_write_reg(reg_addr, addrdir & 0xff);
369 /* Set up the sub address */
370 if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
371 || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
372 kw_write_reg(reg_subaddr, subaddr);
374 /* Start sending address & disable interrupt*/
375 kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/);
376 kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
378 /* State machine, to turn into an interrupt handler in the future */
379 while(state != state_idle) {
380 u8 isr = kw_i2c_wait_interrupt(bus);
381 state = kw_i2c_handle_interrupt(bus, state, addrdir & 1, &rc,
388 static struct pmac_i2c_host_kw *__init kw_i2c_host_init(struct device_node *np)
390 struct pmac_i2c_host_kw *host;
391 u32 *psteps, *prate, *addrp, steps;
393 host = kzalloc(sizeof(struct pmac_i2c_host_kw), GFP_KERNEL);
395 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
400 /* Apple is kind enough to provide a valid AAPL,address property
401 * on all i2c keywest nodes so far ... we would have to fallback
402 * to macio parsing if that wasn't the case
404 addrp = (u32 *)get_property(np, "AAPL,address", NULL);
406 printk(KERN_ERR "low_i2c: Can't find address for %s\n",
411 init_MUTEX(&host->mutex);
412 psteps = (u32 *)get_property(np, "AAPL,address-step", NULL);
413 steps = psteps ? (*psteps) : 0x10;
414 for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
416 /* Select interface rate */
417 host->speed = KW_I2C_MODE_25KHZ;
418 prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL);
419 if (prate) switch(*prate) {
421 host->speed = KW_I2C_MODE_100KHZ;
424 host->speed = KW_I2C_MODE_50KHZ;
427 host->speed = KW_I2C_MODE_25KHZ;
431 printk(KERN_INFO "KeyWest i2c @0x%08x %s\n", *addrp, np->full_name);
432 host->base = ioremap((*addrp), 0x1000);
438 static void __init kw_i2c_add(struct pmac_i2c_host_kw *host,
439 struct device_node *controller,
440 struct device_node *busnode,
443 struct pmac_i2c_bus *bus;
445 bus = kzalloc(sizeof(struct pmac_i2c_bus), GFP_KERNEL);
449 bus->controller = of_node_get(controller);
450 bus->busnode = of_node_get(busnode);
451 bus->type = pmac_i2c_bus_keywest;
452 bus->hostdata = host;
453 bus->channel = channel;
454 bus->mode = pmac_i2c_mode_std;
455 bus->open = kw_i2c_open;
456 bus->close = kw_i2c_close;
457 bus->xfer = kw_i2c_xfer;
458 init_MUTEX(&bus->sem);
459 if (controller == busnode)
460 bus->flags = pmac_i2c_multibus;
461 list_add(&bus->link, &pmac_i2c_busses);
463 printk(KERN_INFO " channel %d bus %s\n", channel,
464 (controller == busnode) ? "<multibus>" : busnode->full_name);
467 static void __init kw_i2c_probe(void)
469 struct device_node *np, *child, *parent;
471 /* Probe keywest-i2c busses */
473 (np = of_find_compatible_node(np, "i2c","keywest-i2c")) != NULL;){
474 struct pmac_i2c_host_kw *host;
475 int multibus, chans, i;
477 /* Found one, init a host structure */
478 host = kw_i2c_host_init(np);
482 /* Now check if we have a multibus setup (old style) or if we
483 * have proper bus nodes. Note that the "new" way (proper bus
484 * nodes) might cause us to not create some busses that are
485 * kept hidden in the device-tree. In the future, we might
486 * want to work around that by creating busses without a node
489 child = of_get_next_child(np, NULL);
490 multibus = !child || strcmp(child->name, "i2c-bus");
493 /* For a multibus setup, we get the bus count based on the
497 parent = of_get_parent(np);
500 chans = parent->name[0] == 'u' ? 2 : 1;
501 for (i = 0; i < chans; i++)
502 kw_i2c_add(host, np, np, i);
505 (child = of_get_next_child(np, child)) != NULL;) {
507 (u32 *)get_property(child, "reg", NULL);
510 kw_i2c_add(host, np, child, *reg);
523 #ifdef CONFIG_ADB_PMU
526 * i2c command block to the PMU
539 static void pmu_i2c_complete(struct adb_request *req)
544 static int pmu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
545 u32 subaddr, u8 *data, int len)
547 struct adb_request *req = bus->hostdata;
548 struct pmu_i2c_hdr *hdr = (struct pmu_i2c_hdr *)&req->data[1];
549 struct completion comp;
550 int read = addrdir & 1;
554 /* For now, limit ourselves to 16 bytes transfers */
558 init_completion(&comp);
560 for (retry = 0; retry < 16; retry++) {
561 memset(req, 0, sizeof(struct adb_request));
562 hdr->bus = bus->channel;
566 case pmac_i2c_mode_std:
569 hdr->address = addrdir;
570 hdr->mode = PMU_I2C_MODE_SIMPLE;
572 case pmac_i2c_mode_stdsub:
573 case pmac_i2c_mode_combined:
576 hdr->address = addrdir & 0xfe;
577 hdr->comb_addr = addrdir;
578 hdr->sub_addr = subaddr;
579 if (bus->mode == pmac_i2c_mode_stdsub)
580 hdr->mode = PMU_I2C_MODE_STDSUB;
582 hdr->mode = PMU_I2C_MODE_COMBINED;
588 INIT_COMPLETION(comp);
589 req->data[0] = PMU_I2C_CMD;
590 req->reply[0] = 0xff;
591 req->nbytes = sizeof(struct pmu_i2c_hdr) + 1;
592 req->done = pmu_i2c_complete;
595 memcpy(hdr->data, data, len);
598 rc = pmu_queue_request(req);
601 wait_for_completion(&comp);
602 if (req->reply[0] == PMU_I2C_STATUS_OK)
606 if (req->reply[0] != PMU_I2C_STATUS_OK)
609 for (retry = 0; retry < 16; retry++) {
610 memset(req, 0, sizeof(struct adb_request));
612 /* I know that looks like a lot, slow as hell, but darwin
613 * does it so let's be on the safe side for now
617 hdr->bus = PMU_I2C_BUS_STATUS;
619 INIT_COMPLETION(comp);
620 req->data[0] = PMU_I2C_CMD;
621 req->reply[0] = 0xff;
623 req->done = pmu_i2c_complete;
625 rc = pmu_queue_request(req);
628 wait_for_completion(&comp);
630 if (req->reply[0] == PMU_I2C_STATUS_OK && !read)
632 if (req->reply[0] == PMU_I2C_STATUS_DATAREAD && read) {
633 int rlen = req->reply_len - 1;
636 printk(KERN_WARNING "low_i2c: PMU returned %d"
637 " bytes, expected %d !\n", rlen, len);
640 memcpy(data, &req->reply[1], len);
647 static void __init pmu_i2c_probe(void)
649 struct pmac_i2c_bus *bus;
650 struct device_node *busnode;
656 /* There might or might not be a "pmu-i2c" node, we use that
657 * or via-pmu itself, whatever we find. I haven't seen a machine
658 * with separate bus nodes, so we assume a multibus setup
660 busnode = of_find_node_by_name(NULL, "pmu-i2c");
662 busnode = of_find_node_by_name(NULL, "via-pmu");
666 printk(KERN_INFO "PMU i2c %s\n", busnode->full_name);
669 * We add bus 1 and 2 only for now, bus 0 is "special"
671 for (channel = 1; channel <= 2; channel++) {
672 sz = sizeof(struct pmac_i2c_bus) + sizeof(struct adb_request);
673 bus = kzalloc(sz, GFP_KERNEL);
677 bus->controller = busnode;
678 bus->busnode = busnode;
679 bus->type = pmac_i2c_bus_pmu;
680 bus->channel = channel;
681 bus->mode = pmac_i2c_mode_std;
682 bus->hostdata = bus + 1;
683 bus->xfer = pmu_i2c_xfer;
684 init_MUTEX(&bus->sem);
685 bus->flags = pmac_i2c_multibus;
686 list_add(&bus->link, &pmac_i2c_busses);
688 printk(KERN_INFO " channel %d bus <multibus>\n", channel);
692 #endif /* CONFIG_ADB_PMU */
701 #ifdef CONFIG_PMAC_SMU
703 static void smu_i2c_complete(struct smu_i2c_cmd *cmd, void *misc)
708 static int smu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
709 u32 subaddr, u8 *data, int len)
711 struct smu_i2c_cmd *cmd = bus->hostdata;
712 struct completion comp;
713 int read = addrdir & 1;
716 memset(cmd, 0, sizeof(struct smu_i2c_cmd));
717 cmd->info.bus = bus->channel;
718 cmd->info.devaddr = addrdir;
719 cmd->info.datalen = len;
722 case pmac_i2c_mode_std:
725 cmd->info.type = SMU_I2C_TRANSFER_SIMPLE;
727 case pmac_i2c_mode_stdsub:
728 case pmac_i2c_mode_combined:
729 if (subsize > 3 || subsize < 1)
731 cmd->info.sublen = subsize;
732 /* that's big-endian only but heh ! */
733 memcpy(&cmd->info.subaddr, ((char *)&subaddr) + (4 - subsize),
735 if (bus->mode == pmac_i2c_mode_stdsub)
736 cmd->info.type = SMU_I2C_TRANSFER_STDSUB;
738 cmd->info.type = SMU_I2C_TRANSFER_COMBINED;
744 memcpy(cmd->info.data, data, len);
746 init_completion(&comp);
747 cmd->done = smu_i2c_complete;
749 rc = smu_queue_i2c(cmd);
752 wait_for_completion(&comp);
756 memcpy(data, cmd->info.data, len);
757 return rc < 0 ? rc : 0;
760 static void __init smu_i2c_probe(void)
762 struct device_node *controller, *busnode;
763 struct pmac_i2c_bus *bus;
770 controller = of_find_node_by_name(NULL, "smu_i2c_control");
771 if (controller == NULL)
772 controller = of_find_node_by_name(NULL, "smu");
773 if (controller == NULL)
776 printk(KERN_INFO "SMU i2c %s\n", controller->full_name);
778 /* Look for childs, note that they might not be of the right
779 * type as older device trees mix i2c busses and other thigns
783 (busnode = of_get_next_child(controller, busnode)) != NULL;) {
784 if (strcmp(busnode->type, "i2c") &&
785 strcmp(busnode->type, "i2c-bus"))
787 reg = (u32 *)get_property(busnode, "reg", NULL);
791 sz = sizeof(struct pmac_i2c_bus) + sizeof(struct smu_i2c_cmd);
792 bus = kzalloc(sz, GFP_KERNEL);
796 bus->controller = controller;
797 bus->busnode = of_node_get(busnode);
798 bus->type = pmac_i2c_bus_smu;
800 bus->mode = pmac_i2c_mode_std;
801 bus->hostdata = bus + 1;
802 bus->xfer = smu_i2c_xfer;
803 init_MUTEX(&bus->sem);
805 list_add(&bus->link, &pmac_i2c_busses);
807 printk(KERN_INFO " channel %x bus %s\n",
808 bus->channel, busnode->full_name);
812 #endif /* CONFIG_PMAC_SMU */
821 struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node)
823 struct device_node *p = of_node_get(node);
824 struct device_node *prev = NULL;
825 struct pmac_i2c_bus *bus;
828 list_for_each_entry(bus, &pmac_i2c_busses, link) {
829 if (p == bus->busnode) {
830 if (prev && bus->flags & pmac_i2c_multibus) {
832 reg = (u32 *)get_property(prev, "reg",
836 if (((*reg) >> 8) != bus->channel)
846 p = of_get_parent(p);
850 EXPORT_SYMBOL_GPL(pmac_i2c_find_bus);
852 u8 pmac_i2c_get_dev_addr(struct device_node *device)
854 u32 *reg = (u32 *)get_property(device, "reg", NULL);
859 return (*reg) & 0xff;
861 EXPORT_SYMBOL_GPL(pmac_i2c_get_dev_addr);
863 struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus)
865 return bus->controller;
867 EXPORT_SYMBOL_GPL(pmac_i2c_get_controller);
869 struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus)
873 EXPORT_SYMBOL_GPL(pmac_i2c_get_bus_node);
875 int pmac_i2c_get_type(struct pmac_i2c_bus *bus)
879 EXPORT_SYMBOL_GPL(pmac_i2c_get_type);
881 int pmac_i2c_get_flags(struct pmac_i2c_bus *bus)
885 EXPORT_SYMBOL_GPL(pmac_i2c_get_flags);
887 void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
888 struct i2c_adapter *adapter)
890 WARN_ON(bus->adapter != NULL);
891 bus->adapter = adapter;
893 EXPORT_SYMBOL_GPL(pmac_i2c_attach_adapter);
895 void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
896 struct i2c_adapter *adapter)
898 WARN_ON(bus->adapter != adapter);
901 EXPORT_SYMBOL_GPL(pmac_i2c_detach_adapter);
903 struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus)
907 EXPORT_SYMBOL_GPL(pmac_i2c_get_adapter);
909 extern int pmac_i2c_match_adapter(struct device_node *dev,
910 struct i2c_adapter *adapter)
912 struct pmac_i2c_bus *bus = pmac_i2c_find_bus(dev);
916 return (bus->adapter == adapter);
918 EXPORT_SYMBOL_GPL(pmac_i2c_match_adapter);
920 int pmac_low_i2c_lock(struct device_node *np)
922 struct pmac_i2c_bus *bus, *found = NULL;
924 list_for_each_entry(bus, &pmac_i2c_busses, link) {
925 if (np == bus->controller) {
932 return pmac_i2c_open(bus, 0);
934 EXPORT_SYMBOL_GPL(pmac_low_i2c_lock);
936 int pmac_low_i2c_unlock(struct device_node *np)
938 struct pmac_i2c_bus *bus, *found = NULL;
940 list_for_each_entry(bus, &pmac_i2c_busses, link) {
941 if (np == bus->controller) {
951 EXPORT_SYMBOL_GPL(pmac_low_i2c_unlock);
954 int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled)
959 bus->polled = polled;
961 bus->mode = pmac_i2c_mode_std;
962 if (bus->open && (rc = bus->open(bus)) != 0) {
969 EXPORT_SYMBOL_GPL(pmac_i2c_open);
971 void pmac_i2c_close(struct pmac_i2c_bus *bus)
973 WARN_ON(!bus->opened);
979 EXPORT_SYMBOL_GPL(pmac_i2c_close);
981 int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode)
983 WARN_ON(!bus->opened);
985 /* Report me if you see the error below as there might be a new
986 * "combined4" mode that I need to implement for the SMU bus
988 if (mode < pmac_i2c_mode_dumb || mode > pmac_i2c_mode_combined) {
989 printk(KERN_ERR "low_i2c: Invalid mode %d requested on"
990 " bus %s !\n", mode, bus->busnode->full_name);
997 EXPORT_SYMBOL_GPL(pmac_i2c_setmode);
999 int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
1000 u32 subaddr, u8 *data, int len)
1004 WARN_ON(!bus->opened);
1006 DBG("xfer() chan=%d, addrdir=0x%x, mode=%d, subsize=%d, subaddr=0x%x,"
1007 " %d bytes, bus %s\n", bus->channel, addrdir, bus->mode, subsize,
1008 subaddr, len, bus->busnode->full_name);
1010 rc = bus->xfer(bus, addrdir, subsize, subaddr, data, len);
1014 DBG("xfer error %d\n", rc);
1018 EXPORT_SYMBOL_GPL(pmac_i2c_xfer);
1021 * Initialize us: probe all i2c busses on the machine and instantiate
1024 /* This is non-static as it might be called early by smp code */
1025 int __init pmac_i2c_init(void)
1027 static int i2c_inited;
1033 /* Probe keywest-i2c busses */
1036 #ifdef CONFIG_ADB_PMU
1040 #ifdef CONFIG_PMAC_SMU
1046 arch_initcall(pmac_i2c_init);