2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
4 * iSeries specific routines for PCI.
6 * Based on code from pci.c and iSeries_pci.c 32bit
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/ide.h>
28 #include <linux/pci.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/ppcdebug.h>
36 #include <asm/iommu.h>
38 #include <asm/iSeries/HvCallPci.h>
39 #include <asm/iSeries/HvCallXm.h>
40 #include <asm/iSeries/iSeries_pci.h>
41 #include <asm/iSeries/mf.h>
43 #include <asm/ppc-pci.h>
47 extern unsigned long io_page_mask;
50 * Forward declares of prototypes.
52 static struct device_node *find_Device_Node(int bus, int devfn);
53 static void scan_PHB_slots(struct pci_controller *Phb);
54 static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
55 static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
57 LIST_HEAD(iSeries_Global_Device_List);
59 static int DeviceCount;
61 /* Counters and control flags. */
62 static long Pci_Io_Read_Count;
63 static long Pci_Io_Write_Count;
65 static long Pci_Cfg_Read_Count;
66 static long Pci_Cfg_Write_Count;
68 static long Pci_Error_Count;
70 static int Pci_Retry_Max = 3; /* Only retry 3 times */
71 static int Pci_Error_Flag = 1; /* Set Retry Error on. */
73 static struct pci_ops iSeries_pci_ops;
77 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
79 #define IOMM_TABLE_MAX_ENTRIES 1024
80 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
81 #define BASE_IO_MEMORY 0xE000000000000000UL
83 static unsigned long max_io_memory = 0xE000000000000000UL;
84 static long current_iomm_table_entry;
89 static struct device_node **iomm_table;
90 static u8 *iobar_table;
93 * Static and Global variables
95 static char *pci_io_text = "iSeries PCI I/O";
96 static DEFINE_SPINLOCK(iomm_table_lock);
99 * iomm_table_initialize
101 * Allocates and initalizes the Address Translation Table and Bar
102 * Tables to get them ready for use. Must be called before any
103 * I/O space is handed out to the device BARs.
105 static void iomm_table_initialize(void)
107 spin_lock(&iomm_table_lock);
108 iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
110 iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
112 spin_unlock(&iomm_table_lock);
113 if ((iomm_table == NULL) || (iobar_table == NULL))
114 panic("PCI: I/O tables allocation failed.\n");
118 * iomm_table_allocate_entry
120 * Adds pci_dev entry in address translation table
122 * - Allocates the number of entries required in table base on BAR
124 * - Allocates starting at BASE_IO_MEMORY and increases.
125 * - The size is round up to be a multiple of entry size.
126 * - CurrentIndex is incremented to keep track of the last entry.
127 * - Builds the resource entry for allocated BARs.
129 static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
131 struct resource *bar_res = &dev->resource[bar_num];
132 long bar_size = pci_resource_len(dev, bar_num);
135 * No space to allocate, quick exit, skip Allocation.
140 * Set Resource values.
142 spin_lock(&iomm_table_lock);
143 bar_res->name = pci_io_text;
145 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
146 bar_res->start += BASE_IO_MEMORY;
147 bar_res->end = bar_res->start + bar_size - 1;
149 * Allocate the number of table entries needed for BAR.
151 while (bar_size > 0 ) {
152 iomm_table[current_iomm_table_entry] = dev->sysdata;
153 iobar_table[current_iomm_table_entry] = bar_num;
154 bar_size -= IOMM_TABLE_ENTRY_SIZE;
155 ++current_iomm_table_entry;
157 max_io_memory = BASE_IO_MEMORY +
158 (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
159 spin_unlock(&iomm_table_lock);
163 * allocate_device_bars
165 * - Allocates ALL pci_dev BAR's and updates the resources with the
166 * BAR value. BARS with zero length will have the resources
167 * The HvCallPci_getBarParms is used to get the size of the BAR
168 * space. It calls iomm_table_allocate_entry to allocate
170 * - Loops through The Bar resources(0 - 5) including the ROM
173 static void allocate_device_bars(struct pci_dev *dev)
175 struct resource *bar_res;
178 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
179 bar_res = &dev->resource[bar_num];
180 iomm_table_allocate_entry(dev, bar_num);
185 * Log error information to system console.
186 * Filter out the device not there errors.
187 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
188 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
189 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
191 static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
192 int AgentId, int HvRc)
196 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
197 Error_Text, Bus, SubBus, AgentId, HvRc);
201 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
203 static struct device_node *build_device_node(HvBusNumber Bus,
204 HvSubBusNumber SubBus, int AgentId, int Function)
206 struct device_node *node;
209 PPCDBG(PPCDBG_BUSWALK,
210 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
211 Bus, SubBus, AgentId, Function);
213 node = kmalloc(sizeof(struct device_node), GFP_KERNEL);
216 memset(node, 0, sizeof(struct device_node));
217 pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
223 list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
225 pdn->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
227 pdn->DsaAddr.DsaAddr = 0;
228 pdn->DsaAddr.Dsa.busNumber = Bus;
229 pdn->DsaAddr.Dsa.subBusNumber = SubBus;
230 pdn->DsaAddr.Dsa.deviceId = 0x10;
231 pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
236 * unsigned long __init find_and_init_phbs(void)
239 * This function checks for all possible system PCI host bridges that connect
240 * PCI buses. The system hypervisor is queried as to the guest partition
241 * ownership status. A pci_controller is built for any bus which is partially
242 * owned or fully owned by this guest partition.
244 unsigned long __init find_and_init_phbs(void)
246 struct pci_controller *phb;
249 PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
251 /* Check all possible buses. */
252 for (bus = 0; bus < 256; bus++) {
253 int ret = HvCallXm_testBus(bus);
255 printk("bus %d appears to exist\n", bus);
257 phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
260 pci_setup_pci_controller(phb);
262 phb->pci_mem_offset = phb->local_number = bus;
263 phb->first_busno = bus;
264 phb->last_busno = bus;
265 phb->ops = &iSeries_pci_ops;
267 PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
270 /* Find and connect the devices. */
274 * Check for Unexpected Return code, a clue that something
277 else if (ret != 0x0301)
278 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
285 * iSeries_pcibios_init
287 * Chance to initialize and structures or variable before PCI Bus walk.
289 void iSeries_pcibios_init(void)
291 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
292 iomm_table_initialize();
293 find_and_init_phbs();
295 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
299 * iSeries_pci_final_fixup(void)
301 void __init iSeries_pci_final_fixup(void)
303 struct pci_dev *pdev = NULL;
304 struct device_node *node;
307 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
309 /* Fix up at the device node and pci_dev relationship */
310 mf_display_src(0xC9000100);
312 printk("pcibios_final_fixup\n");
313 for_each_pci_dev(pdev) {
314 node = find_Device_Node(pdev->bus->number, pdev->devfn);
315 printk("pci dev %p (%x.%x), node %p\n", pdev,
316 pdev->bus->number, pdev->devfn, node);
320 pdev->sysdata = (void *)node;
321 PCI_DN(node)->pcidev = pdev;
322 PPCDBG(PPCDBG_BUSWALK,
323 "pdev 0x%p <==> DevNode 0x%p\n",
325 allocate_device_bars(pdev);
326 iSeries_Device_Information(pdev, DeviceCount);
327 iommu_devnode_init_iSeries(node);
329 printk("PCI: Device Tree not found for 0x%016lX\n",
330 (unsigned long)pdev);
331 pdev->irq = PCI_DN(node)->Irq;
333 iSeries_activate_IRQs();
334 mf_display_src(0xC9000200);
337 void pcibios_fixup_bus(struct pci_bus *PciBus)
339 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
343 void pcibios_fixup_resources(struct pci_dev *pdev)
345 PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
349 * Loop through each node function to find usable EADs bridges.
351 static void scan_PHB_slots(struct pci_controller *Phb)
353 struct HvCallPci_DeviceInfo *DevInfo;
354 HvBusNumber bus = Phb->local_number; /* System Bus */
355 const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
358 const int MaxAgents = 8;
360 DevInfo = (struct HvCallPci_DeviceInfo*)
361 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
366 * Probe for EADs Bridges
368 for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
369 HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
370 ISERIES_HV_ADDR(DevInfo),
371 sizeof(struct HvCallPci_DeviceInfo));
373 if (DevInfo->deviceType == HvCallPci_NodeDevice)
374 scan_EADS_bridge(bus, SubBus, IdSel);
376 printk("PCI: Invalid System Configuration(0x%02X)"
377 " for bus 0x%02x id 0x%02x.\n",
378 DevInfo->deviceType, bus, IdSel);
381 pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
386 static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
389 struct HvCallPci_BridgeInfo *BridgeInfo;
394 BridgeInfo = (struct HvCallPci_BridgeInfo *)
395 kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
396 if (BridgeInfo == NULL)
399 /* Note: hvSubBus and irq is always be 0 at this level! */
400 for (Function = 0; Function < 8; ++Function) {
401 AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
402 HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
404 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
405 bus, IdSel, Function, AgentId);
406 /* Connect EADs: 0x18.00.12 = 0x00 */
407 PPCDBG(PPCDBG_BUSWALK,
408 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
409 bus, SubBus, AgentId);
410 HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
411 ISERIES_HV_ADDR(BridgeInfo),
412 sizeof(struct HvCallPci_BridgeInfo));
414 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
415 BridgeInfo->busUnitInfo.deviceType,
416 BridgeInfo->subBusNumber,
417 BridgeInfo->maxAgents,
418 BridgeInfo->maxSubBusNumber,
419 BridgeInfo->logicalSlotNumber);
420 PPCDBG(PPCDBG_BUSWALK,
421 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
422 BridgeInfo->busUnitInfo.deviceType,
423 BridgeInfo->subBusNumber,
424 BridgeInfo->maxAgents,
425 BridgeInfo->maxSubBusNumber,
426 BridgeInfo->logicalSlotNumber);
428 if (BridgeInfo->busUnitInfo.deviceType ==
429 HvCallPci_BridgeDevice) {
430 /* Scan_Bridge_Slot...: 0x18.00.12 */
431 scan_bridge_slot(bus, BridgeInfo);
433 printk("PCI: Invalid Bridge Configuration(0x%02X)",
434 BridgeInfo->busUnitInfo.deviceType);
436 } else if (HvRc != 0x000B)
437 pci_Log_Error("EADs Connect",
438 bus, SubBus, AgentId, HvRc);
444 * This assumes that the node slot is always on the primary bus!
446 static int scan_bridge_slot(HvBusNumber Bus,
447 struct HvCallPci_BridgeInfo *BridgeInfo)
449 struct device_node *node;
450 HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
454 int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
455 int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
456 HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
458 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
459 Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
460 PPCDBG(PPCDBG_BUSWALK,
461 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
462 Bus, 0, EADsIdSel, Irq);
465 * Connect all functions of any device found.
467 for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
468 for (Function = 0; Function < 8; ++Function) {
469 HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
470 HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
473 pci_Log_Error("Connect Bus Unit",
474 Bus, SubBus, AgentId, HvRc);
478 HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
479 PCI_VENDOR_ID, &VendorId);
481 pci_Log_Error("Read Vendor",
482 Bus, SubBus, AgentId, HvRc);
485 printk("read vendor ID: %x\n", VendorId);
487 /* FoundDevice: 0x18.28.10 = 0x12AE */
488 PPCDBG(PPCDBG_BUSWALK,
489 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
490 Bus, SubBus, AgentId, VendorId, Irq);
491 HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
492 PCI_INTERRUPT_LINE, Irq);
494 pci_Log_Error("PciCfgStore Irq Failed!",
495 Bus, SubBus, AgentId, HvRc);
498 node = build_device_node(Bus, SubBus, EADsIdSel, Function);
499 PCI_DN(node)->Irq = Irq;
500 PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber;
502 } /* for (Function = 0; Function < 8; ++Function) */
503 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
508 * I/0 Memory copy MUST use mmio commands on iSeries
509 * To do; For performance, include the hv call directly
511 void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
514 long NumberOfBytes = Count;
516 while (NumberOfBytes > 0) {
517 iSeries_Write_Byte(ByteValue, dest++);
521 EXPORT_SYMBOL(iSeries_memset_io);
523 void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
526 long NumberOfBytes = count;
528 while (NumberOfBytes > 0) {
529 iSeries_Write_Byte(*src++, dest++);
533 EXPORT_SYMBOL(iSeries_memcpy_toio);
535 void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
538 long NumberOfBytes = count;
540 while (NumberOfBytes > 0) {
541 *dst++ = iSeries_Read_Byte(src++);
545 EXPORT_SYMBOL(iSeries_memcpy_fromio);
548 * Look down the chain to find the matching Device Device
550 static struct device_node *find_Device_Node(int bus, int devfn)
552 struct list_head *pos;
554 list_for_each(pos, &iSeries_Global_Device_List) {
555 struct device_node *node =
556 list_entry(pos, struct device_node, Device_List);
558 if ((bus == ISERIES_BUS(node)) &&
559 (devfn == PCI_DN(node)->devfn))
567 * Returns the device node for the passed pci_dev
568 * Sanity Check Node PciDev to passed pci_dev
569 * If none is found, returns a NULL which the client must handle.
571 static struct device_node *get_Device_Node(struct pci_dev *pdev)
573 struct device_node *node;
575 node = pdev->sysdata;
576 if (node == NULL || PCI_DN(node)->pcidev != pdev)
577 node = find_Device_Node(pdev->bus->number, pdev->devfn);
583 * Config space read and write functions.
584 * For now at least, we look for the device node for the bus and devfn
585 * that we are asked to access. It may be possible to translate the devfn
586 * to a subbus and deviceid more directly.
588 static u64 hv_cfg_read_func[4] = {
589 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
590 HvCallPciConfigLoad32, HvCallPciConfigLoad32
593 static u64 hv_cfg_write_func[4] = {
594 HvCallPciConfigStore8, HvCallPciConfigStore16,
595 HvCallPciConfigStore32, HvCallPciConfigStore32
599 * Read PCI config space
601 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
602 int offset, int size, u32 *val)
604 struct device_node *node = find_Device_Node(bus->number, devfn);
606 struct HvCallPci_LoadReturn ret;
609 return PCIBIOS_DEVICE_NOT_FOUND;
612 return PCIBIOS_BAD_REGISTER_NUMBER;
615 fn = hv_cfg_read_func[(size - 1) & 3];
616 HvCall3Ret16(fn, &ret, PCI_DN(node)->DsaAddr.DsaAddr, offset, 0);
620 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
628 * Write PCI config space
631 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
632 int offset, int size, u32 val)
634 struct device_node *node = find_Device_Node(bus->number, devfn);
639 return PCIBIOS_DEVICE_NOT_FOUND;
641 return PCIBIOS_BAD_REGISTER_NUMBER;
643 fn = hv_cfg_write_func[(size - 1) & 3];
644 ret = HvCall4(fn, PCI_DN(node)->DsaAddr.DsaAddr, offset, val, 0);
647 return PCIBIOS_DEVICE_NOT_FOUND;
652 static struct pci_ops iSeries_pci_ops = {
653 .read = iSeries_pci_read_config,
654 .write = iSeries_pci_write_config
659 * -> On Failure, print and log information.
660 * Increment Retry Count, if exceeds max, panic partition.
662 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
663 * PCI: Device 23.90 ReadL Retry( 1)
664 * PCI: Device 23.90 ReadL Retry Successful(1)
666 static int CheckReturnCode(char *TextHdr, struct device_node *DevNode,
670 struct pci_dn *pdn = PCI_DN(DevNode);
674 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
675 TextHdr, pdn->DsaAddr.Dsa.busNumber, pdn->devfn,
678 * Bump the retry and check for retry count exceeded.
679 * If, Exceeded, panic the system.
681 if (((*retry) > Pci_Retry_Max) &&
682 (Pci_Error_Flag > 0)) {
683 mf_display_src(0xB6000103);
685 panic("PCI: Hardware I/O Error, SRC B6000103, "
686 "Automatic Reboot Disabled.\n");
688 return -1; /* Retry Try */
694 * Translate the I/O Address into a device node, bar, and bar offset.
695 * Note: Make sure the passed variable end up on the stack to avoid
696 * the exposure of being device global.
698 static inline struct device_node *xlate_iomm_address(
699 const volatile void __iomem *IoAddress,
700 u64 *dsaptr, u64 *BarOffsetPtr)
702 unsigned long OrigIoAddr;
703 unsigned long BaseIoAddr;
704 unsigned long TableIndex;
705 struct device_node *DevNode;
707 OrigIoAddr = (unsigned long __force)IoAddress;
708 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
710 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
711 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
712 DevNode = iomm_table[TableIndex];
714 if (DevNode != NULL) {
715 int barnum = iobar_table[TableIndex];
716 *dsaptr = PCI_DN(DevNode)->DsaAddr.DsaAddr | (barnum << 24);
717 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
719 panic("PCI: Invalid PCI IoAddress detected!\n");
724 * Read MM I/O Instructions for the iSeries
725 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
726 * else, data is returned in big Endian format.
728 * iSeries_Read_Byte = Read Byte ( 8 bit)
729 * iSeries_Read_Word = Read Word (16 bit)
730 * iSeries_Read_Long = Read Long (32 bit)
732 u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
737 struct HvCallPci_LoadReturn ret;
738 struct device_node *DevNode =
739 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
741 if (DevNode == NULL) {
742 static unsigned long last_jiffies;
743 static int num_printed;
745 if ((jiffies - last_jiffies) > 60 * HZ) {
746 last_jiffies = jiffies;
749 if (num_printed++ < 10)
750 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
755 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
756 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
758 return (u8)ret.value;
760 EXPORT_SYMBOL(iSeries_Read_Byte);
762 u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
767 struct HvCallPci_LoadReturn ret;
768 struct device_node *DevNode =
769 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
771 if (DevNode == NULL) {
772 static unsigned long last_jiffies;
773 static int num_printed;
775 if ((jiffies - last_jiffies) > 60 * HZ) {
776 last_jiffies = jiffies;
779 if (num_printed++ < 10)
780 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
785 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
787 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
789 return swab16((u16)ret.value);
791 EXPORT_SYMBOL(iSeries_Read_Word);
793 u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
798 struct HvCallPci_LoadReturn ret;
799 struct device_node *DevNode =
800 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
802 if (DevNode == NULL) {
803 static unsigned long last_jiffies;
804 static int num_printed;
806 if ((jiffies - last_jiffies) > 60 * HZ) {
807 last_jiffies = jiffies;
810 if (num_printed++ < 10)
811 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
816 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
818 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
820 return swab32((u32)ret.value);
822 EXPORT_SYMBOL(iSeries_Read_Long);
825 * Write MM I/O Instructions for the iSeries
827 * iSeries_Write_Byte = Write Byte (8 bit)
828 * iSeries_Write_Word = Write Word(16 bit)
829 * iSeries_Write_Long = Write Long(32 bit)
831 void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
837 struct device_node *DevNode =
838 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
840 if (DevNode == NULL) {
841 static unsigned long last_jiffies;
842 static int num_printed;
844 if ((jiffies - last_jiffies) > 60 * HZ) {
845 last_jiffies = jiffies;
848 if (num_printed++ < 10)
849 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
853 ++Pci_Io_Write_Count;
854 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
855 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
857 EXPORT_SYMBOL(iSeries_Write_Byte);
859 void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
865 struct device_node *DevNode =
866 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
868 if (DevNode == NULL) {
869 static unsigned long last_jiffies;
870 static int num_printed;
872 if ((jiffies - last_jiffies) > 60 * HZ) {
873 last_jiffies = jiffies;
876 if (num_printed++ < 10)
877 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
881 ++Pci_Io_Write_Count;
882 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
883 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
885 EXPORT_SYMBOL(iSeries_Write_Word);
887 void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
893 struct device_node *DevNode =
894 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
896 if (DevNode == NULL) {
897 static unsigned long last_jiffies;
898 static int num_printed;
900 if ((jiffies - last_jiffies) > 60 * HZ) {
901 last_jiffies = jiffies;
904 if (num_printed++ < 10)
905 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
909 ++Pci_Io_Write_Count;
910 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
911 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
913 EXPORT_SYMBOL(iSeries_Write_Long);