5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
12 #include <asm/pgtable.h>
14 #include <asm/hydra.h>
17 #include <asm/machdep.h>
18 #include <asm/sections.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/grackle.h>
26 void __iomem *gg2_pci_config_base;
29 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
30 * limit the bus number to 3 bits
33 int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
36 volatile void __iomem *cfg_data;
37 struct pci_controller *hose = bus->sysdata;
40 return PCIBIOS_DEVICE_NOT_FOUND;
42 * Note: the caller has already checked that off is
43 * suitably aligned and that len is 1, 2 or 4.
45 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
48 *val = in_8(cfg_data);
51 *val = in_le16(cfg_data);
54 *val = in_le32(cfg_data);
57 return PCIBIOS_SUCCESSFUL;
60 int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
63 volatile void __iomem *cfg_data;
64 struct pci_controller *hose = bus->sysdata;
67 return PCIBIOS_DEVICE_NOT_FOUND;
69 * Note: the caller has already checked that off is
70 * suitably aligned and that len is 1, 2 or 4.
72 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
78 out_le16(cfg_data, val);
81 out_le32(cfg_data, val);
84 return PCIBIOS_SUCCESSFUL;
87 static struct pci_ops gg2_pci_ops =
94 * Access functions for PCI config space using RTAS calls.
96 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
99 struct pci_controller *hose = bus->sysdata;
100 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
101 | (((bus->number - hose->first_busno) & 0xff) << 16)
102 | (hose->index << 24);
106 rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
108 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
111 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
114 struct pci_controller *hose = bus->sysdata;
115 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
116 | (((bus->number - hose->first_busno) & 0xff) << 16)
117 | (hose->index << 24);
120 rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
122 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
125 static struct pci_ops rtas_pci_ops =
131 volatile struct Hydra __iomem *Hydra = NULL;
136 struct device_node *np;
139 np = find_devices("mac-io");
140 if (np == NULL || of_address_to_resource(np, 0, &r))
142 Hydra = ioremap(r.start, r.end-r.start);
143 printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
144 printk("Hydra Feature_Control was %x",
145 in_le32(&Hydra->Feature_Control));
146 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
147 HYDRA_FC_SCSI_CELL_EN |
148 HYDRA_FC_SCCA_ENABLE |
149 HYDRA_FC_SCCB_ENABLE |
150 HYDRA_FC_ARB_BYPASS |
151 HYDRA_FC_MPIC_ENABLE |
152 HYDRA_FC_SLOW_SCC_PCLK |
153 HYDRA_FC_MPIC_IS_MASTER));
154 printk(", now %x\n", in_le32(&Hydra->Feature_Control));
158 #define PRG_CL_RESET_VALID 0x00010000
161 setup_python(struct pci_controller *hose, struct device_node *dev)
167 if (of_address_to_resource(dev, 0, &r)) {
168 printk(KERN_ERR "No address for Python PCI controller\n");
172 /* Clear the magic go-slow bit */
173 reg = ioremap(r.start + 0xf6000, 0x40);
175 val = in_be32(®[12]);
176 if (val & PRG_CL_RESET_VALID) {
177 out_be32(®[12], val & ~PRG_CL_RESET_VALID);
182 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
185 /* Marvell Discovery II based Pegasos 2 */
186 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
188 struct device_node *root = of_find_node_by_path("/");
189 struct device_node *rtas;
191 rtas = of_find_node_by_name (root, "rtas");
193 hose->ops = &rtas_pci_ops;
196 printk ("RTAS supporting Pegasos OF not found, please upgrade"
199 pci_assign_all_buses = 1;
200 /* keep the reference to the root node */
204 chrp_find_bridges(void)
206 struct device_node *dev;
207 const int *bus_range;
209 struct pci_controller *hose;
210 const unsigned int *dma;
211 const char *model, *machine;
212 int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
213 struct device_node *root = of_find_node_by_path("/");
216 * The PCI host bridge nodes on some machines don't have
217 * properties to adequately identify them, so we have to
218 * look at what sort of machine this is as well.
220 machine = of_get_property(root, "model", NULL);
221 if (machine != NULL) {
222 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
223 is_mot = strncmp(machine, "MOT", 3) == 0;
224 if (strncmp(machine, "Pegasos2", 8) == 0)
226 else if (strncmp(machine, "Pegasos", 7) == 0)
229 for (dev = root->child; dev != NULL; dev = dev->sibling) {
230 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
233 /* The GG2 bridge on the LongTrail doesn't have an address */
234 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
235 printk(KERN_WARNING "Can't use %s: no address\n",
239 bus_range = of_get_property(dev, "bus-range", &len);
240 if (bus_range == NULL || len < 2 * sizeof(int)) {
241 printk(KERN_WARNING "Can't get bus-range for %s\n",
245 if (bus_range[1] == bus_range[0])
246 printk(KERN_INFO "PCI bus %d", bus_range[0]);
248 printk(KERN_INFO "PCI buses %d..%d",
249 bus_range[0], bus_range[1]);
250 printk(" controlled by %s", dev->full_name);
252 printk(" at %llx", (unsigned long long)r.start);
255 hose = pcibios_alloc_controller();
257 printk("Can't allocate PCI controller structure for %s\n",
261 hose->arch_data = dev;
262 hose->first_busno = bus_range[0];
263 hose->last_busno = bus_range[1];
265 model = of_get_property(dev, "model", NULL);
268 if (device_is_compatible(dev, "IBM,python")) {
269 setup_python(hose, dev);
271 || strncmp(model, "Motorola, Grackle", 17) == 0) {
273 } else if (is_longtrail) {
274 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
275 hose->ops = &gg2_pci_ops;
277 gg2_pci_config_base = p;
278 } else if (is_pegasos == 1) {
279 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
280 } else if (is_pegasos == 2) {
281 setup_peg2(hose, dev);
282 } else if (!strncmp(model, "IBM,CPC710", 10)) {
283 setup_indirect_pci(hose,
284 r.start + 0x000f8000,
285 r.start + 0x000f8010);
287 dma = of_get_property(dev, "system-dma-base",
289 if (dma && len >= sizeof(*dma)) {
290 dma = (unsigned int *)
291 (((unsigned long)dma) +
293 pci_dram_offset = *dma;
297 printk("No methods for %s (model %s), using RTAS\n",
298 dev->full_name, model);
299 hose->ops = &rtas_pci_ops;
302 pci_process_bridge_OF_ranges(hose, dev, index == 0);
304 /* check the first bridge for a property that we can
305 use to set pci_dram_offset */
306 dma = of_get_property(dev, "ibm,dma-ranges", &len);
307 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
308 pci_dram_offset = dma[2] - dma[3];
309 printk("pci_dram_offset = %lx\n", pci_dram_offset);
315 /* SL82C105 IDE Control/Status Register */
316 #define SL82C105_IDECSR 0x40
318 /* Fixup for Winbond ATA quirk, required for briq */
319 void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
323 /* If non-briq machines need that fixup too, please speak up */
324 if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
327 if ((sl82c105->class & 5) != 5) {
328 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
329 /* Enable SL82C105 PCI native IDE mode */
330 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
331 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
332 sl82c105->class |= 0x05;
333 /* Disable SL82C105 second port */
334 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
338 chrp_pci_fixup_winbond_ata);