1 /* hw_ops.c - query/set operations on active SPU context.
3 * Copyright (C) IBM 2005
4 * Author: Mark Nutter <mnutter@us.ibm.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
26 #include <linux/poll.h>
27 #include <linux/smp.h>
28 #include <linux/smp_lock.h>
29 #include <linux/stddef.h>
30 #include <linux/unistd.h>
34 #include <asm/spu_priv1.h>
35 #include <asm/spu_csa.h>
36 #include <asm/mmu_context.h>
39 static int spu_hw_mbox_read(struct spu_context *ctx, u32 * data)
41 struct spu *spu = ctx->spu;
42 struct spu_problem __iomem *prob = spu->problem;
46 spin_lock_irq(&spu->register_lock);
47 mbox_stat = in_be32(&prob->mb_stat_R);
48 if (mbox_stat & 0x0000ff) {
49 *data = in_be32(&prob->pu_mb_R);
52 spin_unlock_irq(&spu->register_lock);
56 static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
58 return in_be32(&ctx->spu->problem->mb_stat_R);
61 static unsigned int spu_hw_mbox_stat_poll(struct spu_context *ctx,
64 struct spu *spu = ctx->spu;
68 spin_lock_irq(&spu->register_lock);
69 stat = in_be32(&spu->problem->mb_stat_R);
71 /* if the requested event is there, return the poll
72 mask, otherwise enable the interrupt to get notified,
73 but first mark any pending interrupts as done so
74 we don't get woken up unnecessarily */
76 if (events & (POLLIN | POLLRDNORM)) {
78 ret |= POLLIN | POLLRDNORM;
80 spu_int_stat_clear(spu, 2, 0x1);
81 spu_int_mask_or(spu, 2, 0x1);
84 if (events & (POLLOUT | POLLWRNORM)) {
86 ret = POLLOUT | POLLWRNORM;
88 spu_int_stat_clear(spu, 2, 0x10);
89 spu_int_mask_or(spu, 2, 0x10);
92 spin_unlock_irq(&spu->register_lock);
96 static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
98 struct spu *spu = ctx->spu;
99 struct spu_problem __iomem *prob = spu->problem;
100 struct spu_priv2 __iomem *priv2 = spu->priv2;
103 spin_lock_irq(&spu->register_lock);
104 if (in_be32(&prob->mb_stat_R) & 0xff0000) {
105 /* read the first available word */
106 *data = in_be64(&priv2->puint_mb_R);
109 /* make sure we get woken up by the interrupt */
110 spu_int_mask_or(spu, 2, 0x1);
113 spin_unlock_irq(&spu->register_lock);
117 static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
119 struct spu *spu = ctx->spu;
120 struct spu_problem __iomem *prob = spu->problem;
123 spin_lock_irq(&spu->register_lock);
124 if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
125 /* we have space to write wbox_data to */
126 out_be32(&prob->spu_mb_W, data);
129 /* make sure we get woken up by the interrupt when space
131 spu_int_mask_or(spu, 2, 0x10);
134 spin_unlock_irq(&spu->register_lock);
138 static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
140 out_be32(&ctx->spu->problem->signal_notify1, data);
143 static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
145 out_be32(&ctx->spu->problem->signal_notify2, data);
148 static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
150 struct spu *spu = ctx->spu;
151 struct spu_priv2 __iomem *priv2 = spu->priv2;
154 spin_lock_irq(&spu->register_lock);
155 tmp = in_be64(&priv2->spu_cfg_RW);
160 out_be64(&priv2->spu_cfg_RW, tmp);
161 spin_unlock_irq(&spu->register_lock);
164 static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
166 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
169 static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
171 struct spu *spu = ctx->spu;
172 struct spu_priv2 __iomem *priv2 = spu->priv2;
175 spin_lock_irq(&spu->register_lock);
176 tmp = in_be64(&priv2->spu_cfg_RW);
181 out_be64(&priv2->spu_cfg_RW, tmp);
182 spin_unlock_irq(&spu->register_lock);
185 static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
187 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
190 static u32 spu_hw_npc_read(struct spu_context *ctx)
192 return in_be32(&ctx->spu->problem->spu_npc_RW);
195 static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
197 out_be32(&ctx->spu->problem->spu_npc_RW, val);
200 static u32 spu_hw_status_read(struct spu_context *ctx)
202 return in_be32(&ctx->spu->problem->spu_status_R);
205 static char *spu_hw_get_ls(struct spu_context *ctx)
207 return ctx->spu->local_store;
210 static u32 spu_hw_runcntl_read(struct spu_context *ctx)
212 return in_be32(&ctx->spu->problem->spu_runcntl_RW);
215 static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
217 spin_lock_irq(&ctx->spu->register_lock);
218 if (val & SPU_RUNCNTL_ISOLATE)
219 out_be64(&ctx->spu->priv2->spu_privcntl_RW, 4LL);
220 out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
221 spin_unlock_irq(&ctx->spu->register_lock);
224 static void spu_hw_master_start(struct spu_context *ctx)
226 struct spu *spu = ctx->spu;
229 spin_lock_irq(&spu->register_lock);
230 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
231 spu_mfc_sr1_set(spu, sr1);
232 spin_unlock_irq(&spu->register_lock);
235 static void spu_hw_master_stop(struct spu_context *ctx)
237 struct spu *spu = ctx->spu;
240 spin_lock_irq(&spu->register_lock);
241 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
242 spu_mfc_sr1_set(spu, sr1);
243 spin_unlock_irq(&spu->register_lock);
246 static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
248 struct spu_problem __iomem *prob = ctx->spu->problem;
251 spin_lock_irq(&ctx->spu->register_lock);
253 if (in_be32(&prob->dma_querytype_RW))
256 out_be32(&prob->dma_querymask_RW, mask);
257 out_be32(&prob->dma_querytype_RW, mode);
259 spin_unlock_irq(&ctx->spu->register_lock);
263 static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
265 return in_be32(&ctx->spu->problem->dma_tagstatus_R);
268 static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
270 return in_be32(&ctx->spu->problem->dma_qstatus_R);
273 static int spu_hw_send_mfc_command(struct spu_context *ctx,
274 struct mfc_dma_command *cmd)
277 struct spu_problem __iomem *prob = ctx->spu->problem;
279 spin_lock_irq(&ctx->spu->register_lock);
280 out_be32(&prob->mfc_lsa_W, cmd->lsa);
281 out_be64(&prob->mfc_ea_W, cmd->ea);
282 out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
283 cmd->size << 16 | cmd->tag);
284 out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
285 cmd->class << 16 | cmd->cmd);
286 status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
287 spin_unlock_irq(&ctx->spu->register_lock);
289 switch (status & 0xffff) {
299 struct spu_context_ops spu_hw_ops = {
300 .mbox_read = spu_hw_mbox_read,
301 .mbox_stat_read = spu_hw_mbox_stat_read,
302 .mbox_stat_poll = spu_hw_mbox_stat_poll,
303 .ibox_read = spu_hw_ibox_read,
304 .wbox_write = spu_hw_wbox_write,
305 .signal1_write = spu_hw_signal1_write,
306 .signal2_write = spu_hw_signal2_write,
307 .signal1_type_set = spu_hw_signal1_type_set,
308 .signal1_type_get = spu_hw_signal1_type_get,
309 .signal2_type_set = spu_hw_signal2_type_set,
310 .signal2_type_get = spu_hw_signal2_type_get,
311 .npc_read = spu_hw_npc_read,
312 .npc_write = spu_hw_npc_write,
313 .status_read = spu_hw_status_read,
314 .get_ls = spu_hw_get_ls,
315 .runcntl_read = spu_hw_runcntl_read,
316 .runcntl_write = spu_hw_runcntl_write,
317 .master_start = spu_hw_master_start,
318 .master_stop = spu_hw_master_stop,
319 .set_mfc_query = spu_hw_set_mfc_query,
320 .read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
321 .get_mfc_free_elements = spu_hw_get_mfc_free_elements,
322 .send_mfc_command = spu_hw_send_mfc_command,