2 * Low-level SPU handling
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/poll.h>
29 #include <linux/ptrace.h>
30 #include <linux/slab.h>
31 #include <linux/wait.h>
35 #include <asm/semaphore.h>
37 #include <asm/mmu_context.h>
39 #include "interrupt.h"
41 static int __spu_trap_invalid_dma(struct spu *spu)
43 pr_debug("%s\n", __FUNCTION__);
44 force_sig(SIGBUS, /* info, */ current);
48 static int __spu_trap_dma_align(struct spu *spu)
50 pr_debug("%s\n", __FUNCTION__);
51 force_sig(SIGBUS, /* info, */ current);
55 static int __spu_trap_error(struct spu *spu)
57 pr_debug("%s\n", __FUNCTION__);
58 force_sig(SIGILL, /* info, */ current);
62 static void spu_restart_dma(struct spu *spu)
64 struct spu_priv2 __iomem *priv2 = spu->priv2;
66 if (!test_bit(SPU_CONTEXT_SWITCH_PENDING_nr, &spu->flags))
67 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
70 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
72 struct spu_priv2 __iomem *priv2 = spu->priv2;
73 struct mm_struct *mm = spu->mm;
76 pr_debug("%s\n", __FUNCTION__);
78 if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE_nr, &spu->flags)) {
79 /* SLBs are pre-loaded for context switch, so
80 * we should never get here!
82 printk("%s: invalid access during switch!\n", __func__);
85 if (!mm || (REGION_ID(ea) != USER_REGION_ID)) {
86 /* Future: support kernel segments so that drivers
89 pr_debug("invalid region access at %016lx\n", ea);
93 esid = (ea & ESID_MASK) | SLB_ESID_V;
94 vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) | SLB_VSID_USER;
95 if (in_hugepage_area(mm->context, ea))
98 out_be64(&priv2->slb_index_W, spu->slb_replace);
99 out_be64(&priv2->slb_vsid_RW, vsid);
100 out_be64(&priv2->slb_esid_RW, esid);
103 if (spu->slb_replace >= 8)
104 spu->slb_replace = 0;
106 spu_restart_dma(spu);
111 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
112 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
114 pr_debug("%s\n", __FUNCTION__);
116 /* Handle kernel space hash faults immediately.
117 User hash faults need to be deferred to process context. */
118 if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
119 && REGION_ID(ea) != USER_REGION_ID
120 && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
121 spu_restart_dma(spu);
125 if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE_nr, &spu->flags)) {
126 printk("%s: invalid access during switch!\n", __func__);
133 wake_up(&spu->stop_wq);
137 static int __spu_trap_mailbox(struct spu *spu)
139 if (spu->ibox_callback)
140 spu->ibox_callback(spu);
142 /* atomically disable SPU mailbox interrupts */
143 spin_lock(&spu->register_lock);
144 out_be64(&spu->priv1->int_mask_class2_RW,
145 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x1);
146 spin_unlock(&spu->register_lock);
150 static int __spu_trap_stop(struct spu *spu)
152 pr_debug("%s\n", __FUNCTION__);
153 spu->stop_code = in_be32(&spu->problem->spu_status_R);
154 wake_up(&spu->stop_wq);
158 static int __spu_trap_halt(struct spu *spu)
160 pr_debug("%s\n", __FUNCTION__);
161 spu->stop_code = in_be32(&spu->problem->spu_status_R);
162 wake_up(&spu->stop_wq);
166 static int __spu_trap_tag_group(struct spu *spu)
168 pr_debug("%s\n", __FUNCTION__);
169 /* wake_up(&spu->dma_wq); */
173 static int __spu_trap_spubox(struct spu *spu)
175 if (spu->wbox_callback)
176 spu->wbox_callback(spu);
178 /* atomically disable SPU mailbox interrupts */
179 spin_lock(&spu->register_lock);
180 out_be64(&spu->priv1->int_mask_class2_RW,
181 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x10);
182 spin_unlock(&spu->register_lock);
187 spu_irq_class_0(int irq, void *data, struct pt_regs *regs)
192 spu->class_0_pending = 1;
193 wake_up(&spu->stop_wq);
199 spu_irq_class_0_bottom(struct spu *spu)
203 spu->class_0_pending = 0;
205 stat = in_be64(&spu->priv1->int_stat_class0_RW);
207 if (stat & 1) /* invalid MFC DMA */
208 __spu_trap_invalid_dma(spu);
210 if (stat & 2) /* invalid DMA alignment */
211 __spu_trap_dma_align(spu);
213 if (stat & 4) /* error on SPU */
214 __spu_trap_error(spu);
216 out_be64(&spu->priv1->int_stat_class0_RW, stat);
221 spu_irq_class_1(int irq, void *data, struct pt_regs *regs)
224 unsigned long stat, mask, dar, dsisr;
228 /* atomically read & clear class1 status. */
229 spin_lock(&spu->register_lock);
230 mask = in_be64(&spu->priv1->int_mask_class1_RW);
231 stat = in_be64(&spu->priv1->int_stat_class1_RW) & mask;
232 dar = in_be64(&spu->priv1->mfc_dar_RW);
233 dsisr = in_be64(&spu->priv1->mfc_dsisr_RW);
234 out_be64(&spu->priv1->mfc_dsisr_RW, 0UL);
235 out_be64(&spu->priv1->int_stat_class1_RW, stat);
236 spin_unlock(&spu->register_lock);
238 if (stat & 1) /* segment fault */
239 __spu_trap_data_seg(spu, dar);
241 if (stat & 2) { /* mapping fault */
242 __spu_trap_data_map(spu, dar, dsisr);
245 if (stat & 4) /* ls compare & suspend on get */
248 if (stat & 8) /* ls compare & suspend on put */
251 return stat ? IRQ_HANDLED : IRQ_NONE;
255 spu_irq_class_2(int irq, void *data, struct pt_regs *regs)
261 stat = in_be64(&spu->priv1->int_stat_class2_RW);
263 pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat,
264 in_be64(&spu->priv1->int_mask_class2_RW));
267 if (stat & 1) /* PPC core mailbox */
268 __spu_trap_mailbox(spu);
270 if (stat & 2) /* SPU stop-and-signal */
271 __spu_trap_stop(spu);
273 if (stat & 4) /* SPU halted */
274 __spu_trap_halt(spu);
276 if (stat & 8) /* DMA tag group complete */
277 __spu_trap_tag_group(spu);
279 if (stat & 0x10) /* SPU mailbox threshold */
280 __spu_trap_spubox(spu);
282 out_be64(&spu->priv1->int_stat_class2_RW, stat);
283 return stat ? IRQ_HANDLED : IRQ_NONE;
287 spu_request_irqs(struct spu *spu)
292 irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
294 snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", spu->number);
295 ret = request_irq(irq_base + spu->isrc,
296 spu_irq_class_0, 0, spu->irq_c0, spu);
299 out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
301 snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", spu->number);
302 ret = request_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc,
303 spu_irq_class_1, 0, spu->irq_c1, spu);
306 out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
308 snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", spu->number);
309 ret = request_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc,
310 spu_irq_class_2, 0, spu->irq_c2, spu);
313 out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
317 free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
319 free_irq(irq_base + spu->isrc, spu);
325 spu_free_irqs(struct spu *spu)
329 irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
331 free_irq(irq_base + spu->isrc, spu);
332 free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
333 free_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc, spu);
336 static LIST_HEAD(spu_list);
337 static DECLARE_MUTEX(spu_mutex);
339 static void spu_init_channels(struct spu *spu)
341 static const struct {
345 { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
346 { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
348 { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
349 { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
350 { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
352 struct spu_priv2 *priv2;
357 /* initialize all channel data to zero */
358 for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
361 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
362 for (count = 0; count < zero_list[i].count; count++)
363 out_be64(&priv2->spu_chnldata_RW, 0);
366 /* initialize channel counts to meaningful values */
367 for (i = 0; i < ARRAY_SIZE(count_list); i++) {
368 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
369 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
373 static void spu_init_regs(struct spu *spu)
375 out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
376 out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
377 out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
380 struct spu *spu_alloc(void)
385 if (!list_empty(&spu_list)) {
386 spu = list_entry(spu_list.next, struct spu, list);
387 list_del_init(&spu->list);
388 pr_debug("Got SPU %x %d\n", spu->isrc, spu->number);
390 pr_debug("No SPU left\n");
396 spu_init_channels(spu);
402 EXPORT_SYMBOL(spu_alloc);
404 void spu_free(struct spu *spu)
407 list_add_tail(&spu->list, &spu_list);
410 EXPORT_SYMBOL(spu_free);
412 static int spu_handle_mm_fault(struct spu *spu)
414 struct mm_struct *mm = spu->mm;
415 struct vm_area_struct *vma;
416 u64 ea, dsisr, is_write;
422 if (!IS_VALID_EA(ea)) {
429 if (mm->pgd == NULL) {
433 down_read(&mm->mmap_sem);
434 vma = find_vma(mm, ea);
437 if (vma->vm_start <= ea)
439 if (!(vma->vm_flags & VM_GROWSDOWN))
442 if (expand_stack(vma, ea))
446 is_write = dsisr & MFC_DSISR_ACCESS_PUT;
448 if (!(vma->vm_flags & VM_WRITE))
451 if (dsisr & MFC_DSISR_ACCESS_DENIED)
453 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
457 switch (handle_mm_fault(mm, vma, ea, is_write)) {
464 case VM_FAULT_SIGBUS:
473 up_read(&mm->mmap_sem);
477 up_read(&mm->mmap_sem);
481 static int spu_handle_pte_fault(struct spu *spu)
483 u64 ea, dsisr, access, error = 0UL;
488 if (dsisr & MFC_DSISR_PTE_NOT_FOUND) {
489 access = (_PAGE_PRESENT | _PAGE_USER);
490 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
491 if (hash_page(ea, access, 0x300) != 0)
492 error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
494 if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) ||
495 (dsisr & MFC_DSISR_ACCESS_DENIED)) {
496 if ((ret = spu_handle_mm_fault(spu)) != 0)
497 error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
499 error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
504 spu_restart_dma(spu);
506 __spu_trap_invalid_dma(spu);
511 static inline int spu_pending(struct spu *spu, u32 * stat)
513 struct spu_problem __iomem *prob = spu->problem;
516 *stat = in_be32(&prob->spu_status_R);
517 pte_fault = spu->dsisr &
518 (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED);
519 return (!(*stat & 0x1) || pte_fault || spu->class_0_pending) ? 1 : 0;
522 int spu_run(struct spu *spu)
524 struct spu_problem __iomem *prob;
525 struct spu_priv1 __iomem *priv1;
526 struct spu_priv2 __iomem *priv2;
536 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
539 ret = wait_event_interruptible(spu->stop_wq,
540 spu_pending(spu, &status));
543 (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))
544 ret = spu_handle_pte_fault(spu);
546 if (spu->class_0_pending)
547 spu_irq_class_0_bottom(spu);
549 if (!ret && signal_pending(current))
552 } while (!ret && !(status &
553 (SPU_STATUS_STOPPED_BY_STOP |
554 SPU_STATUS_STOPPED_BY_HALT)));
556 /* Ensure SPU is stopped. */
557 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
559 while (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)
562 out_be64(&priv2->slb_invalidate_all_W, 0);
563 out_be64(&priv1->tlb_invalidate_entry_W, 0UL);
566 /* Check for SPU breakpoint. */
567 if (unlikely(current->ptrace & PT_PTRACED)) {
568 status = in_be32(&prob->spu_status_R);
570 if ((status & SPU_STATUS_STOPPED_BY_STOP)
571 && status >> SPU_STOP_STATUS_SHIFT == 0x3fff) {
572 force_sig(SIGTRAP, current);
579 EXPORT_SYMBOL(spu_run);
581 static void __iomem * __init map_spe_prop(struct device_node *n,
584 struct address_prop {
585 unsigned long address;
587 } __attribute__((packed)) *prop;
592 p = get_property(n, name, &proplen);
593 if (proplen != sizeof (struct address_prop))
598 return ioremap(prop->address, prop->len);
601 static void spu_unmap(struct spu *spu)
605 iounmap(spu->problem);
606 iounmap((u8 __iomem *)spu->local_store);
609 static int __init spu_map_device(struct spu *spu, struct device_node *spe)
615 prop = get_property(spe, "isrc", NULL);
618 spu->isrc = *(unsigned int *)prop;
620 spu->name = get_property(spe, "name", NULL);
624 prop = get_property(spe, "local-store", NULL);
627 spu->local_store_phys = *(unsigned long *)prop;
629 /* we use local store as ram, not io memory */
630 spu->local_store = (void __force *)map_spe_prop(spe, "local-store");
631 if (!spu->local_store)
634 spu->problem= map_spe_prop(spe, "problem");
638 spu->priv1= map_spe_prop(spe, "priv1");
642 spu->priv2= map_spe_prop(spe, "priv2");
654 static int __init find_spu_node_id(struct device_node *spe)
657 struct device_node *cpu;
659 cpu = spe->parent->parent;
660 id = (unsigned int *)get_property(cpu, "node-id", NULL);
665 static int __init create_spu(struct device_node *spe)
672 spu = kmalloc(sizeof (*spu), GFP_KERNEL);
676 ret = spu_map_device(spu, spe);
680 spu->node = find_spu_node_id(spe);
682 spu->slb_replace = 0;
687 spu->class_0_pending = 0;
691 spin_lock_init(&spu->register_lock);
693 out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
694 out_be64(&spu->priv1->mfc_sr1_RW, 0x33);
696 init_waitqueue_head(&spu->stop_wq);
697 spu->ibox_callback = NULL;
698 spu->wbox_callback = NULL;
701 spu->number = number++;
702 ret = spu_request_irqs(spu);
706 list_add(&spu->list, &spu_list);
709 pr_debug(KERN_DEBUG "Using SPE %s %02x %p %p %p %p %d\n",
710 spu->name, spu->isrc, spu->local_store,
711 spu->problem, spu->priv1, spu->priv2, spu->number);
723 static void destroy_spu(struct spu *spu)
725 list_del_init(&spu->list);
732 static void cleanup_spu_base(void)
734 struct spu *spu, *tmp;
736 list_for_each_entry_safe(spu, tmp, &spu_list, list)
740 module_exit(cleanup_spu_base);
742 static int __init init_spu_base(void)
744 struct device_node *node;
748 for (node = of_find_node_by_type(NULL, "spe");
749 node; node = of_find_node_by_type(node, "spe")) {
750 ret = create_spu(node);
752 printk(KERN_WARNING "%s: Error initializing %s\n",
753 __FUNCTION__, node->name);
758 /* in some old firmware versions, the spe is called 'spc', so we
759 look for that as well */
760 for (node = of_find_node_by_type(NULL, "spc");
761 node; node = of_find_node_by_type(node, "spc")) {
762 ret = create_spu(node);
764 printk(KERN_WARNING "%s: Error initializing %s\n",
765 __FUNCTION__, node->name);
772 module_init(init_spu_base);
774 MODULE_LICENSE("GPL");
775 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");