err.no Git - linux-2.6/blob - arch/powerpc/platforms/cell/pmu.c

   1 /*
   2  * Cell Broadband Engine Performance Monitor
   3  *
   4  * (C) Copyright IBM Corporation 2001,2006
   5  *
   6  * Author:
   7  *    David Erb (djerb@us.ibm.com)
   8  *    Kevin Corry (kevcorry@us.ibm.com)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2, or (at your option)
  13  * any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/interrupt.h>
  26 #include <linux/types.h>
  27 #include <asm/io.h>
  28 #include <asm/machdep.h>
  29 #include <asm/pmc.h>
  30 #include <asm/reg.h>
  31 #include <asm/spu.h>
  32
  33 #include "cbe_regs.h"
  34 #include "interrupt.h"
  35
  36 /*
  37  * When writing to write-only mmio addresses, save a shadow copy. All of the
  38  * registers are 32-bit, but stored in the upper-half of a 64-bit field in
  39  * pmd_regs.
  40  */
  41
  42 #define WRITE_WO_MMIO(reg, x)                                   \
  43         do {                                                    \
  44                 u32 _x = (x);                                   \
  45                 struct cbe_pmd_regs __iomem *pmd_regs;          \
  46                 struct cbe_pmd_shadow_regs *shadow_regs;        \
  47                 pmd_regs = cbe_get_cpu_pmd_regs(cpu);           \
  48                 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
  49                 out_be64(&(pmd_regs->reg), (((u64)_x) << 32));  \
  50                 shadow_regs->reg = _x;                          \
  51         } while (0)
  52
  53 #define READ_SHADOW_REG(val, reg)                               \
  54         do {                                                    \
  55                 struct cbe_pmd_shadow_regs *shadow_regs;        \
  56                 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
  57                 (val) = shadow_regs->reg;                       \
  58         } while (0)
  59
  60 #define READ_MMIO_UPPER32(val, reg)                             \
  61         do {                                                    \
  62                 struct cbe_pmd_regs __iomem *pmd_regs;          \
  63                 pmd_regs = cbe_get_cpu_pmd_regs(cpu);           \
  64                 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32);   \
  65         } while (0)
  66
  67 /*
  68  * Physical counter registers.
  69  * Each physical counter can act as one 32-bit counter or two 16-bit counters.
  70  */
  71
  72 u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
  73 {
  74         u32 val_in_latch, val = 0;
  75
  76         if (phys_ctr < NR_PHYS_CTRS) {
  77                 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
  78
  79                 /* Read the latch or the actual counter, whichever is newer. */
  80                 if (val_in_latch & (1 << phys_ctr)) {
  81                         READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
  82                 } else {
  83                         READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
  84                 }
  85         }
  86
  87         return val;
  88 }
  89 EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
  90
  91 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
  92 {
  93         struct cbe_pmd_shadow_regs *shadow_regs;
  94         u32 pm_ctrl;
  95
  96         if (phys_ctr < NR_PHYS_CTRS) {
  97                 /* Writing to a counter only writes to a hardware latch.
  98                  * The new value is not propagated to the actual counter
  99                  * until the performance monitor is enabled.
 100                  */
 101                 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
 102
 103                 pm_ctrl = cbe_read_pm(cpu, pm_control);
 104                 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
 105                         /* The counters are already active, so we need to
 106                          * rewrite the pm_control register to "re-enable"
 107                          * the PMU.
 108                          */
 109                         cbe_write_pm(cpu, pm_control, pm_ctrl);
 110                 } else {
 111                         shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
 112                         shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
 113                 }
 114         }
 115 }
 116 EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
 117
 118 /*
 119  * "Logical" counter registers.
 120  * These will read/write 16-bits or 32-bits depending on the
 121  * current size of the counter. Counters 4 - 7 are always 16-bit.
 122  */
 123
 124 u32 cbe_read_ctr(u32 cpu, u32 ctr)
 125 {
 126         u32 val;
 127         u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
 128
 129         val = cbe_read_phys_ctr(cpu, phys_ctr);
 130
 131         if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
 132                 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
 133
 134         return val;
 135 }
 136 EXPORT_SYMBOL_GPL(cbe_read_ctr);
 137
 138 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
 139 {
 140         u32 phys_ctr;
 141         u32 phys_val;
 142
 143         phys_ctr = ctr & (NR_PHYS_CTRS - 1);
 144
 145         if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
 146                 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
 147
 148                 if (ctr < NR_PHYS_CTRS)
 149                         val = (val << 16) | (phys_val & 0xffff);
 150                 else
 151                         val = (val & 0xffff) | (phys_val & 0xffff0000);
 152         }
 153
 154         cbe_write_phys_ctr(cpu, phys_ctr, val);
 155 }
 156 EXPORT_SYMBOL_GPL(cbe_write_ctr);
 157
 158 /*
 159  * Counter-control registers.
 160  * Each "logical" counter has a corresponding control register.
 161  */
 162
 163 u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
 164 {
 165         u32 pm07_control = 0;
 166
 167         if (ctr < NR_CTRS)
 168                 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
 169
 170         return pm07_control;
 171 }
 172 EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
 173
 174 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
 175 {
 176         if (ctr < NR_CTRS)
 177                 WRITE_WO_MMIO(pm07_control[ctr], val);
 178 }
 179 EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
 180
 181 /*
 182  * Other PMU control registers. Most of these are write-only.
 183  */
 184
 185 u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
 186 {
 187         u32 val = 0;
 188
 189         switch (reg) {
 190         case group_control:
 191                 READ_SHADOW_REG(val, group_control);
 192                 break;
 193
 194         case debug_bus_control:
 195                 READ_SHADOW_REG(val, debug_bus_control);
 196                 break;
 197
 198         case trace_address:
 199                 READ_MMIO_UPPER32(val, trace_address);
 200                 break;
 201
 202         case ext_tr_timer:
 203                 READ_SHADOW_REG(val, ext_tr_timer);
 204                 break;
 205
 206         case pm_status:
 207                 READ_MMIO_UPPER32(val, pm_status);
 208                 break;
 209
 210         case pm_control:
 211                 READ_SHADOW_REG(val, pm_control);
 212                 break;
 213
 214         case pm_interval:
 215                 READ_SHADOW_REG(val, pm_interval);
 216                 break;
 217
 218         case pm_start_stop:
 219                 READ_SHADOW_REG(val, pm_start_stop);
 220                 break;
 221         }
 222
 223         return val;
 224 }
 225 EXPORT_SYMBOL_GPL(cbe_read_pm);
 226
 227 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
 228 {
 229         switch (reg) {
 230         case group_control:
 231                 WRITE_WO_MMIO(group_control, val);
 232                 break;
 233
 234         case debug_bus_control:
 235                 WRITE_WO_MMIO(debug_bus_control, val);
 236                 break;
 237
 238         case trace_address:
 239                 WRITE_WO_MMIO(trace_address, val);
 240                 break;
 241
 242         case ext_tr_timer:
 243                 WRITE_WO_MMIO(ext_tr_timer, val);
 244                 break;
 245
 246         case pm_status:
 247                 WRITE_WO_MMIO(pm_status, val);
 248                 break;
 249
 250         case pm_control:
 251                 WRITE_WO_MMIO(pm_control, val);
 252                 break;
 253
 254         case pm_interval:
 255                 WRITE_WO_MMIO(pm_interval, val);
 256                 break;
 257
 258         case pm_start_stop:
 259                 WRITE_WO_MMIO(pm_start_stop, val);
 260                 break;
 261         }
 262 }
 263 EXPORT_SYMBOL_GPL(cbe_write_pm);
 264
 265 /*
 266  * Get/set the size of a physical counter to either 16 or 32 bits.
 267  */
 268
 269 u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
 270 {
 271         u32 pm_ctrl, size = 0;
 272
 273         if (phys_ctr < NR_PHYS_CTRS) {
 274                 pm_ctrl = cbe_read_pm(cpu, pm_control);
 275                 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
 276         }
 277
 278         return size;
 279 }
 280 EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
 281
 282 void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
 283 {
 284         u32 pm_ctrl;
 285
 286         if (phys_ctr < NR_PHYS_CTRS) {
 287                 pm_ctrl = cbe_read_pm(cpu, pm_control);
 288                 switch (ctr_size) {
 289                 case 16:
 290                         pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
 291                         break;
 292
 293                 case 32:
 294                         pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
 295                         break;
 296                 }
 297                 cbe_write_pm(cpu, pm_control, pm_ctrl);
 298         }
 299 }
 300 EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
 301
 302 /*
 303  * Enable/disable the entire performance monitoring unit.
 304  * When we enable the PMU, all pending writes to counters get committed.
 305  */
 306
 307 void cbe_enable_pm(u32 cpu)
 308 {
 309         struct cbe_pmd_shadow_regs *shadow_regs;
 310         u32 pm_ctrl;
 311
 312         shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
 313         shadow_regs->counter_value_in_latch = 0;
 314
 315         pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
 316         cbe_write_pm(cpu, pm_control, pm_ctrl);
 317 }
 318 EXPORT_SYMBOL_GPL(cbe_enable_pm);
 319
 320 void cbe_disable_pm(u32 cpu)
 321 {
 322         u32 pm_ctrl;
 323         pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
 324         cbe_write_pm(cpu, pm_control, pm_ctrl);
 325 }
 326 EXPORT_SYMBOL_GPL(cbe_disable_pm);
 327
 328 /*
 329  * Reading from the trace_buffer.
 330  * The trace buffer is two 64-bit registers. Reading from
 331  * the second half automatically increments the trace_address.
 332  */
 333
 334 void cbe_read_trace_buffer(u32 cpu, u64 *buf)
 335 {
 336         struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
 337
 338         *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
 339         *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
 340 }
 341 EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
 342
 343 /*
 344  * Enabling/disabling interrupts for the entire performance monitoring unit.
 345  */
 346
 347 u32 cbe_query_pm_interrupts(u32 cpu)
 348 {
 349         return cbe_read_pm(cpu, pm_status);
 350 }
 351 EXPORT_SYMBOL_GPL(cbe_query_pm_interrupts);
 352
 353 u32 cbe_clear_pm_interrupts(u32 cpu)
 354 {
 355         /* Reading pm_status clears the interrupt bits. */
 356         return cbe_query_pm_interrupts(cpu);
 357 }
 358 EXPORT_SYMBOL_GPL(cbe_clear_pm_interrupts);
 359
 360 void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
 361 {
 362         /* Set which node and thread will handle the next interrupt. */
 363         iic_set_interrupt_routing(cpu, thread, 0);
 364
 365         /* Enable the interrupt bits in the pm_status register. */
 366         if (mask)
 367                 cbe_write_pm(cpu, pm_status, mask);
 368 }
 369 EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
 370
 371 void cbe_disable_pm_interrupts(u32 cpu)
 372 {
 373         cbe_clear_pm_interrupts(cpu);
 374         cbe_write_pm(cpu, pm_status, 0);
 375 }
 376 EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
 377
 378 static irqreturn_t cbe_pm_irq(int irq, void *dev_id, struct pt_regs *regs)
 379 {
 380         perf_irq(regs);
 381         return IRQ_HANDLED;
 382 }
 383
 384 int __init cbe_init_pm_irq(void)
 385 {
 386         unsigned int irq;
 387         int rc, node;
 388
 389         for_each_node(node) {
 390                 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
 391                                                (node << IIC_IRQ_NODE_SHIFT));
 392                 if (irq == NO_IRQ) {
 393                         printk("ERROR: Unable to allocate irq for node %d\n",
 394                                node);
 395                         return -EINVAL;
 396                 }
 397
 398                 rc = request_irq(irq, cbe_pm_irq,
 399                                  IRQF_DISABLED, "cbe-pmu-0", NULL);
 400                 if (rc) {
 401                         printk("ERROR: Request for irq on node %d failed\n",
 402                                node);
 403                         return rc;
 404                 }
 405         }
 406
 407         return 0;
 408 }
 409 arch_initcall(cbe_init_pm_irq);
 410