2 * MPC85xx setup and early boot code plus other random bits.
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/pci.h>
20 #include <linux/kdev_t.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/initrd.h>
26 #include <linux/module.h>
27 #include <linux/fsl_devices.h>
29 #include <asm/system.h>
30 #include <asm/pgtable.h>
32 #include <asm/atomic.h>
35 #include <asm/machdep.h>
37 #include <asm/bootinfo.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/mpc85xx.h>
41 #include <mm/mmu_decl.h>
45 #include <asm/i8259.h>
47 #include <sysdev/fsl_soc.h>
50 static int cds_pci_slot = 2;
51 static volatile u8 *cadmus;
55 #define ARCADIA_HOST_BRIDGE_IDSEL 17
56 #define ARCADIA_2ND_BRIDGE_IDSEL 3
58 extern int mpc85xx_pci2_busno;
60 static int mpc85xx_exclude_device(struct pci_controller *hose,
61 u_char bus, u_char devfn)
63 if (bus == 0 && PCI_SLOT(devfn) == 0)
64 return PCIBIOS_DEVICE_NOT_FOUND;
65 if (mpc85xx_pci2_busno)
66 if (bus == (mpc85xx_pci2_busno) && PCI_SLOT(devfn) == 0)
67 return PCIBIOS_DEVICE_NOT_FOUND;
68 /* We explicitly do not go past the Tundra 320 Bridge */
69 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
70 return PCIBIOS_DEVICE_NOT_FOUND;
71 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
72 return PCIBIOS_DEVICE_NOT_FOUND;
74 return PCIBIOS_SUCCESSFUL;
77 static void __init mpc85xx_cds_pcibios_fixup(void)
82 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
83 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
85 * U-Boot does not set the enable bits
86 * for the IDE device. Force them on here.
88 pci_read_config_byte(dev, 0x40, &c);
89 c |= 0x03; /* IDE: Chip Enable Bits */
90 pci_write_config_byte(dev, 0x40, c);
93 * Since only primary interface works, force the
94 * IDE function to standard primary IDE interrupt
98 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
103 * Force legacy USB interrupt routing
105 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
106 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
108 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
112 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
113 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
115 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
119 /* Now map all the PCI irqs */
121 for_each_pci_dev(dev)
122 pci_read_irq_line(dev);
125 #ifdef CONFIG_PPC_I8259
126 #warning The i8259 PIC support is currently broken
127 static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
129 unsigned int cascade_irq = i8259_irq();
131 if (cascade_irq != NO_IRQ)
132 generic_handle_irq(cascade_irq);
134 desc->chip->eoi(irq);
136 #endif /* PPC_I8259 */
137 #endif /* CONFIG_PCI */
139 static void __init mpc85xx_cds_pic_init(void)
143 struct device_node *np = NULL;
144 #ifdef CONFIG_PPC_I8259
145 struct device_node *cascade_node = NULL;
149 np = of_find_node_by_type(np, "open-pic");
152 printk(KERN_ERR "Could not find open-pic node\n");
156 if (of_address_to_resource(np, 0, &r)) {
157 printk(KERN_ERR "Failed to map mpic register space\n");
162 mpic = mpic_alloc(np, r.start,
163 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
165 BUG_ON(mpic == NULL);
167 /* Return the mpic node */
170 mpic_assign_isu(mpic, 0, r.start + 0x10200);
171 mpic_assign_isu(mpic, 1, r.start + 0x10280);
172 mpic_assign_isu(mpic, 2, r.start + 0x10300);
173 mpic_assign_isu(mpic, 3, r.start + 0x10380);
174 mpic_assign_isu(mpic, 4, r.start + 0x10400);
175 mpic_assign_isu(mpic, 5, r.start + 0x10480);
176 mpic_assign_isu(mpic, 6, r.start + 0x10500);
177 mpic_assign_isu(mpic, 7, r.start + 0x10580);
179 /* Used only for 8548 so far, but no harm in
180 * allocating them for everyone */
181 mpic_assign_isu(mpic, 8, r.start + 0x10600);
182 mpic_assign_isu(mpic, 9, r.start + 0x10680);
183 mpic_assign_isu(mpic, 10, r.start + 0x10700);
184 mpic_assign_isu(mpic, 11, r.start + 0x10780);
186 /* External Interrupts */
187 mpic_assign_isu(mpic, 12, r.start + 0x10000);
188 mpic_assign_isu(mpic, 13, r.start + 0x10080);
189 mpic_assign_isu(mpic, 14, r.start + 0x10100);
193 #ifdef CONFIG_PPC_I8259
194 /* Initialize the i8259 controller */
195 for_each_node_by_type(np, "interrupt-controller")
196 if (of_device_is_compatible(np, "chrp,iic")) {
201 if (cascade_node == NULL) {
202 printk(KERN_DEBUG "Could not find i8259 PIC\n");
206 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
207 if (cascade_irq == NO_IRQ) {
208 printk(KERN_ERR "Failed to map cascade interrupt\n");
212 i8259_init(cascade_node, 0);
213 of_node_put(cascade_node);
215 set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
216 #endif /* CONFIG_PPC_I8259 */
220 * Setup the architecture
222 static void __init mpc85xx_cds_setup_arch(void)
224 struct device_node *cpu;
226 struct device_node *np;
230 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
232 cpu = of_find_node_by_type(NULL, "cpu");
234 const unsigned int *fp;
236 fp = of_get_property(cpu, "clock-frequency", NULL);
238 loops_per_jiffy = *fp / HZ;
240 loops_per_jiffy = 500000000 / HZ;
244 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
245 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
247 if (ppc_md.progress) {
249 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
250 cadmus[CM_VER], cds_pci_slot);
251 ppc_md.progress(buf, 0);
255 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
256 mpc85xx_add_bridge(np);
258 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
259 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
263 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
265 uint pvid, svid, phid1;
266 uint memsize = total_memory;
268 pvid = mfspr(SPRN_PVR);
269 svid = mfspr(SPRN_SVR);
271 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
272 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
273 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
274 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
276 /* Display cpu Pll setting */
277 phid1 = mfspr(SPRN_HID1);
278 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
280 /* Display the amount of memory */
281 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
286 * Called very early, device-tree isn't unflattened
288 static int __init mpc85xx_cds_probe(void)
290 unsigned long root = of_get_flat_dt_root();
292 return of_flat_dt_is_compatible(root, "MPC85xxCDS");
295 define_machine(mpc85xx_cds) {
296 .name = "MPC85xx CDS",
297 .probe = mpc85xx_cds_probe,
298 .setup_arch = mpc85xx_cds_setup_arch,
299 .init_IRQ = mpc85xx_cds_pic_init,
300 .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
301 .get_irq = mpic_get_irq,
302 .restart = mpc85xx_restart,
303 .calibrate_decr = generic_calibrate_decr,
304 .progress = udbg_progress,