2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
73 * Note: pte --> Linux PTE
74 * HPTE --> PowerPC Hashed Page Table Entry
77 * htab_initialize is called with the MMU off (of course), but
78 * the kernel has been copied down to zero so it can directly
79 * reference global data. At this point it is very difficult
80 * to print debug info.
85 extern unsigned long dart_tablebase;
86 #endif /* CONFIG_U3_DART */
88 static unsigned long _SDR1;
89 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91 struct hash_pte *htab_address;
92 unsigned long htab_size_bytes;
93 unsigned long htab_hash_mask;
94 int mmu_linear_psize = MMU_PAGE_4K;
95 int mmu_virtual_psize = MMU_PAGE_4K;
96 int mmu_vmalloc_psize = MMU_PAGE_4K;
97 #ifdef CONFIG_SPARSEMEM_VMEMMAP
98 int mmu_vmemmap_psize = MMU_PAGE_4K;
100 int mmu_io_psize = MMU_PAGE_4K;
101 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
102 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
103 u16 mmu_slb_size = 64;
104 #ifdef CONFIG_HUGETLB_PAGE
105 int mmu_huge_psize = MMU_PAGE_16M;
106 unsigned int HPAGE_SHIFT;
108 #ifdef CONFIG_PPC_64K_PAGES
109 int mmu_ci_restrictions;
111 #ifdef CONFIG_DEBUG_PAGEALLOC
112 static u8 *linear_map_hash_slots;
113 static unsigned long linear_map_hash_count;
114 static DEFINE_SPINLOCK(linear_map_hash_lock);
115 #endif /* CONFIG_DEBUG_PAGEALLOC */
117 /* There are definitions of page sizes arrays to be used when none
118 * is provided by the firmware.
121 /* Pre-POWER4 CPUs (4k pages only)
123 static struct mmu_psize_def mmu_psize_defaults_old[] = {
133 /* POWER4, GPUL, POWER5
135 * Support for 16Mb large pages
137 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
155 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
156 unsigned long pstart, unsigned long mode,
157 int psize, int ssize)
159 unsigned long vaddr, paddr;
160 unsigned int step, shift;
161 unsigned long tmp_mode;
164 shift = mmu_psize_defs[psize].shift;
167 for (vaddr = vstart, paddr = pstart; vaddr < vend;
168 vaddr += step, paddr += step) {
169 unsigned long hash, hpteg;
170 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
171 unsigned long va = hpt_va(vaddr, vsid, ssize);
175 /* Make non-kernel text non-executable */
176 if (!in_kernel_text(vaddr))
177 tmp_mode = mode | HPTE_R_N;
179 hash = hpt_hash(va, shift, ssize);
180 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
182 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
184 BUG_ON(!ppc_md.hpte_insert);
185 ret = ppc_md.hpte_insert(hpteg, va, paddr,
186 tmp_mode, HPTE_V_BOLTED, psize, ssize);
190 #ifdef CONFIG_DEBUG_PAGEALLOC
191 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
192 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
193 #endif /* CONFIG_DEBUG_PAGEALLOC */
195 return ret < 0 ? ret : 0;
198 #ifdef CONFIG_MEMORY_HOTPLUG
199 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
200 int psize, int ssize)
203 unsigned int step, shift;
205 shift = mmu_psize_defs[psize].shift;
208 if (!ppc_md.hpte_removebolted) {
209 printk(KERN_WARNING "Platform doesn't implement "
210 "hpte_removebolted\n");
214 for (vaddr = vstart; vaddr < vend; vaddr += step)
215 ppc_md.hpte_removebolted(vaddr, psize, ssize);
219 #endif /* CONFIG_MEMORY_HOTPLUG */
221 static int __init htab_dt_scan_seg_sizes(unsigned long node,
222 const char *uname, int depth,
225 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
227 unsigned long size = 0;
229 /* We are scanning "cpu" nodes only */
230 if (type == NULL || strcmp(type, "cpu") != 0)
233 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
237 for (; size >= 4; size -= 4, ++prop) {
239 DBG("1T segment support detected\n");
240 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
244 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
248 static void __init htab_init_seg_sizes(void)
250 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
253 static int __init htab_dt_scan_page_sizes(unsigned long node,
254 const char *uname, int depth,
257 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
259 unsigned long size = 0;
261 /* We are scanning "cpu" nodes only */
262 if (type == NULL || strcmp(type, "cpu") != 0)
265 prop = (u32 *)of_get_flat_dt_prop(node,
266 "ibm,segment-page-sizes", &size);
268 DBG("Page sizes from device-tree:\n");
270 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
272 unsigned int shift = prop[0];
273 unsigned int slbenc = prop[1];
274 unsigned int lpnum = prop[2];
275 unsigned int lpenc = 0;
276 struct mmu_psize_def *def;
279 size -= 3; prop += 3;
280 while(size > 0 && lpnum) {
281 if (prop[0] == shift)
283 prop += 2; size -= 2;
298 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
306 def = &mmu_psize_defs[idx];
311 def->avpnm = (1 << (shift - 23)) - 1;
314 /* We don't know for sure what's up with tlbiel, so
315 * for now we only set it for 4K and 64K pages
317 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
322 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
323 "tlbiel=%d, penc=%d\n",
324 idx, shift, def->sllp, def->avpnm, def->tlbiel,
332 static void __init htab_init_page_sizes(void)
336 /* Default to 4K pages only */
337 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
338 sizeof(mmu_psize_defaults_old));
341 * Try to find the available page sizes in the device-tree
343 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
344 if (rc != 0) /* Found */
348 * Not in the device-tree, let's fallback on known size
349 * list for 16M capable GP & GR
351 if (cpu_has_feature(CPU_FTR_16M_PAGE))
352 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
353 sizeof(mmu_psize_defaults_gp));
355 #ifndef CONFIG_DEBUG_PAGEALLOC
357 * Pick a size for the linear mapping. Currently, we only support
358 * 16M, 1M and 4K which is the default
360 if (mmu_psize_defs[MMU_PAGE_16M].shift)
361 mmu_linear_psize = MMU_PAGE_16M;
362 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
363 mmu_linear_psize = MMU_PAGE_1M;
364 #endif /* CONFIG_DEBUG_PAGEALLOC */
366 #ifdef CONFIG_PPC_64K_PAGES
368 * Pick a size for the ordinary pages. Default is 4K, we support
369 * 64K for user mappings and vmalloc if supported by the processor.
370 * We only use 64k for ioremap if the processor
371 * (and firmware) support cache-inhibited large pages.
372 * If not, we use 4k and set mmu_ci_restrictions so that
373 * hash_page knows to switch processes that use cache-inhibited
374 * mappings to 4k pages.
376 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
377 mmu_virtual_psize = MMU_PAGE_64K;
378 mmu_vmalloc_psize = MMU_PAGE_64K;
379 if (mmu_linear_psize == MMU_PAGE_4K)
380 mmu_linear_psize = MMU_PAGE_64K;
381 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
383 * Don't use 64k pages for ioremap on pSeries, since
384 * that would stop us accessing the HEA ethernet.
386 if (!machine_is(pseries))
387 mmu_io_psize = MMU_PAGE_64K;
389 mmu_ci_restrictions = 1;
391 #endif /* CONFIG_PPC_64K_PAGES */
393 #ifdef CONFIG_SPARSEMEM_VMEMMAP
394 /* We try to use 16M pages for vmemmap if that is supported
395 * and we have at least 1G of RAM at boot
397 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
398 lmb_phys_mem_size() >= 0x40000000)
399 mmu_vmemmap_psize = MMU_PAGE_16M;
400 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
401 mmu_vmemmap_psize = MMU_PAGE_64K;
403 mmu_vmemmap_psize = MMU_PAGE_4K;
404 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
406 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
407 "virtual = %d, io = %d"
408 #ifdef CONFIG_SPARSEMEM_VMEMMAP
412 mmu_psize_defs[mmu_linear_psize].shift,
413 mmu_psize_defs[mmu_virtual_psize].shift,
414 mmu_psize_defs[mmu_io_psize].shift
415 #ifdef CONFIG_SPARSEMEM_VMEMMAP
416 ,mmu_psize_defs[mmu_vmemmap_psize].shift
420 #ifdef CONFIG_HUGETLB_PAGE
421 /* Init large page size. Currently, we pick 16M or 1M depending
422 * on what is available
424 if (mmu_psize_defs[MMU_PAGE_16M].shift)
425 set_huge_psize(MMU_PAGE_16M);
426 /* With 4k/4level pagetables, we can't (for now) cope with a
427 * huge page size < PMD_SIZE */
428 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
429 set_huge_psize(MMU_PAGE_1M);
430 #endif /* CONFIG_HUGETLB_PAGE */
433 static int __init htab_dt_scan_pftsize(unsigned long node,
434 const char *uname, int depth,
437 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
440 /* We are scanning "cpu" nodes only */
441 if (type == NULL || strcmp(type, "cpu") != 0)
444 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
446 /* pft_size[0] is the NUMA CEC cookie */
447 ppc64_pft_size = prop[1];
453 static unsigned long __init htab_get_table_size(void)
455 unsigned long mem_size, rnd_mem_size, pteg_count;
457 /* If hash size isn't already provided by the platform, we try to
458 * retrieve it from the device-tree. If it's not there neither, we
459 * calculate it now based on the total RAM size
461 if (ppc64_pft_size == 0)
462 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
464 return 1UL << ppc64_pft_size;
466 /* round mem_size up to next power of 2 */
467 mem_size = lmb_phys_mem_size();
468 rnd_mem_size = 1UL << __ilog2(mem_size);
469 if (rnd_mem_size < mem_size)
473 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
475 return pteg_count << 7;
478 #ifdef CONFIG_MEMORY_HOTPLUG
479 void create_section_mapping(unsigned long start, unsigned long end)
481 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
482 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
483 mmu_linear_psize, mmu_kernel_ssize));
486 int remove_section_mapping(unsigned long start, unsigned long end)
488 return htab_remove_mapping(start, end, mmu_linear_psize,
491 #endif /* CONFIG_MEMORY_HOTPLUG */
493 static inline void make_bl(unsigned int *insn_addr, void *func)
495 unsigned long funcp = *((unsigned long *)func);
496 int offset = funcp - (unsigned long)insn_addr;
498 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
499 flush_icache_range((unsigned long)insn_addr, 4+
500 (unsigned long)insn_addr);
503 static void __init htab_finish_init(void)
505 extern unsigned int *htab_call_hpte_insert1;
506 extern unsigned int *htab_call_hpte_insert2;
507 extern unsigned int *htab_call_hpte_remove;
508 extern unsigned int *htab_call_hpte_updatepp;
510 #ifdef CONFIG_PPC_HAS_HASH_64K
511 extern unsigned int *ht64_call_hpte_insert1;
512 extern unsigned int *ht64_call_hpte_insert2;
513 extern unsigned int *ht64_call_hpte_remove;
514 extern unsigned int *ht64_call_hpte_updatepp;
516 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
517 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
518 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
519 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
520 #endif /* CONFIG_PPC_HAS_HASH_64K */
522 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
523 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
524 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
525 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
528 void __init htab_initialize(void)
531 unsigned long pteg_count;
532 unsigned long mode_rw;
533 unsigned long base = 0, size = 0, limit;
536 DBG(" -> htab_initialize()\n");
538 /* Initialize segment sizes */
539 htab_init_seg_sizes();
541 /* Initialize page sizes */
542 htab_init_page_sizes();
544 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
545 mmu_kernel_ssize = MMU_SEGSIZE_1T;
546 mmu_highuser_ssize = MMU_SEGSIZE_1T;
547 printk(KERN_INFO "Using 1TB segments\n");
551 * Calculate the required size of the htab. We want the number of
552 * PTEGs to equal one half the number of real pages.
554 htab_size_bytes = htab_get_table_size();
555 pteg_count = htab_size_bytes >> 7;
557 htab_hash_mask = pteg_count - 1;
559 if (firmware_has_feature(FW_FEATURE_LPAR)) {
560 /* Using a hypervisor which owns the htab */
564 /* Find storage for the HPT. Must be contiguous in
565 * the absolute address space. On cell we want it to be
566 * in the first 2 Gig so we can use it for IOMMU hacks.
568 if (machine_is(cell))
573 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
575 DBG("Hash table allocated at %lx, size: %lx\n", table,
578 htab_address = abs_to_virt(table);
580 /* htab absolute addr + encoded htabsize */
581 _SDR1 = table + __ilog2(pteg_count) - 11;
583 /* Initialize the HPT with no entries */
584 memset((void *)table, 0, htab_size_bytes);
587 mtspr(SPRN_SDR1, _SDR1);
590 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
592 #ifdef CONFIG_DEBUG_PAGEALLOC
593 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
594 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
596 memset(linear_map_hash_slots, 0, linear_map_hash_count);
597 #endif /* CONFIG_DEBUG_PAGEALLOC */
599 /* On U3 based machines, we need to reserve the DART area and
600 * _NOT_ map it to avoid cache paradoxes as it's remapped non
604 /* create bolted the linear mapping in the hash table */
605 for (i=0; i < lmb.memory.cnt; i++) {
606 base = (unsigned long)__va(lmb.memory.region[i].base);
607 size = lmb.memory.region[i].size;
609 DBG("creating mapping for region: %lx : %lx\n", base, size);
611 #ifdef CONFIG_U3_DART
612 /* Do not map the DART space. Fortunately, it will be aligned
613 * in such a way that it will not cross two lmb regions and
614 * will fit within a single 16Mb page.
615 * The DART space is assumed to be a full 16Mb region even if
616 * we only use 2Mb of that space. We will use more of it later
617 * for AGP GART. We have to use a full 16Mb large page.
619 DBG("DART base: %lx\n", dart_tablebase);
621 if (dart_tablebase != 0 && dart_tablebase >= base
622 && dart_tablebase < (base + size)) {
623 unsigned long dart_table_end = dart_tablebase + 16 * MB;
624 if (base != dart_tablebase)
625 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
629 if ((base + size) > dart_table_end)
630 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
632 __pa(dart_table_end),
638 #endif /* CONFIG_U3_DART */
639 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
640 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
644 * If we have a memory_limit and we've allocated TCEs then we need to
645 * explicitly map the TCE area at the top of RAM. We also cope with the
646 * case that the TCEs start below memory_limit.
647 * tce_alloc_start/end are 16MB aligned so the mapping should work
648 * for either 4K or 16MB pages.
650 if (tce_alloc_start) {
651 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
652 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
654 if (base + size >= tce_alloc_start)
655 tce_alloc_start = base + size + 1;
657 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
658 __pa(tce_alloc_start), mode_rw,
659 mmu_linear_psize, mmu_kernel_ssize));
664 DBG(" <- htab_initialize()\n");
669 void htab_initialize_secondary(void)
671 if (!firmware_has_feature(FW_FEATURE_LPAR))
672 mtspr(SPRN_SDR1, _SDR1);
676 * Called by asm hashtable.S for doing lazy icache flush
678 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
682 if (!pfn_valid(pte_pfn(pte)))
685 page = pte_page(pte);
688 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
690 __flush_dcache_icache(page_address(page));
691 set_bit(PG_arch_1, &page->flags);
698 #ifdef CONFIG_PPC_MM_SLICES
699 unsigned int get_paca_psize(unsigned long addr)
701 unsigned long index, slices;
703 if (addr < SLICE_LOW_TOP) {
704 slices = get_paca()->context.low_slices_psize;
705 index = GET_LOW_SLICE_INDEX(addr);
707 slices = get_paca()->context.high_slices_psize;
708 index = GET_HIGH_SLICE_INDEX(addr);
710 return (slices >> (index * 4)) & 0xF;
714 unsigned int get_paca_psize(unsigned long addr)
716 return get_paca()->context.user_psize;
721 * Demote a segment to using 4k pages.
722 * For now this makes the whole process use 4k pages.
724 #ifdef CONFIG_PPC_64K_PAGES
725 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
727 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
729 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
730 #ifdef CONFIG_SPU_BASE
731 spu_flush_all_slbs(mm);
733 if (get_paca_psize(addr) != MMU_PAGE_4K) {
734 get_paca()->context = mm->context;
735 slb_flush_and_rebolt();
738 #endif /* CONFIG_PPC_64K_PAGES */
740 #ifdef CONFIG_PPC_SUBPAGE_PROT
742 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
743 * Userspace sets the subpage permissions using the subpage_prot system call.
745 * Result is 0: full permissions, _PAGE_RW: read-only,
746 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
748 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
750 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
754 if (ea >= spt->maxaddr)
756 if (ea < 0x100000000) {
757 /* addresses below 4GB use spt->low_prot */
758 sbpm = spt->low_prot;
760 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
764 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
767 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
769 /* extract 2-bit bitfield for this 4k subpage */
770 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
772 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
773 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
777 #else /* CONFIG_PPC_SUBPAGE_PROT */
778 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
786 * 1 - normal page fault
787 * -1 - critical hash insertion error
788 * -2 - access not permitted by subpage protection mechanism
790 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
794 struct mm_struct *mm;
797 int rc, user_region = 0, local = 0;
800 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
803 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
804 DBG_LOW(" out of pgtable range !\n");
808 /* Get region & vsid */
809 switch (REGION_ID(ea)) {
814 DBG_LOW(" user region with no mm !\n");
817 psize = get_slice_psize(mm, ea);
818 ssize = user_segment_size(ea);
819 vsid = get_vsid(mm->context.id, ea, ssize);
821 case VMALLOC_REGION_ID:
823 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
824 if (ea < VMALLOC_END)
825 psize = mmu_vmalloc_psize;
827 psize = mmu_io_psize;
828 ssize = mmu_kernel_ssize;
832 * Send the problem up to do_page_fault
836 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
843 /* Check CPU locality */
844 tmp = cpumask_of_cpu(smp_processor_id());
845 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
848 #ifdef CONFIG_HUGETLB_PAGE
849 /* Handle hugepage regions */
850 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
851 DBG_LOW(" -> huge page !\n");
852 return hash_huge_page(mm, access, ea, vsid, local, trap);
854 #endif /* CONFIG_HUGETLB_PAGE */
856 #ifndef CONFIG_PPC_64K_PAGES
857 /* If we use 4K pages and our psize is not 4K, then we are hitting
858 * a special driver mapping, we need to align the address before
861 if (psize != MMU_PAGE_4K)
862 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
863 #endif /* CONFIG_PPC_64K_PAGES */
865 /* Get PTE and page size from page tables */
866 ptep = find_linux_pte(pgdir, ea);
867 if (ptep == NULL || !pte_present(*ptep)) {
868 DBG_LOW(" no PTE !\n");
872 #ifndef CONFIG_PPC_64K_PAGES
873 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
875 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
876 pte_val(*(ptep + PTRS_PER_PTE)));
878 /* Pre-check access permissions (will be re-checked atomically
879 * in __hash_page_XX but this pre-check is a fast path
881 if (access & ~pte_val(*ptep)) {
882 DBG_LOW(" no access !\n");
886 /* Do actual hashing */
887 #ifdef CONFIG_PPC_64K_PAGES
888 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
889 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
890 demote_segment_4k(mm, ea);
894 /* If this PTE is non-cacheable and we have restrictions on
895 * using non cacheable large pages, then we switch to 4k
897 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
898 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
900 demote_segment_4k(mm, ea);
902 } else if (ea < VMALLOC_END) {
904 * some driver did a non-cacheable mapping
905 * in vmalloc space, so switch vmalloc
908 printk(KERN_ALERT "Reducing vmalloc segment "
909 "to 4kB pages because of "
910 "non-cacheable mapping\n");
911 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
912 #ifdef CONFIG_SPU_BASE
913 spu_flush_all_slbs(mm);
918 if (psize != get_paca_psize(ea)) {
919 get_paca()->context = mm->context;
920 slb_flush_and_rebolt();
922 } else if (get_paca()->vmalloc_sllp !=
923 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
924 get_paca()->vmalloc_sllp =
925 mmu_psize_defs[mmu_vmalloc_psize].sllp;
926 slb_vmalloc_update();
928 #endif /* CONFIG_PPC_64K_PAGES */
930 #ifdef CONFIG_PPC_HAS_HASH_64K
931 if (psize == MMU_PAGE_64K)
932 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
934 #endif /* CONFIG_PPC_HAS_HASH_64K */
936 int spp = subpage_protection(pgdir, ea);
940 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
944 #ifndef CONFIG_PPC_64K_PAGES
945 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
947 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
948 pte_val(*(ptep + PTRS_PER_PTE)));
950 DBG_LOW(" -> rc=%d\n", rc);
953 EXPORT_SYMBOL_GPL(hash_page);
955 void hash_preload(struct mm_struct *mm, unsigned long ea,
956 unsigned long access, unsigned long trap)
966 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
968 #ifdef CONFIG_PPC_MM_SLICES
969 /* We only prefault standard pages for now */
970 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
974 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
975 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
977 /* Get Linux PTE if available */
981 ptep = find_linux_pte(pgdir, ea);
985 #ifdef CONFIG_PPC_64K_PAGES
986 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
987 * a 64K kernel), then we don't preload, hash_page() will take
988 * care of it once we actually try to access the page.
989 * That way we don't have to duplicate all of the logic for segment
990 * page size demotion here
992 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
994 #endif /* CONFIG_PPC_64K_PAGES */
997 ssize = user_segment_size(ea);
998 vsid = get_vsid(mm->context.id, ea, ssize);
1000 /* Hash doesn't like irqs */
1001 local_irq_save(flags);
1003 /* Is that local to this CPU ? */
1004 mask = cpumask_of_cpu(smp_processor_id());
1005 if (cpus_equal(mm->cpu_vm_mask, mask))
1009 #ifdef CONFIG_PPC_HAS_HASH_64K
1010 if (mm->context.user_psize == MMU_PAGE_64K)
1011 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1013 #endif /* CONFIG_PPC_HAS_HASH_64K */
1014 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1015 subpage_protection(pgdir, ea));
1017 local_irq_restore(flags);
1020 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1021 * do not forget to update the assembly call site !
1023 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1026 unsigned long hash, index, shift, hidx, slot;
1028 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1029 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1030 hash = hpt_hash(va, shift, ssize);
1031 hidx = __rpte_to_hidx(pte, index);
1032 if (hidx & _PTEIDX_SECONDARY)
1034 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1035 slot += hidx & _PTEIDX_GROUP_IX;
1036 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
1037 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1038 } pte_iterate_hashed_end();
1041 void flush_hash_range(unsigned long number, int local)
1043 if (ppc_md.flush_hash_range)
1044 ppc_md.flush_hash_range(number, local);
1047 struct ppc64_tlb_batch *batch =
1048 &__get_cpu_var(ppc64_tlb_batch);
1050 for (i = 0; i < number; i++)
1051 flush_hash_page(batch->vaddr[i], batch->pte[i],
1052 batch->psize, batch->ssize, local);
1057 * low_hash_fault is called when we the low level hash code failed
1058 * to instert a PTE due to an hypervisor error
1060 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1062 if (user_mode(regs)) {
1063 #ifdef CONFIG_PPC_SUBPAGE_PROT
1065 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1068 _exception(SIGBUS, regs, BUS_ADRERR, address);
1070 bad_page_fault(regs, address, SIGBUS);
1073 #ifdef CONFIG_DEBUG_PAGEALLOC
1074 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1076 unsigned long hash, hpteg;
1077 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1078 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1079 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
1080 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
1083 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1084 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1086 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1087 mode, HPTE_V_BOLTED,
1088 mmu_linear_psize, mmu_kernel_ssize);
1090 spin_lock(&linear_map_hash_lock);
1091 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1092 linear_map_hash_slots[lmi] = ret | 0x80;
1093 spin_unlock(&linear_map_hash_lock);
1096 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1098 unsigned long hash, hidx, slot;
1099 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1100 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1102 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1103 spin_lock(&linear_map_hash_lock);
1104 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1105 hidx = linear_map_hash_slots[lmi] & 0x7f;
1106 linear_map_hash_slots[lmi] = 0;
1107 spin_unlock(&linear_map_hash_lock);
1108 if (hidx & _PTEIDX_SECONDARY)
1110 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1111 slot += hidx & _PTEIDX_GROUP_IX;
1112 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1115 void kernel_map_pages(struct page *page, int numpages, int enable)
1117 unsigned long flags, vaddr, lmi;
1120 local_irq_save(flags);
1121 for (i = 0; i < numpages; i++, page++) {
1122 vaddr = (unsigned long)page_address(page);
1123 lmi = __pa(vaddr) >> PAGE_SHIFT;
1124 if (lmi >= linear_map_hash_count)
1127 kernel_map_linear_page(vaddr, lmi);
1129 kernel_unmap_linear_page(vaddr, lmi);
1131 local_irq_restore(flags);
1133 #endif /* CONFIG_DEBUG_PAGEALLOC */