2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
73 * Note: pte --> Linux PTE
74 * HPTE --> PowerPC Hashed Page Table Entry
77 * htab_initialize is called with the MMU off (of course), but
78 * the kernel has been copied down to zero so it can directly
79 * reference global data. At this point it is very difficult
80 * to print debug info.
85 extern unsigned long dart_tablebase;
86 #endif /* CONFIG_U3_DART */
88 static unsigned long _SDR1;
89 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91 struct hash_pte *htab_address;
92 unsigned long htab_size_bytes;
93 unsigned long htab_hash_mask;
94 int mmu_linear_psize = MMU_PAGE_4K;
95 int mmu_virtual_psize = MMU_PAGE_4K;
96 int mmu_vmalloc_psize = MMU_PAGE_4K;
97 #ifdef CONFIG_SPARSEMEM_VMEMMAP
98 int mmu_vmemmap_psize = MMU_PAGE_4K;
100 int mmu_io_psize = MMU_PAGE_4K;
101 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
102 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
103 u16 mmu_slb_size = 64;
104 #ifdef CONFIG_HUGETLB_PAGE
105 int mmu_huge_psize = MMU_PAGE_16M;
106 unsigned int HPAGE_SHIFT;
108 #ifdef CONFIG_PPC_64K_PAGES
109 int mmu_ci_restrictions;
111 #ifdef CONFIG_DEBUG_PAGEALLOC
112 static u8 *linear_map_hash_slots;
113 static unsigned long linear_map_hash_count;
114 static DEFINE_SPINLOCK(linear_map_hash_lock);
115 #endif /* CONFIG_DEBUG_PAGEALLOC */
117 /* There are definitions of page sizes arrays to be used when none
118 * is provided by the firmware.
121 /* Pre-POWER4 CPUs (4k pages only)
123 struct mmu_psize_def mmu_psize_defaults_old[] = {
133 /* POWER4, GPUL, POWER5
135 * Support for 16Mb large pages
137 struct mmu_psize_def mmu_psize_defaults_gp[] = {
155 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
156 unsigned long pstart, unsigned long mode,
157 int psize, int ssize)
159 unsigned long vaddr, paddr;
160 unsigned int step, shift;
161 unsigned long tmp_mode;
164 shift = mmu_psize_defs[psize].shift;
167 for (vaddr = vstart, paddr = pstart; vaddr < vend;
168 vaddr += step, paddr += step) {
169 unsigned long hash, hpteg;
170 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
171 unsigned long va = hpt_va(vaddr, vsid, ssize);
175 /* Make non-kernel text non-executable */
176 if (!in_kernel_text(vaddr))
177 tmp_mode = mode | HPTE_R_N;
179 hash = hpt_hash(va, shift, ssize);
180 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
182 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
184 BUG_ON(!ppc_md.hpte_insert);
185 ret = ppc_md.hpte_insert(hpteg, va, paddr,
186 tmp_mode, HPTE_V_BOLTED, psize, ssize);
190 #ifdef CONFIG_DEBUG_PAGEALLOC
191 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
192 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
193 #endif /* CONFIG_DEBUG_PAGEALLOC */
195 return ret < 0 ? ret : 0;
198 #ifdef CONFIG_MEMORY_HOTPLUG
199 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
200 int psize, int ssize)
203 unsigned int step, shift;
205 shift = mmu_psize_defs[psize].shift;
208 if (!ppc_md.hpte_removebolted) {
209 printk(KERN_WARNING "Platform doesn't implement "
210 "hpte_removebolted\n");
214 for (vaddr = vstart; vaddr < vend; vaddr += step)
215 ppc_md.hpte_removebolted(vaddr, psize, ssize);
219 #endif /* CONFIG_MEMORY_HOTPLUG */
221 static int __init htab_dt_scan_seg_sizes(unsigned long node,
222 const char *uname, int depth,
225 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
227 unsigned long size = 0;
229 /* We are scanning "cpu" nodes only */
230 if (type == NULL || strcmp(type, "cpu") != 0)
233 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
237 for (; size >= 4; size -= 4, ++prop) {
239 DBG("1T segment support detected\n");
240 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
244 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
248 static void __init htab_init_seg_sizes(void)
250 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
253 static int __init htab_dt_scan_page_sizes(unsigned long node,
254 const char *uname, int depth,
257 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
259 unsigned long size = 0;
261 /* We are scanning "cpu" nodes only */
262 if (type == NULL || strcmp(type, "cpu") != 0)
265 prop = (u32 *)of_get_flat_dt_prop(node,
266 "ibm,segment-page-sizes", &size);
268 DBG("Page sizes from device-tree:\n");
270 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
272 unsigned int shift = prop[0];
273 unsigned int slbenc = prop[1];
274 unsigned int lpnum = prop[2];
275 unsigned int lpenc = 0;
276 struct mmu_psize_def *def;
279 size -= 3; prop += 3;
280 while(size > 0 && lpnum) {
281 if (prop[0] == shift)
283 prop += 2; size -= 2;
298 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
306 def = &mmu_psize_defs[idx];
311 def->avpnm = (1 << (shift - 23)) - 1;
314 /* We don't know for sure what's up with tlbiel, so
315 * for now we only set it for 4K and 64K pages
317 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
322 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
323 "tlbiel=%d, penc=%d\n",
324 idx, shift, def->sllp, def->avpnm, def->tlbiel,
332 static void __init htab_init_page_sizes(void)
336 /* Default to 4K pages only */
337 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
338 sizeof(mmu_psize_defaults_old));
341 * Try to find the available page sizes in the device-tree
343 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
344 if (rc != 0) /* Found */
348 * Not in the device-tree, let's fallback on known size
349 * list for 16M capable GP & GR
351 if (cpu_has_feature(CPU_FTR_16M_PAGE))
352 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
353 sizeof(mmu_psize_defaults_gp));
355 #ifndef CONFIG_DEBUG_PAGEALLOC
357 * Pick a size for the linear mapping. Currently, we only support
358 * 16M, 1M and 4K which is the default
360 if (mmu_psize_defs[MMU_PAGE_16M].shift)
361 mmu_linear_psize = MMU_PAGE_16M;
362 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
363 mmu_linear_psize = MMU_PAGE_1M;
364 #endif /* CONFIG_DEBUG_PAGEALLOC */
366 #ifdef CONFIG_PPC_64K_PAGES
368 * Pick a size for the ordinary pages. Default is 4K, we support
369 * 64K for user mappings and vmalloc if supported by the processor.
370 * We only use 64k for ioremap if the processor
371 * (and firmware) support cache-inhibited large pages.
372 * If not, we use 4k and set mmu_ci_restrictions so that
373 * hash_page knows to switch processes that use cache-inhibited
374 * mappings to 4k pages.
376 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
377 mmu_virtual_psize = MMU_PAGE_64K;
378 mmu_vmalloc_psize = MMU_PAGE_64K;
379 if (mmu_linear_psize == MMU_PAGE_4K)
380 mmu_linear_psize = MMU_PAGE_64K;
381 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
383 * Don't use 64k pages for ioremap on pSeries, since
384 * that would stop us accessing the HEA ethernet.
386 if (!machine_is(pseries))
387 mmu_io_psize = MMU_PAGE_64K;
389 mmu_ci_restrictions = 1;
391 #endif /* CONFIG_PPC_64K_PAGES */
393 #ifdef CONFIG_SPARSEMEM_VMEMMAP
394 /* We try to use 16M pages for vmemmap if that is supported
395 * and we have at least 1G of RAM at boot
397 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
398 lmb_phys_mem_size() >= 0x40000000)
399 mmu_vmemmap_psize = MMU_PAGE_16M;
400 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
401 mmu_vmemmap_psize = MMU_PAGE_64K;
403 mmu_vmemmap_psize = MMU_PAGE_4K;
404 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
406 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
407 "virtual = %d, io = %d"
408 #ifdef CONFIG_SPARSEMEM_VMEMMAP
412 mmu_psize_defs[mmu_linear_psize].shift,
413 mmu_psize_defs[mmu_virtual_psize].shift,
414 mmu_psize_defs[mmu_io_psize].shift
415 #ifdef CONFIG_SPARSEMEM_VMEMMAP
416 ,mmu_psize_defs[mmu_vmemmap_psize].shift
420 #ifdef CONFIG_HUGETLB_PAGE
421 /* Init large page size. Currently, we pick 16M or 1M depending
422 * on what is available
424 if (mmu_psize_defs[MMU_PAGE_16M].shift)
425 set_huge_psize(MMU_PAGE_16M);
426 /* With 4k/4level pagetables, we can't (for now) cope with a
427 * huge page size < PMD_SIZE */
428 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
429 set_huge_psize(MMU_PAGE_1M);
430 #endif /* CONFIG_HUGETLB_PAGE */
433 static int __init htab_dt_scan_pftsize(unsigned long node,
434 const char *uname, int depth,
437 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
440 /* We are scanning "cpu" nodes only */
441 if (type == NULL || strcmp(type, "cpu") != 0)
444 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
446 /* pft_size[0] is the NUMA CEC cookie */
447 ppc64_pft_size = prop[1];
453 static unsigned long __init htab_get_table_size(void)
455 unsigned long mem_size, rnd_mem_size, pteg_count;
457 /* If hash size isn't already provided by the platform, we try to
458 * retrieve it from the device-tree. If it's not there neither, we
459 * calculate it now based on the total RAM size
461 if (ppc64_pft_size == 0)
462 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
464 return 1UL << ppc64_pft_size;
466 /* round mem_size up to next power of 2 */
467 mem_size = lmb_phys_mem_size();
468 rnd_mem_size = 1UL << __ilog2(mem_size);
469 if (rnd_mem_size < mem_size)
473 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
475 return pteg_count << 7;
478 #ifdef CONFIG_MEMORY_HOTPLUG
479 void create_section_mapping(unsigned long start, unsigned long end)
481 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
482 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
483 mmu_linear_psize, mmu_kernel_ssize));
486 int remove_section_mapping(unsigned long start, unsigned long end)
488 return htab_remove_mapping(start, end, mmu_linear_psize,
491 #endif /* CONFIG_MEMORY_HOTPLUG */
493 static inline void make_bl(unsigned int *insn_addr, void *func)
495 unsigned long funcp = *((unsigned long *)func);
496 int offset = funcp - (unsigned long)insn_addr;
498 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
499 flush_icache_range((unsigned long)insn_addr, 4+
500 (unsigned long)insn_addr);
503 static void __init htab_finish_init(void)
505 extern unsigned int *htab_call_hpte_insert1;
506 extern unsigned int *htab_call_hpte_insert2;
507 extern unsigned int *htab_call_hpte_remove;
508 extern unsigned int *htab_call_hpte_updatepp;
510 #ifdef CONFIG_PPC_HAS_HASH_64K
511 extern unsigned int *ht64_call_hpte_insert1;
512 extern unsigned int *ht64_call_hpte_insert2;
513 extern unsigned int *ht64_call_hpte_remove;
514 extern unsigned int *ht64_call_hpte_updatepp;
516 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
517 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
518 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
519 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
520 #endif /* CONFIG_PPC_HAS_HASH_64K */
522 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
523 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
524 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
525 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
528 void __init htab_initialize(void)
531 unsigned long pteg_count;
532 unsigned long mode_rw;
533 unsigned long base = 0, size = 0, limit;
536 extern unsigned long tce_alloc_start, tce_alloc_end;
538 DBG(" -> htab_initialize()\n");
540 /* Initialize segment sizes */
541 htab_init_seg_sizes();
543 /* Initialize page sizes */
544 htab_init_page_sizes();
546 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
547 mmu_kernel_ssize = MMU_SEGSIZE_1T;
548 mmu_highuser_ssize = MMU_SEGSIZE_1T;
549 printk(KERN_INFO "Using 1TB segments\n");
553 * Calculate the required size of the htab. We want the number of
554 * PTEGs to equal one half the number of real pages.
556 htab_size_bytes = htab_get_table_size();
557 pteg_count = htab_size_bytes >> 7;
559 htab_hash_mask = pteg_count - 1;
561 if (firmware_has_feature(FW_FEATURE_LPAR)) {
562 /* Using a hypervisor which owns the htab */
566 /* Find storage for the HPT. Must be contiguous in
567 * the absolute address space. On cell we want it to be
568 * in the first 2 Gig so we can use it for IOMMU hacks.
570 if (machine_is(cell))
575 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
577 DBG("Hash table allocated at %lx, size: %lx\n", table,
580 htab_address = abs_to_virt(table);
582 /* htab absolute addr + encoded htabsize */
583 _SDR1 = table + __ilog2(pteg_count) - 11;
585 /* Initialize the HPT with no entries */
586 memset((void *)table, 0, htab_size_bytes);
589 mtspr(SPRN_SDR1, _SDR1);
592 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
594 #ifdef CONFIG_DEBUG_PAGEALLOC
595 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
596 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
598 memset(linear_map_hash_slots, 0, linear_map_hash_count);
599 #endif /* CONFIG_DEBUG_PAGEALLOC */
601 /* On U3 based machines, we need to reserve the DART area and
602 * _NOT_ map it to avoid cache paradoxes as it's remapped non
606 /* create bolted the linear mapping in the hash table */
607 for (i=0; i < lmb.memory.cnt; i++) {
608 base = (unsigned long)__va(lmb.memory.region[i].base);
609 size = lmb.memory.region[i].size;
611 DBG("creating mapping for region: %lx : %lx\n", base, size);
613 #ifdef CONFIG_U3_DART
614 /* Do not map the DART space. Fortunately, it will be aligned
615 * in such a way that it will not cross two lmb regions and
616 * will fit within a single 16Mb page.
617 * The DART space is assumed to be a full 16Mb region even if
618 * we only use 2Mb of that space. We will use more of it later
619 * for AGP GART. We have to use a full 16Mb large page.
621 DBG("DART base: %lx\n", dart_tablebase);
623 if (dart_tablebase != 0 && dart_tablebase >= base
624 && dart_tablebase < (base + size)) {
625 unsigned long dart_table_end = dart_tablebase + 16 * MB;
626 if (base != dart_tablebase)
627 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
631 if ((base + size) > dart_table_end)
632 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
634 __pa(dart_table_end),
640 #endif /* CONFIG_U3_DART */
641 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
642 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
646 * If we have a memory_limit and we've allocated TCEs then we need to
647 * explicitly map the TCE area at the top of RAM. We also cope with the
648 * case that the TCEs start below memory_limit.
649 * tce_alloc_start/end are 16MB aligned so the mapping should work
650 * for either 4K or 16MB pages.
652 if (tce_alloc_start) {
653 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
654 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
656 if (base + size >= tce_alloc_start)
657 tce_alloc_start = base + size + 1;
659 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
660 __pa(tce_alloc_start), mode_rw,
661 mmu_linear_psize, mmu_kernel_ssize));
666 DBG(" <- htab_initialize()\n");
671 void htab_initialize_secondary(void)
673 if (!firmware_has_feature(FW_FEATURE_LPAR))
674 mtspr(SPRN_SDR1, _SDR1);
678 * Called by asm hashtable.S for doing lazy icache flush
680 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
684 if (!pfn_valid(pte_pfn(pte)))
687 page = pte_page(pte);
690 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
692 __flush_dcache_icache(page_address(page));
693 set_bit(PG_arch_1, &page->flags);
701 * Demote a segment to using 4k pages.
702 * For now this makes the whole process use 4k pages.
704 #ifdef CONFIG_PPC_64K_PAGES
705 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
707 if (mm->context.user_psize == MMU_PAGE_4K)
709 slice_set_user_psize(mm, MMU_PAGE_4K);
710 #ifdef CONFIG_SPU_BASE
711 spu_flush_all_slbs(mm);
713 if (get_paca()->context.user_psize != MMU_PAGE_4K) {
714 get_paca()->context = mm->context;
715 slb_flush_and_rebolt();
718 #endif /* CONFIG_PPC_64K_PAGES */
720 #ifdef CONFIG_PPC_SUBPAGE_PROT
722 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
723 * Userspace sets the subpage permissions using the subpage_prot system call.
725 * Result is 0: full permissions, _PAGE_RW: read-only,
726 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
728 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
730 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
734 if (ea >= spt->maxaddr)
736 if (ea < 0x100000000) {
737 /* addresses below 4GB use spt->low_prot */
738 sbpm = spt->low_prot;
740 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
744 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
747 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
749 /* extract 2-bit bitfield for this 4k subpage */
750 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
752 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
753 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
757 #else /* CONFIG_PPC_SUBPAGE_PROT */
758 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
766 * 1 - normal page fault
767 * -1 - critical hash insertion error
768 * -2 - access not permitted by subpage protection mechanism
770 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
774 struct mm_struct *mm;
777 int rc, user_region = 0, local = 0;
780 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
783 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
784 DBG_LOW(" out of pgtable range !\n");
788 /* Get region & vsid */
789 switch (REGION_ID(ea)) {
794 DBG_LOW(" user region with no mm !\n");
797 #ifdef CONFIG_PPC_MM_SLICES
798 psize = get_slice_psize(mm, ea);
800 psize = mm->context.user_psize;
802 ssize = user_segment_size(ea);
803 vsid = get_vsid(mm->context.id, ea, ssize);
805 case VMALLOC_REGION_ID:
807 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
808 if (ea < VMALLOC_END)
809 psize = mmu_vmalloc_psize;
811 psize = mmu_io_psize;
812 ssize = mmu_kernel_ssize;
816 * Send the problem up to do_page_fault
820 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
827 /* Check CPU locality */
828 tmp = cpumask_of_cpu(smp_processor_id());
829 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
832 #ifdef CONFIG_HUGETLB_PAGE
833 /* Handle hugepage regions */
834 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
835 DBG_LOW(" -> huge page !\n");
836 return hash_huge_page(mm, access, ea, vsid, local, trap);
838 #endif /* CONFIG_HUGETLB_PAGE */
840 #ifndef CONFIG_PPC_64K_PAGES
841 /* If we use 4K pages and our psize is not 4K, then we are hitting
842 * a special driver mapping, we need to align the address before
845 if (psize != MMU_PAGE_4K)
846 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
847 #endif /* CONFIG_PPC_64K_PAGES */
849 /* Get PTE and page size from page tables */
850 ptep = find_linux_pte(pgdir, ea);
851 if (ptep == NULL || !pte_present(*ptep)) {
852 DBG_LOW(" no PTE !\n");
856 #ifndef CONFIG_PPC_64K_PAGES
857 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
859 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
860 pte_val(*(ptep + PTRS_PER_PTE)));
862 /* Pre-check access permissions (will be re-checked atomically
863 * in __hash_page_XX but this pre-check is a fast path
865 if (access & ~pte_val(*ptep)) {
866 DBG_LOW(" no access !\n");
870 /* Do actual hashing */
871 #ifdef CONFIG_PPC_64K_PAGES
872 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
873 if (pte_val(*ptep) & _PAGE_4K_PFN) {
874 demote_segment_4k(mm, ea);
878 /* If this PTE is non-cacheable and we have restrictions on
879 * using non cacheable large pages, then we switch to 4k
881 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
882 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
884 demote_segment_4k(mm, ea);
886 } else if (ea < VMALLOC_END) {
888 * some driver did a non-cacheable mapping
889 * in vmalloc space, so switch vmalloc
892 printk(KERN_ALERT "Reducing vmalloc segment "
893 "to 4kB pages because of "
894 "non-cacheable mapping\n");
895 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
896 #ifdef CONFIG_SPU_BASE
897 spu_flush_all_slbs(mm);
902 if (psize != get_paca()->context.user_psize) {
903 get_paca()->context = mm->context;
904 slb_flush_and_rebolt();
906 } else if (get_paca()->vmalloc_sllp !=
907 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
908 get_paca()->vmalloc_sllp =
909 mmu_psize_defs[mmu_vmalloc_psize].sllp;
910 slb_vmalloc_update();
912 #endif /* CONFIG_PPC_64K_PAGES */
914 #ifdef CONFIG_PPC_HAS_HASH_64K
915 if (psize == MMU_PAGE_64K)
916 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
918 #endif /* CONFIG_PPC_HAS_HASH_64K */
920 int spp = subpage_protection(pgdir, ea);
924 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
928 #ifndef CONFIG_PPC_64K_PAGES
929 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
931 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
932 pte_val(*(ptep + PTRS_PER_PTE)));
934 DBG_LOW(" -> rc=%d\n", rc);
937 EXPORT_SYMBOL_GPL(hash_page);
939 void hash_preload(struct mm_struct *mm, unsigned long ea,
940 unsigned long access, unsigned long trap)
950 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
952 #ifdef CONFIG_PPC_MM_SLICES
953 /* We only prefault standard pages for now */
954 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
958 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
959 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
961 /* Get Linux PTE if available */
965 ptep = find_linux_pte(pgdir, ea);
969 #ifdef CONFIG_PPC_64K_PAGES
970 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
971 * a 64K kernel), then we don't preload, hash_page() will take
972 * care of it once we actually try to access the page.
973 * That way we don't have to duplicate all of the logic for segment
974 * page size demotion here
976 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
978 #endif /* CONFIG_PPC_64K_PAGES */
981 ssize = user_segment_size(ea);
982 vsid = get_vsid(mm->context.id, ea, ssize);
984 /* Hash doesn't like irqs */
985 local_irq_save(flags);
987 /* Is that local to this CPU ? */
988 mask = cpumask_of_cpu(smp_processor_id());
989 if (cpus_equal(mm->cpu_vm_mask, mask))
993 #ifdef CONFIG_PPC_HAS_HASH_64K
994 if (mm->context.user_psize == MMU_PAGE_64K)
995 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
997 #endif /* CONFIG_PPC_HAS_HASH_64K */
998 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
999 subpage_protection(pgdir, ea));
1001 local_irq_restore(flags);
1004 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1005 * do not forget to update the assembly call site !
1007 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1010 unsigned long hash, index, shift, hidx, slot;
1012 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1013 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1014 hash = hpt_hash(va, shift, ssize);
1015 hidx = __rpte_to_hidx(pte, index);
1016 if (hidx & _PTEIDX_SECONDARY)
1018 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1019 slot += hidx & _PTEIDX_GROUP_IX;
1020 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
1021 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1022 } pte_iterate_hashed_end();
1025 void flush_hash_range(unsigned long number, int local)
1027 if (ppc_md.flush_hash_range)
1028 ppc_md.flush_hash_range(number, local);
1031 struct ppc64_tlb_batch *batch =
1032 &__get_cpu_var(ppc64_tlb_batch);
1034 for (i = 0; i < number; i++)
1035 flush_hash_page(batch->vaddr[i], batch->pte[i],
1036 batch->psize, batch->ssize, local);
1041 * low_hash_fault is called when we the low level hash code failed
1042 * to instert a PTE due to an hypervisor error
1044 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1046 if (user_mode(regs)) {
1047 #ifdef CONFIG_PPC_SUBPAGE_PROT
1049 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1052 _exception(SIGBUS, regs, BUS_ADRERR, address);
1054 bad_page_fault(regs, address, SIGBUS);
1057 #ifdef CONFIG_DEBUG_PAGEALLOC
1058 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1060 unsigned long hash, hpteg;
1061 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1062 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1063 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
1064 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
1067 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1068 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1070 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1071 mode, HPTE_V_BOLTED,
1072 mmu_linear_psize, mmu_kernel_ssize);
1074 spin_lock(&linear_map_hash_lock);
1075 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1076 linear_map_hash_slots[lmi] = ret | 0x80;
1077 spin_unlock(&linear_map_hash_lock);
1080 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1082 unsigned long hash, hidx, slot;
1083 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1084 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1086 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1087 spin_lock(&linear_map_hash_lock);
1088 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1089 hidx = linear_map_hash_slots[lmi] & 0x7f;
1090 linear_map_hash_slots[lmi] = 0;
1091 spin_unlock(&linear_map_hash_lock);
1092 if (hidx & _PTEIDX_SECONDARY)
1094 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1095 slot += hidx & _PTEIDX_GROUP_IX;
1096 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1099 void kernel_map_pages(struct page *page, int numpages, int enable)
1101 unsigned long flags, vaddr, lmi;
1104 local_irq_save(flags);
1105 for (i = 0; i < numpages; i++, page++) {
1106 vaddr = (unsigned long)page_address(page);
1107 lmi = __pa(vaddr) >> PAGE_SHIFT;
1108 if (lmi >= linear_map_hash_count)
1111 kernel_map_linear_page(vaddr, lmi);
1113 kernel_unmap_linear_page(vaddr, lmi);
1115 local_irq_restore(flags);
1117 #endif /* CONFIG_DEBUG_PAGEALLOC */