2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
73 * Note: pte --> Linux PTE
74 * HPTE --> PowerPC Hashed Page Table Entry
77 * htab_initialize is called with the MMU off (of course), but
78 * the kernel has been copied down to zero so it can directly
79 * reference global data. At this point it is very difficult
80 * to print debug info.
85 extern unsigned long dart_tablebase;
86 #endif /* CONFIG_U3_DART */
88 static unsigned long _SDR1;
89 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91 struct hash_pte *htab_address;
92 unsigned long htab_size_bytes;
93 unsigned long htab_hash_mask;
94 int mmu_linear_psize = MMU_PAGE_4K;
95 int mmu_virtual_psize = MMU_PAGE_4K;
96 int mmu_vmalloc_psize = MMU_PAGE_4K;
97 int mmu_io_psize = MMU_PAGE_4K;
98 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
99 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
100 u16 mmu_slb_size = 64;
101 #ifdef CONFIG_HUGETLB_PAGE
102 int mmu_huge_psize = MMU_PAGE_16M;
103 unsigned int HPAGE_SHIFT;
105 #ifdef CONFIG_PPC_64K_PAGES
106 int mmu_ci_restrictions;
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 static u8 *linear_map_hash_slots;
110 static unsigned long linear_map_hash_count;
111 static DEFINE_SPINLOCK(linear_map_hash_lock);
112 #endif /* CONFIG_DEBUG_PAGEALLOC */
114 /* There are definitions of page sizes arrays to be used when none
115 * is provided by the firmware.
118 /* Pre-POWER4 CPUs (4k pages only)
120 struct mmu_psize_def mmu_psize_defaults_old[] = {
130 /* POWER4, GPUL, POWER5
132 * Support for 16Mb large pages
134 struct mmu_psize_def mmu_psize_defaults_gp[] = {
152 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
153 unsigned long pstart, unsigned long mode,
154 int psize, int ssize)
156 unsigned long vaddr, paddr;
157 unsigned int step, shift;
158 unsigned long tmp_mode;
161 shift = mmu_psize_defs[psize].shift;
164 for (vaddr = vstart, paddr = pstart; vaddr < vend;
165 vaddr += step, paddr += step) {
166 unsigned long hash, hpteg;
167 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
168 unsigned long va = hpt_va(vaddr, vsid, ssize);
172 /* Make non-kernel text non-executable */
173 if (!in_kernel_text(vaddr))
174 tmp_mode = mode | HPTE_R_N;
176 hash = hpt_hash(va, shift, ssize);
177 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
179 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
181 BUG_ON(!ppc_md.hpte_insert);
182 ret = ppc_md.hpte_insert(hpteg, va, paddr,
183 tmp_mode, HPTE_V_BOLTED, psize, ssize);
187 #ifdef CONFIG_DEBUG_PAGEALLOC
188 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
189 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
190 #endif /* CONFIG_DEBUG_PAGEALLOC */
192 return ret < 0 ? ret : 0;
195 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
196 int psize, int ssize)
199 unsigned int step, shift;
201 shift = mmu_psize_defs[psize].shift;
204 if (!ppc_md.hpte_removebolted) {
205 printk(KERN_WARNING "Platform doesn't implement "
206 "hpte_removebolted\n");
210 for (vaddr = vstart; vaddr < vend; vaddr += step)
211 ppc_md.hpte_removebolted(vaddr, psize, ssize);
216 static int __init htab_dt_scan_seg_sizes(unsigned long node,
217 const char *uname, int depth,
220 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
222 unsigned long size = 0;
224 /* We are scanning "cpu" nodes only */
225 if (type == NULL || strcmp(type, "cpu") != 0)
228 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
232 for (; size >= 4; size -= 4, ++prop) {
234 DBG("1T segment support detected\n");
235 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
239 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
243 static void __init htab_init_seg_sizes(void)
245 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
248 static int __init htab_dt_scan_page_sizes(unsigned long node,
249 const char *uname, int depth,
252 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
254 unsigned long size = 0;
256 /* We are scanning "cpu" nodes only */
257 if (type == NULL || strcmp(type, "cpu") != 0)
260 prop = (u32 *)of_get_flat_dt_prop(node,
261 "ibm,segment-page-sizes", &size);
263 DBG("Page sizes from device-tree:\n");
265 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
267 unsigned int shift = prop[0];
268 unsigned int slbenc = prop[1];
269 unsigned int lpnum = prop[2];
270 unsigned int lpenc = 0;
271 struct mmu_psize_def *def;
274 size -= 3; prop += 3;
275 while(size > 0 && lpnum) {
276 if (prop[0] == shift)
278 prop += 2; size -= 2;
293 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
301 def = &mmu_psize_defs[idx];
306 def->avpnm = (1 << (shift - 23)) - 1;
309 /* We don't know for sure what's up with tlbiel, so
310 * for now we only set it for 4K and 64K pages
312 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
317 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
318 "tlbiel=%d, penc=%d\n",
319 idx, shift, def->sllp, def->avpnm, def->tlbiel,
327 static void __init htab_init_page_sizes(void)
331 /* Default to 4K pages only */
332 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
333 sizeof(mmu_psize_defaults_old));
336 * Try to find the available page sizes in the device-tree
338 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
339 if (rc != 0) /* Found */
343 * Not in the device-tree, let's fallback on known size
344 * list for 16M capable GP & GR
346 if (cpu_has_feature(CPU_FTR_16M_PAGE))
347 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
348 sizeof(mmu_psize_defaults_gp));
350 #ifndef CONFIG_DEBUG_PAGEALLOC
352 * Pick a size for the linear mapping. Currently, we only support
353 * 16M, 1M and 4K which is the default
355 if (mmu_psize_defs[MMU_PAGE_16M].shift)
356 mmu_linear_psize = MMU_PAGE_16M;
357 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
358 mmu_linear_psize = MMU_PAGE_1M;
359 #endif /* CONFIG_DEBUG_PAGEALLOC */
361 #ifdef CONFIG_PPC_64K_PAGES
363 * Pick a size for the ordinary pages. Default is 4K, we support
364 * 64K for user mappings and vmalloc if supported by the processor.
365 * We only use 64k for ioremap if the processor
366 * (and firmware) support cache-inhibited large pages.
367 * If not, we use 4k and set mmu_ci_restrictions so that
368 * hash_page knows to switch processes that use cache-inhibited
369 * mappings to 4k pages.
371 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
372 mmu_virtual_psize = MMU_PAGE_64K;
373 mmu_vmalloc_psize = MMU_PAGE_64K;
374 if (mmu_linear_psize == MMU_PAGE_4K)
375 mmu_linear_psize = MMU_PAGE_64K;
376 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
378 * Don't use 64k pages for ioremap on pSeries, since
379 * that would stop us accessing the HEA ethernet.
381 if (!machine_is(pseries))
382 mmu_io_psize = MMU_PAGE_64K;
384 mmu_ci_restrictions = 1;
386 #endif /* CONFIG_PPC_64K_PAGES */
388 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
389 "virtual = %d, io = %d\n",
390 mmu_psize_defs[mmu_linear_psize].shift,
391 mmu_psize_defs[mmu_virtual_psize].shift,
392 mmu_psize_defs[mmu_io_psize].shift);
394 #ifdef CONFIG_HUGETLB_PAGE
395 /* Init large page size. Currently, we pick 16M or 1M depending
396 * on what is available
398 if (mmu_psize_defs[MMU_PAGE_16M].shift)
399 set_huge_psize(MMU_PAGE_16M);
400 /* With 4k/4level pagetables, we can't (for now) cope with a
401 * huge page size < PMD_SIZE */
402 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
403 set_huge_psize(MMU_PAGE_1M);
404 #endif /* CONFIG_HUGETLB_PAGE */
407 static int __init htab_dt_scan_pftsize(unsigned long node,
408 const char *uname, int depth,
411 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
414 /* We are scanning "cpu" nodes only */
415 if (type == NULL || strcmp(type, "cpu") != 0)
418 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
420 /* pft_size[0] is the NUMA CEC cookie */
421 ppc64_pft_size = prop[1];
427 static unsigned long __init htab_get_table_size(void)
429 unsigned long mem_size, rnd_mem_size, pteg_count;
431 /* If hash size isn't already provided by the platform, we try to
432 * retrieve it from the device-tree. If it's not there neither, we
433 * calculate it now based on the total RAM size
435 if (ppc64_pft_size == 0)
436 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
438 return 1UL << ppc64_pft_size;
440 /* round mem_size up to next power of 2 */
441 mem_size = lmb_phys_mem_size();
442 rnd_mem_size = 1UL << __ilog2(mem_size);
443 if (rnd_mem_size < mem_size)
447 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
449 return pteg_count << 7;
452 #ifdef CONFIG_MEMORY_HOTPLUG
453 void create_section_mapping(unsigned long start, unsigned long end)
455 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
456 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
457 mmu_linear_psize, mmu_kernel_ssize));
460 int remove_section_mapping(unsigned long start, unsigned long end)
462 return htab_remove_mapping(start, end, mmu_linear_psize,
465 #endif /* CONFIG_MEMORY_HOTPLUG */
467 static inline void make_bl(unsigned int *insn_addr, void *func)
469 unsigned long funcp = *((unsigned long *)func);
470 int offset = funcp - (unsigned long)insn_addr;
472 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
473 flush_icache_range((unsigned long)insn_addr, 4+
474 (unsigned long)insn_addr);
477 static void __init htab_finish_init(void)
479 extern unsigned int *htab_call_hpte_insert1;
480 extern unsigned int *htab_call_hpte_insert2;
481 extern unsigned int *htab_call_hpte_remove;
482 extern unsigned int *htab_call_hpte_updatepp;
484 #ifdef CONFIG_PPC_HAS_HASH_64K
485 extern unsigned int *ht64_call_hpte_insert1;
486 extern unsigned int *ht64_call_hpte_insert2;
487 extern unsigned int *ht64_call_hpte_remove;
488 extern unsigned int *ht64_call_hpte_updatepp;
490 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
491 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
492 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
493 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
494 #endif /* CONFIG_PPC_HAS_HASH_64K */
496 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
497 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
498 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
499 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
502 void __init htab_initialize(void)
505 unsigned long pteg_count;
506 unsigned long mode_rw;
507 unsigned long base = 0, size = 0, limit;
510 extern unsigned long tce_alloc_start, tce_alloc_end;
512 DBG(" -> htab_initialize()\n");
514 /* Initialize segment sizes */
515 htab_init_seg_sizes();
517 /* Initialize page sizes */
518 htab_init_page_sizes();
520 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
521 mmu_kernel_ssize = MMU_SEGSIZE_1T;
522 mmu_highuser_ssize = MMU_SEGSIZE_1T;
523 printk(KERN_INFO "Using 1TB segments\n");
527 * Calculate the required size of the htab. We want the number of
528 * PTEGs to equal one half the number of real pages.
530 htab_size_bytes = htab_get_table_size();
531 pteg_count = htab_size_bytes >> 7;
533 htab_hash_mask = pteg_count - 1;
535 if (firmware_has_feature(FW_FEATURE_LPAR)) {
536 /* Using a hypervisor which owns the htab */
540 /* Find storage for the HPT. Must be contiguous in
541 * the absolute address space. On cell we want it to be
542 * in the first 2 Gig so we can use it for IOMMU hacks.
544 if (machine_is(cell))
549 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
551 DBG("Hash table allocated at %lx, size: %lx\n", table,
554 htab_address = abs_to_virt(table);
556 /* htab absolute addr + encoded htabsize */
557 _SDR1 = table + __ilog2(pteg_count) - 11;
559 /* Initialize the HPT with no entries */
560 memset((void *)table, 0, htab_size_bytes);
563 mtspr(SPRN_SDR1, _SDR1);
566 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
568 #ifdef CONFIG_DEBUG_PAGEALLOC
569 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
570 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
572 memset(linear_map_hash_slots, 0, linear_map_hash_count);
573 #endif /* CONFIG_DEBUG_PAGEALLOC */
575 /* On U3 based machines, we need to reserve the DART area and
576 * _NOT_ map it to avoid cache paradoxes as it's remapped non
580 /* create bolted the linear mapping in the hash table */
581 for (i=0; i < lmb.memory.cnt; i++) {
582 base = (unsigned long)__va(lmb.memory.region[i].base);
583 size = lmb.memory.region[i].size;
585 DBG("creating mapping for region: %lx : %lx\n", base, size);
587 #ifdef CONFIG_U3_DART
588 /* Do not map the DART space. Fortunately, it will be aligned
589 * in such a way that it will not cross two lmb regions and
590 * will fit within a single 16Mb page.
591 * The DART space is assumed to be a full 16Mb region even if
592 * we only use 2Mb of that space. We will use more of it later
593 * for AGP GART. We have to use a full 16Mb large page.
595 DBG("DART base: %lx\n", dart_tablebase);
597 if (dart_tablebase != 0 && dart_tablebase >= base
598 && dart_tablebase < (base + size)) {
599 unsigned long dart_table_end = dart_tablebase + 16 * MB;
600 if (base != dart_tablebase)
601 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
605 if ((base + size) > dart_table_end)
606 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
608 __pa(dart_table_end),
614 #endif /* CONFIG_U3_DART */
615 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
616 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
620 * If we have a memory_limit and we've allocated TCEs then we need to
621 * explicitly map the TCE area at the top of RAM. We also cope with the
622 * case that the TCEs start below memory_limit.
623 * tce_alloc_start/end are 16MB aligned so the mapping should work
624 * for either 4K or 16MB pages.
626 if (tce_alloc_start) {
627 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
628 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
630 if (base + size >= tce_alloc_start)
631 tce_alloc_start = base + size + 1;
633 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
634 __pa(tce_alloc_start), mode_rw,
635 mmu_linear_psize, mmu_kernel_ssize));
640 DBG(" <- htab_initialize()\n");
645 void htab_initialize_secondary(void)
647 if (!firmware_has_feature(FW_FEATURE_LPAR))
648 mtspr(SPRN_SDR1, _SDR1);
652 * Called by asm hashtable.S for doing lazy icache flush
654 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
658 if (!pfn_valid(pte_pfn(pte)))
661 page = pte_page(pte);
664 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
666 __flush_dcache_icache(page_address(page));
667 set_bit(PG_arch_1, &page->flags);
675 * Demote a segment to using 4k pages.
676 * For now this makes the whole process use 4k pages.
678 #ifdef CONFIG_PPC_64K_PAGES
679 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
681 if (mm->context.user_psize == MMU_PAGE_4K)
683 slice_set_user_psize(mm, MMU_PAGE_4K);
684 #ifdef CONFIG_SPU_BASE
685 spu_flush_all_slbs(mm);
687 if (get_paca()->context.user_psize != MMU_PAGE_4K) {
688 get_paca()->context = mm->context;
689 slb_flush_and_rebolt();
692 #endif /* CONFIG_PPC_64K_PAGES */
694 #ifdef CONFIG_PPC_SUBPAGE_PROT
696 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
697 * Userspace sets the subpage permissions using the subpage_prot system call.
699 * Result is 0: full permissions, _PAGE_RW: read-only,
700 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
702 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
704 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
708 if (ea >= spt->maxaddr)
710 if (ea < 0x100000000) {
711 /* addresses below 4GB use spt->low_prot */
712 sbpm = spt->low_prot;
714 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
718 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
721 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
723 /* extract 2-bit bitfield for this 4k subpage */
724 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
726 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
727 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
731 #else /* CONFIG_PPC_SUBPAGE_PROT */
732 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
740 * 1 - normal page fault
741 * -1 - critical hash insertion error
742 * -2 - access not permitted by subpage protection mechanism
744 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
748 struct mm_struct *mm;
751 int rc, user_region = 0, local = 0;
754 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
757 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
758 DBG_LOW(" out of pgtable range !\n");
762 /* Get region & vsid */
763 switch (REGION_ID(ea)) {
768 DBG_LOW(" user region with no mm !\n");
771 #ifdef CONFIG_PPC_MM_SLICES
772 psize = get_slice_psize(mm, ea);
774 psize = mm->context.user_psize;
776 ssize = user_segment_size(ea);
777 vsid = get_vsid(mm->context.id, ea, ssize);
779 case VMALLOC_REGION_ID:
781 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
782 if (ea < VMALLOC_END)
783 psize = mmu_vmalloc_psize;
785 psize = mmu_io_psize;
786 ssize = mmu_kernel_ssize;
790 * Send the problem up to do_page_fault
794 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
801 /* Check CPU locality */
802 tmp = cpumask_of_cpu(smp_processor_id());
803 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
806 #ifdef CONFIG_HUGETLB_PAGE
807 /* Handle hugepage regions */
808 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
809 DBG_LOW(" -> huge page !\n");
810 return hash_huge_page(mm, access, ea, vsid, local, trap);
812 #endif /* CONFIG_HUGETLB_PAGE */
814 #ifndef CONFIG_PPC_64K_PAGES
815 /* If we use 4K pages and our psize is not 4K, then we are hitting
816 * a special driver mapping, we need to align the address before
819 if (psize != MMU_PAGE_4K)
820 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
821 #endif /* CONFIG_PPC_64K_PAGES */
823 /* Get PTE and page size from page tables */
824 ptep = find_linux_pte(pgdir, ea);
825 if (ptep == NULL || !pte_present(*ptep)) {
826 DBG_LOW(" no PTE !\n");
830 #ifndef CONFIG_PPC_64K_PAGES
831 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
833 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
834 pte_val(*(ptep + PTRS_PER_PTE)));
836 /* Pre-check access permissions (will be re-checked atomically
837 * in __hash_page_XX but this pre-check is a fast path
839 if (access & ~pte_val(*ptep)) {
840 DBG_LOW(" no access !\n");
844 /* Do actual hashing */
845 #ifdef CONFIG_PPC_64K_PAGES
846 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
847 if (pte_val(*ptep) & _PAGE_4K_PFN) {
848 demote_segment_4k(mm, ea);
852 /* If this PTE is non-cacheable and we have restrictions on
853 * using non cacheable large pages, then we switch to 4k
855 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
856 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
858 demote_segment_4k(mm, ea);
860 } else if (ea < VMALLOC_END) {
862 * some driver did a non-cacheable mapping
863 * in vmalloc space, so switch vmalloc
866 printk(KERN_ALERT "Reducing vmalloc segment "
867 "to 4kB pages because of "
868 "non-cacheable mapping\n");
869 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
870 #ifdef CONFIG_SPU_BASE
871 spu_flush_all_slbs(mm);
876 if (psize != get_paca()->context.user_psize) {
877 get_paca()->context = mm->context;
878 slb_flush_and_rebolt();
880 } else if (get_paca()->vmalloc_sllp !=
881 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
882 get_paca()->vmalloc_sllp =
883 mmu_psize_defs[mmu_vmalloc_psize].sllp;
884 slb_vmalloc_update();
886 #endif /* CONFIG_PPC_64K_PAGES */
888 #ifdef CONFIG_PPC_HAS_HASH_64K
889 if (psize == MMU_PAGE_64K)
890 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
892 #endif /* CONFIG_PPC_HAS_HASH_64K */
894 int spp = subpage_protection(pgdir, ea);
898 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
902 #ifndef CONFIG_PPC_64K_PAGES
903 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
905 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
906 pte_val(*(ptep + PTRS_PER_PTE)));
908 DBG_LOW(" -> rc=%d\n", rc);
911 EXPORT_SYMBOL_GPL(hash_page);
913 void hash_preload(struct mm_struct *mm, unsigned long ea,
914 unsigned long access, unsigned long trap)
924 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
926 #ifdef CONFIG_PPC_MM_SLICES
927 /* We only prefault standard pages for now */
928 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
932 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
933 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
935 /* Get Linux PTE if available */
939 ptep = find_linux_pte(pgdir, ea);
943 #ifdef CONFIG_PPC_64K_PAGES
944 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
945 * a 64K kernel), then we don't preload, hash_page() will take
946 * care of it once we actually try to access the page.
947 * That way we don't have to duplicate all of the logic for segment
948 * page size demotion here
950 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
952 #endif /* CONFIG_PPC_64K_PAGES */
955 ssize = user_segment_size(ea);
956 vsid = get_vsid(mm->context.id, ea, ssize);
958 /* Hash doesn't like irqs */
959 local_irq_save(flags);
961 /* Is that local to this CPU ? */
962 mask = cpumask_of_cpu(smp_processor_id());
963 if (cpus_equal(mm->cpu_vm_mask, mask))
967 #ifdef CONFIG_PPC_HAS_HASH_64K
968 if (mm->context.user_psize == MMU_PAGE_64K)
969 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
971 #endif /* CONFIG_PPC_HAS_HASH_64K */
972 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
973 subpage_protection(pgdir, ea));
975 local_irq_restore(flags);
978 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
979 * do not forget to update the assembly call site !
981 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
984 unsigned long hash, index, shift, hidx, slot;
986 DBG_LOW("flush_hash_page(va=%016x)\n", va);
987 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
988 hash = hpt_hash(va, shift, ssize);
989 hidx = __rpte_to_hidx(pte, index);
990 if (hidx & _PTEIDX_SECONDARY)
992 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
993 slot += hidx & _PTEIDX_GROUP_IX;
994 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
995 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
996 } pte_iterate_hashed_end();
999 void flush_hash_range(unsigned long number, int local)
1001 if (ppc_md.flush_hash_range)
1002 ppc_md.flush_hash_range(number, local);
1005 struct ppc64_tlb_batch *batch =
1006 &__get_cpu_var(ppc64_tlb_batch);
1008 for (i = 0; i < number; i++)
1009 flush_hash_page(batch->vaddr[i], batch->pte[i],
1010 batch->psize, batch->ssize, local);
1015 * low_hash_fault is called when we the low level hash code failed
1016 * to instert a PTE due to an hypervisor error
1018 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1020 if (user_mode(regs)) {
1021 #ifdef CONFIG_PPC_SUBPAGE_PROT
1023 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1026 _exception(SIGBUS, regs, BUS_ADRERR, address);
1028 bad_page_fault(regs, address, SIGBUS);
1031 #ifdef CONFIG_DEBUG_PAGEALLOC
1032 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1034 unsigned long hash, hpteg;
1035 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1036 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1037 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
1038 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
1041 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1042 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1044 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1045 mode, HPTE_V_BOLTED,
1046 mmu_linear_psize, mmu_kernel_ssize);
1048 spin_lock(&linear_map_hash_lock);
1049 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1050 linear_map_hash_slots[lmi] = ret | 0x80;
1051 spin_unlock(&linear_map_hash_lock);
1054 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1056 unsigned long hash, hidx, slot;
1057 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1058 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1060 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1061 spin_lock(&linear_map_hash_lock);
1062 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1063 hidx = linear_map_hash_slots[lmi] & 0x7f;
1064 linear_map_hash_slots[lmi] = 0;
1065 spin_unlock(&linear_map_hash_lock);
1066 if (hidx & _PTEIDX_SECONDARY)
1068 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1069 slot += hidx & _PTEIDX_GROUP_IX;
1070 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1073 void kernel_map_pages(struct page *page, int numpages, int enable)
1075 unsigned long flags, vaddr, lmi;
1078 local_irq_save(flags);
1079 for (i = 0; i < numpages; i++, page++) {
1080 vaddr = (unsigned long)page_address(page);
1081 lmi = __pa(vaddr) >> PAGE_SHIFT;
1082 if (lmi >= linear_map_hash_count)
1085 kernel_map_linear_page(vaddr, lmi);
1087 kernel_unmap_linear_page(vaddr, lmi);
1089 local_irq_restore(flags);
1091 #endif /* CONFIG_DEBUG_PAGEALLOC */