2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
44 static void fixup_resource(struct resource *res, struct pci_dev *dev);
45 static void do_bus_setup(struct pci_bus *bus);
47 /* pci_io_base -- the base address from which io bars are offsets.
48 * This is the lowest I/O base address (so bar values are always positive),
49 * and it *must* be the start of ISA space if an ISA bus exists because
50 * ISA drivers use hard coded offsets. If no ISA bus exists nothing
51 * is mapped on the first 64K of IO space
53 unsigned long pci_io_base = ISA_IO_BASE;
54 EXPORT_SYMBOL(pci_io_base);
58 static struct dma_mapping_ops *pci_dma_ops;
60 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
62 pci_dma_ops = dma_ops;
65 struct dma_mapping_ops *get_pci_dma_ops(void)
69 EXPORT_SYMBOL(get_pci_dma_ops);
72 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
74 return dma_set_mask(&dev->dev, mask);
77 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
81 rc = dma_set_mask(&dev->dev, mask);
82 dev->dev.coherent_dma_mask = dev->dma_mask;
87 static void fixup_broken_pcnet32(struct pci_dev* dev)
89 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
90 dev->vendor = PCI_VENDOR_ID_AMD;
91 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
94 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
98 * We need to avoid collisions with `mirrored' VGA ports
99 * and other strange ISA hardware, so we always want the
100 * addresses to be allocated in the 0x000-0x0ff region
103 * Why? Because some silly external IO cards only decode
104 * the low 10 bits of the IO address. The 0x00-0xff region
105 * is reserved for motherboard devices that decode all 16
106 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
107 * but we want to try to avoid allocating at 0x2900-0x2bff
108 * which might have be mirrored at 0x0100-0x03ff..
110 void pcibios_align_resource(void *data, struct resource *res,
111 resource_size_t size, resource_size_t align)
113 struct pci_dev *dev = data;
114 struct pci_controller *hose = pci_bus_to_host(dev->bus);
115 resource_size_t start = res->start;
116 unsigned long alignto;
118 if (res->flags & IORESOURCE_IO) {
119 unsigned long offset = (unsigned long)hose->io_base_virt -
121 /* Make sure we start at our min on all hoses */
122 if (start - offset < PCIBIOS_MIN_IO)
123 start = PCIBIOS_MIN_IO + offset;
126 * Put everything into 0x00-0xff region modulo 0x400
129 start = (start + 0x3ff) & ~0x3ff;
131 } else if (res->flags & IORESOURCE_MEM) {
132 /* Make sure we start at our min on all hoses */
133 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
134 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
136 /* Align to multiple of size of minimum base. */
137 alignto = max(0x1000UL, align);
138 start = ALIGN(start, alignto);
144 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
147 struct pci_bus *child_bus;
149 list_for_each_entry(dev, &b->devices, bus_list) {
152 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
153 struct resource *r = &dev->resource[i];
155 if (r->parent || !r->start || !r->flags)
157 pci_claim_resource(dev, i);
161 list_for_each_entry(child_bus, &b->children, node)
162 pcibios_claim_one_bus(child_bus);
164 #ifdef CONFIG_HOTPLUG
165 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
168 static void __init pcibios_claim_of_setup(void)
172 list_for_each_entry(b, &pci_root_buses, node)
173 pcibios_claim_one_bus(b);
176 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
181 prop = of_get_property(np, name, &len);
182 if (prop && len >= 4)
187 static unsigned int pci_parse_of_flags(u32 addr0)
189 unsigned int flags = 0;
191 if (addr0 & 0x02000000) {
192 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
193 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
194 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
195 if (addr0 & 0x40000000)
196 flags |= IORESOURCE_PREFETCH
197 | PCI_BASE_ADDRESS_MEM_PREFETCH;
198 } else if (addr0 & 0x01000000)
199 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
204 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
208 struct resource *res;
213 addrs = of_get_property(node, "assigned-addresses", &proplen);
216 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
217 for (; proplen >= 20; proplen -= 20, addrs += 5) {
218 flags = pci_parse_of_flags(addrs[0]);
221 base = of_read_number(&addrs[1], 2);
222 size = of_read_number(&addrs[3], 2);
226 DBG(" base: %llx, size: %llx, i: %x\n",
227 (unsigned long long)base, (unsigned long long)size, i);
229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 } else if (i == dev->rom_base_reg) {
232 res = &dev->resource[PCI_ROM_RESOURCE];
233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
235 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
239 res->end = base + size - 1;
241 res->name = pci_name(dev);
242 fixup_resource(res, dev);
246 struct pci_dev *of_create_pci_dev(struct device_node *node,
247 struct pci_bus *bus, int devfn)
252 dev = alloc_pci_dev();
255 type = of_get_property(node, "device_type", NULL);
259 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
263 dev->dev.parent = bus->bridge;
264 dev->dev.bus = &pci_bus_type;
266 dev->multifunction = 0; /* maybe a lie? */
268 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
269 dev->device = get_int_prop(node, "device-id", 0xffff);
270 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
271 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
273 dev->cfg_size = pci_cfg_space_size(dev);
275 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
276 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
277 dev->class = get_int_prop(node, "class-code", 0);
278 dev->revision = get_int_prop(node, "revision-id", 0);
280 DBG(" class: 0x%x\n", dev->class);
281 DBG(" revision: 0x%x\n", dev->revision);
283 dev->current_state = 4; /* unknown power state */
284 dev->error_state = pci_channel_io_normal;
285 dev->dma_mask = 0xffffffff;
287 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
288 /* a PCI-PCI bridge */
289 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
290 dev->rom_base_reg = PCI_ROM_ADDRESS1;
291 } else if (!strcmp(type, "cardbus")) {
292 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
294 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
295 dev->rom_base_reg = PCI_ROM_ADDRESS;
296 /* Maybe do a default OF mapping here */
300 pci_parse_of_addrs(node, dev);
302 DBG(" adding to system ...\n");
304 pci_device_add(dev, bus);
308 EXPORT_SYMBOL(of_create_pci_dev);
310 void __devinit of_scan_bus(struct device_node *node,
313 struct device_node *child = NULL;
318 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
320 while ((child = of_get_next_child(node, child)) != NULL) {
321 DBG(" * %s\n", child->full_name);
322 reg = of_get_property(child, "reg", ®len);
323 if (reg == NULL || reglen < 20)
325 devfn = (reg[0] >> 8) & 0xff;
327 /* create a new pci_dev for this device */
328 dev = of_create_pci_dev(child, bus, devfn);
331 DBG("dev header type: %x\n", dev->hdr_type);
333 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
334 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
335 of_scan_pci_bridge(child, dev);
340 EXPORT_SYMBOL(of_scan_bus);
342 void __devinit of_scan_pci_bridge(struct device_node *node,
346 const u32 *busrange, *ranges;
348 struct resource *res;
352 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
354 /* parse bus-range property */
355 busrange = of_get_property(node, "bus-range", &len);
356 if (busrange == NULL || len != 8) {
357 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
361 ranges = of_get_property(node, "ranges", &len);
362 if (ranges == NULL) {
363 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
368 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
370 printk(KERN_ERR "Failed to create pci bus for %s\n",
375 bus->primary = dev->bus->number;
376 bus->subordinate = busrange[1];
380 /* parse ranges property */
381 /* PCI #address-cells == 3 and #size-cells == 2 always */
382 res = &dev->resource[PCI_BRIDGE_RESOURCES];
383 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
385 bus->resource[i] = res;
389 for (; len >= 32; len -= 32, ranges += 8) {
390 flags = pci_parse_of_flags(ranges[0]);
391 size = of_read_number(&ranges[6], 2);
392 if (flags == 0 || size == 0)
394 if (flags & IORESOURCE_IO) {
395 res = bus->resource[0];
397 printk(KERN_ERR "PCI: ignoring extra I/O range"
398 " for bridge %s\n", node->full_name);
402 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
403 printk(KERN_ERR "PCI: too many memory ranges"
404 " for bridge %s\n", node->full_name);
407 res = bus->resource[i];
410 res->start = of_read_number(&ranges[1], 2);
411 res->end = res->start + size - 1;
413 fixup_resource(res, dev);
415 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
417 DBG(" bus name: %s\n", bus->name);
419 mode = PCI_PROBE_NORMAL;
420 if (ppc_md.pci_probe_mode)
421 mode = ppc_md.pci_probe_mode(bus);
422 DBG(" probe mode: %d\n", mode);
424 if (mode == PCI_PROBE_DEVTREE)
425 of_scan_bus(node, bus);
426 else if (mode == PCI_PROBE_NORMAL)
427 pci_scan_child_bus(bus);
429 EXPORT_SYMBOL(of_scan_pci_bridge);
431 void __devinit scan_phb(struct pci_controller *hose)
434 struct device_node *node = hose->dn;
436 struct resource *res;
438 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
440 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
442 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
443 hose->global_number);
446 bus->secondary = hose->first_busno;
449 pcibios_map_io_space(bus);
451 bus->resource[0] = res = &hose->io_resource;
452 if (res->flags && request_resource(&ioport_resource, res)) {
453 printk(KERN_ERR "Failed to request PCI IO region "
454 "on PCI domain %04x\n", hose->global_number);
455 DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
456 res->start, res->end);
459 for (i = 0; i < 3; ++i) {
460 res = &hose->mem_resources[i];
461 bus->resource[i+1] = res;
462 if (res->flags && request_resource(&iomem_resource, res))
463 printk(KERN_ERR "Failed to request PCI memory region "
464 "on PCI domain %04x\n", hose->global_number);
467 mode = PCI_PROBE_NORMAL;
469 if (node && ppc_md.pci_probe_mode)
470 mode = ppc_md.pci_probe_mode(bus);
471 DBG(" probe mode: %d\n", mode);
472 if (mode == PCI_PROBE_DEVTREE) {
473 bus->subordinate = hose->last_busno;
474 of_scan_bus(node, bus);
477 if (mode == PCI_PROBE_NORMAL)
478 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
481 static int __init pcibios_init(void)
483 struct pci_controller *hose, *tmp;
485 /* For now, override phys_mem_access_prot. If we need it,
486 * later, we may move that initialization to each ppc_md
488 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
490 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
492 /* Scan all of the recorded PCI controllers. */
493 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
495 pci_bus_add_devices(hose->bus);
499 pcibios_claim_of_setup();
501 /* FIXME: `else' will be removed when
502 pci_assign_unassigned_resources() is able to work
503 correctly with [partially] allocated PCI tree. */
504 pci_assign_unassigned_resources();
506 /* Call machine dependent final fixup */
507 if (ppc_md.pcibios_fixup)
508 ppc_md.pcibios_fixup();
510 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
515 subsys_initcall(pcibios_init);
517 int pcibios_enable_device(struct pci_dev *dev, int mask)
522 pci_read_config_word(dev, PCI_COMMAND, &cmd);
525 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
526 struct resource *res = &dev->resource[i];
528 /* Only set up the requested stuff */
529 if (!(mask & (1<<i)))
532 if (res->flags & IORESOURCE_IO)
533 cmd |= PCI_COMMAND_IO;
534 if (res->flags & IORESOURCE_MEM)
535 cmd |= PCI_COMMAND_MEMORY;
539 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
541 /* Enable the appropriate bits in the PCI command register. */
542 pci_write_config_word(dev, PCI_COMMAND, cmd);
547 #ifdef CONFIG_HOTPLUG
549 int pcibios_unmap_io_space(struct pci_bus *bus)
551 struct pci_controller *hose;
553 WARN_ON(bus == NULL);
555 /* If this is not a PHB, we only flush the hash table over
556 * the area mapped by this bridge. We don't play with the PTE
557 * mappings since we might have to deal with sub-page alignemnts
558 * so flushing the hash table is the only sane way to make sure
559 * that no hash entries are covering that removed bridge area
560 * while still allowing other busses overlapping those pages
563 struct resource *res = bus->resource[0];
565 DBG("IO unmapping for PCI-PCI bridge %s\n",
566 pci_name(bus->self));
568 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
569 res->end - res->start + 1);
573 /* Get the host bridge */
574 hose = pci_bus_to_host(bus);
576 /* Check if we have IOs allocated */
577 if (hose->io_base_alloc == 0)
580 DBG("IO unmapping for PHB %s\n", hose->dn->full_name);
581 DBG(" alloc=0x%p\n", hose->io_base_alloc);
583 /* This is a PHB, we fully unmap the IO area */
584 vunmap(hose->io_base_alloc);
588 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
590 #endif /* CONFIG_HOTPLUG */
592 int __devinit pcibios_map_io_space(struct pci_bus *bus)
594 struct vm_struct *area;
595 unsigned long phys_page;
596 unsigned long size_page;
597 unsigned long io_virt_offset;
598 struct pci_controller *hose;
600 WARN_ON(bus == NULL);
602 /* If this not a PHB, nothing to do, page tables still exist and
603 * thus HPTEs will be faulted in when needed
606 DBG("IO mapping for PCI-PCI bridge %s\n",
607 pci_name(bus->self));
608 DBG(" virt=0x%016lx...0x%016lx\n",
609 bus->resource[0]->start + _IO_BASE,
610 bus->resource[0]->end + _IO_BASE);
614 /* Get the host bridge */
615 hose = pci_bus_to_host(bus);
616 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
617 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
619 /* Make sure IO area address is clear */
620 hose->io_base_alloc = NULL;
622 /* If there's no IO to map on that bus, get away too */
623 if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
626 /* Let's allocate some IO space for that guy. We don't pass
627 * VM_IOREMAP because we don't care about alignment tricks that
628 * the core does in that case. Maybe we should due to stupid card
629 * with incomplete address decoding but I'd rather not deal with
630 * those outside of the reserved 64K legacy region.
632 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
635 hose->io_base_alloc = area->addr;
636 hose->io_base_virt = (void __iomem *)(area->addr +
637 hose->io_base_phys - phys_page);
639 DBG("IO mapping for PHB %s\n", hose->dn->full_name);
640 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
641 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
642 DBG(" size=0x%016lx (alloc=0x%016lx)\n",
643 hose->pci_io_size, size_page);
645 /* Establish the mapping */
646 if (__ioremap_at(phys_page, area->addr, size_page,
647 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
650 /* Fixup hose IO resource */
651 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
652 hose->io_resource.start += io_virt_offset;
653 hose->io_resource.end += io_virt_offset;
655 DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
656 hose->io_resource.start, hose->io_resource.end);
660 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
662 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
664 struct pci_controller *hose = pci_bus_to_host(dev->bus);
665 unsigned long offset;
667 if (res->flags & IORESOURCE_IO) {
668 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
669 res->start += offset;
671 } else if (res->flags & IORESOURCE_MEM) {
672 res->start += hose->pci_mem_offset;
673 res->end += hose->pci_mem_offset;
677 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
680 /* Update device resources. */
683 DBG("%s: Fixup resources:\n", pci_name(dev));
684 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
685 struct resource *res = &dev->resource[i];
689 DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
690 i, res->flags, res->start, res->end);
692 fixup_resource(res, dev);
694 DBG(" > %08lx:0x%016lx...0x%016lx\n",
695 res->flags, res->start, res->end);
698 EXPORT_SYMBOL(pcibios_fixup_device_resources);
700 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
702 struct dev_archdata *sd = &dev->dev.archdata;
704 sd->of_node = pci_device_to_OF_node(dev);
706 DBG("PCI device %s OF node: %s\n", pci_name(dev),
707 sd->of_node ? sd->of_node->full_name : "<none>");
709 sd->dma_ops = pci_dma_ops;
711 sd->numa_node = pcibus_to_node(dev->bus);
715 if (ppc_md.pci_dma_dev_setup)
716 ppc_md.pci_dma_dev_setup(dev);
718 EXPORT_SYMBOL(pcibios_setup_new_device);
720 static void __devinit do_bus_setup(struct pci_bus *bus)
724 if (ppc_md.pci_dma_bus_setup)
725 ppc_md.pci_dma_bus_setup(bus);
727 list_for_each_entry(dev, &bus->devices, bus_list)
728 pcibios_setup_new_device(dev);
730 /* Read default IRQs and fixup if necessary */
731 list_for_each_entry(dev, &bus->devices, bus_list) {
732 pci_read_irq_line(dev);
733 if (ppc_md.pci_irq_fixup)
734 ppc_md.pci_irq_fixup(dev);
738 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
740 struct pci_dev *dev = bus->self;
741 struct device_node *np;
743 np = pci_bus_to_OF_node(bus);
745 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
747 if (dev && pci_probe_only &&
748 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
749 /* This is a subordinate bridge */
751 pci_read_bridge_bases(bus);
752 pcibios_fixup_device_resources(dev, bus);
760 list_for_each_entry(dev, &bus->devices, bus_list)
761 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
762 pcibios_fixup_device_resources(dev, bus);
764 EXPORT_SYMBOL(pcibios_fixup_bus);
766 unsigned long pci_address_to_pio(phys_addr_t address)
768 struct pci_controller *hose, *tmp;
770 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
771 if (address >= hose->io_base_phys &&
772 address < (hose->io_base_phys + hose->pci_io_size)) {
774 (unsigned long)hose->io_base_virt - _IO_BASE;
775 return base + (address - hose->io_base_phys);
778 return (unsigned int)-1;
780 EXPORT_SYMBOL_GPL(pci_address_to_pio);
783 #define IOBASE_BRIDGE_NUMBER 0
784 #define IOBASE_MEMORY 1
786 #define IOBASE_ISA_IO 3
787 #define IOBASE_ISA_MEM 4
789 long sys_pciconfig_iobase(long which, unsigned long in_bus,
790 unsigned long in_devfn)
792 struct pci_controller* hose;
793 struct list_head *ln;
794 struct pci_bus *bus = NULL;
795 struct device_node *hose_node;
797 /* Argh ! Please forgive me for that hack, but that's the
798 * simplest way to get existing XFree to not lockup on some
799 * G5 machines... So when something asks for bus 0 io base
800 * (bus 0 is HT root), we return the AGP one instead.
802 if (machine_is_compatible("MacRISC4"))
806 /* That syscall isn't quite compatible with PCI domains, but it's
807 * used on pre-domains setup. We return the first match
810 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
812 if (in_bus >= bus->number && in_bus <= bus->subordinate)
816 if (bus == NULL || bus->sysdata == NULL)
819 hose_node = (struct device_node *)bus->sysdata;
820 hose = PCI_DN(hose_node)->phb;
823 case IOBASE_BRIDGE_NUMBER:
824 return (long)hose->first_busno;
826 return (long)hose->pci_mem_offset;
828 return (long)hose->io_base_phys;
830 return (long)isa_io_base;
839 int pcibus_to_node(struct pci_bus *bus)
841 struct pci_controller *phb = pci_bus_to_host(bus);
844 EXPORT_SYMBOL(pcibus_to_node);