2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
25 #include <asm/processor.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
36 #define DBG(fmt...) printk(fmt)
41 unsigned long pci_probe_only = 1;
42 int pci_assign_all_buses = 0;
44 #ifdef CONFIG_PPC_MULTIPLATFORM
45 static void fixup_resource(struct resource *res, struct pci_dev *dev);
46 static void do_bus_setup(struct pci_bus *bus);
47 static void phbs_remap_io(void);
50 /* pci_io_base -- the base address from which io bars are offsets.
51 * This is the lowest I/O base address (so bar values are always positive),
52 * and it *must* be the start of ISA space if an ISA bus exists because
53 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
54 * page is mapped and isa_io_limit prevents access to it.
56 unsigned long isa_io_base; /* NULL if no ISA bus */
57 EXPORT_SYMBOL(isa_io_base);
58 unsigned long pci_io_base;
59 EXPORT_SYMBOL(pci_io_base);
61 void iSeries_pcibios_init(void);
65 struct dma_mapping_ops pci_dma_ops;
66 EXPORT_SYMBOL(pci_dma_ops);
68 int global_phb_number; /* Global phb counter */
70 /* Cached ISA bridge dev. */
71 struct pci_dev *ppc64_isabridge_dev = NULL;
72 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
74 static void fixup_broken_pcnet32(struct pci_dev* dev)
76 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
77 dev->vendor = PCI_VENDOR_ID_AMD;
78 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
81 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
83 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
86 unsigned long offset = 0;
87 struct pci_controller *hose = pci_bus_to_host(dev->bus);
92 if (res->flags & IORESOURCE_IO)
93 offset = (unsigned long)hose->io_base_virt - pci_io_base;
95 if (res->flags & IORESOURCE_MEM)
96 offset = hose->pci_mem_offset;
98 region->start = res->start - offset;
99 region->end = res->end - offset;
102 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
103 struct pci_bus_region *region)
105 unsigned long offset = 0;
106 struct pci_controller *hose = pci_bus_to_host(dev->bus);
111 if (res->flags & IORESOURCE_IO)
112 offset = (unsigned long)hose->io_base_virt - pci_io_base;
114 if (res->flags & IORESOURCE_MEM)
115 offset = hose->pci_mem_offset;
117 res->start = region->start + offset;
118 res->end = region->end + offset;
121 #ifdef CONFIG_HOTPLUG
122 EXPORT_SYMBOL(pcibios_resource_to_bus);
123 EXPORT_SYMBOL(pcibios_bus_to_resource);
127 * We need to avoid collisions with `mirrored' VGA ports
128 * and other strange ISA hardware, so we always want the
129 * addresses to be allocated in the 0x000-0x0ff region
132 * Why? Because some silly external IO cards only decode
133 * the low 10 bits of the IO address. The 0x00-0xff region
134 * is reserved for motherboard devices that decode all 16
135 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
136 * but we want to try to avoid allocating at 0x2900-0x2bff
137 * which might have be mirrored at 0x0100-0x03ff..
139 void pcibios_align_resource(void *data, struct resource *res,
140 resource_size_t size, resource_size_t align)
142 struct pci_dev *dev = data;
143 struct pci_controller *hose = pci_bus_to_host(dev->bus);
144 resource_size_t start = res->start;
145 unsigned long alignto;
147 if (res->flags & IORESOURCE_IO) {
148 unsigned long offset = (unsigned long)hose->io_base_virt -
150 /* Make sure we start at our min on all hoses */
151 if (start - offset < PCIBIOS_MIN_IO)
152 start = PCIBIOS_MIN_IO + offset;
155 * Put everything into 0x00-0xff region modulo 0x400
158 start = (start + 0x3ff) & ~0x3ff;
160 } else if (res->flags & IORESOURCE_MEM) {
161 /* Make sure we start at our min on all hoses */
162 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
163 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
165 /* Align to multiple of size of minimum base. */
166 alignto = max(0x1000UL, align);
167 start = ALIGN(start, alignto);
173 static DEFINE_SPINLOCK(hose_spinlock);
176 * pci_controller(phb) initialized common variables.
178 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
180 memset(hose, 0, sizeof(struct pci_controller));
182 spin_lock(&hose_spinlock);
183 hose->global_number = global_phb_number++;
184 list_add_tail(&hose->list_node, &hose_list);
185 spin_unlock(&hose_spinlock);
188 static void add_linux_pci_domain(struct device_node *dev,
189 struct pci_controller *phb)
191 struct property *of_prop;
194 of_prop = (struct property *)
195 get_property(dev, "linux,pci-domain", &size);
198 WARN_ON(of_prop && size < sizeof(int));
199 if (of_prop && size < sizeof(int))
201 size = sizeof(struct property) + sizeof(int);
202 if (of_prop == NULL) {
204 of_prop = kmalloc(size, GFP_KERNEL);
206 of_prop = alloc_bootmem(size);
208 memset(of_prop, 0, sizeof(struct property));
209 of_prop->name = "linux,pci-domain";
210 of_prop->length = sizeof(int);
211 of_prop->value = (unsigned char *)&of_prop[1];
212 *((int *)of_prop->value) = phb->global_number;
213 prom_add_property(dev, of_prop);
216 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
218 struct pci_controller *phb;
221 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
223 phb = alloc_bootmem(sizeof (struct pci_controller));
226 pci_setup_pci_controller(phb);
227 phb->arch_data = dev;
228 phb->is_dynamic = mem_init_done;
230 PHB_SET_NODE(phb, of_node_to_nid(dev));
231 add_linux_pci_domain(dev, phb);
236 void pcibios_free_controller(struct pci_controller *phb)
238 if (phb->arch_data) {
239 struct device_node *np = phb->arch_data;
240 int *domain = (int *)get_property(np,
241 "linux,pci-domain", NULL);
249 #ifndef CONFIG_PPC_ISERIES
250 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
253 struct pci_bus *child_bus;
255 list_for_each_entry(dev, &b->devices, bus_list) {
258 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
259 struct resource *r = &dev->resource[i];
261 if (r->parent || !r->start || !r->flags)
263 pci_claim_resource(dev, i);
267 list_for_each_entry(child_bus, &b->children, node)
268 pcibios_claim_one_bus(child_bus);
270 #ifdef CONFIG_HOTPLUG
271 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
274 static void __init pcibios_claim_of_setup(void)
278 list_for_each_entry(b, &pci_root_buses, node)
279 pcibios_claim_one_bus(b);
283 #ifdef CONFIG_PPC_MULTIPLATFORM
284 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
289 prop = (u32 *) get_property(np, name, &len);
290 if (prop && len >= 4)
295 static unsigned int pci_parse_of_flags(u32 addr0)
297 unsigned int flags = 0;
299 if (addr0 & 0x02000000) {
300 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
301 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
302 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
303 if (addr0 & 0x40000000)
304 flags |= IORESOURCE_PREFETCH
305 | PCI_BASE_ADDRESS_MEM_PREFETCH;
306 } else if (addr0 & 0x01000000)
307 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
311 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
313 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
317 struct resource *res;
321 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
324 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
325 for (; proplen >= 20; proplen -= 20, addrs += 5) {
326 flags = pci_parse_of_flags(addrs[0]);
329 base = GET_64BIT(addrs, 1);
330 size = GET_64BIT(addrs, 3);
334 DBG(" base: %llx, size: %llx, i: %x\n",
335 (unsigned long long)base, (unsigned long long)size, i);
337 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
338 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
339 } else if (i == dev->rom_base_reg) {
340 res = &dev->resource[PCI_ROM_RESOURCE];
341 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
343 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
347 res->end = base + size - 1;
349 res->name = pci_name(dev);
350 fixup_resource(res, dev);
354 struct pci_dev *of_create_pci_dev(struct device_node *node,
355 struct pci_bus *bus, int devfn)
360 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
363 type = get_property(node, "device_type", NULL);
367 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
369 memset(dev, 0, sizeof(struct pci_dev));
372 dev->dev.parent = bus->bridge;
373 dev->dev.bus = &pci_bus_type;
375 dev->multifunction = 0; /* maybe a lie? */
377 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
378 dev->device = get_int_prop(node, "device-id", 0xffff);
379 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
380 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
382 dev->cfg_size = pci_cfg_space_size(dev);
384 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
385 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
386 dev->class = get_int_prop(node, "class-code", 0);
388 DBG(" class: 0x%x\n", dev->class);
390 dev->current_state = 4; /* unknown power state */
392 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
393 /* a PCI-PCI bridge */
394 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
395 dev->rom_base_reg = PCI_ROM_ADDRESS1;
396 } else if (!strcmp(type, "cardbus")) {
397 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
399 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
400 dev->rom_base_reg = PCI_ROM_ADDRESS;
402 if (node->n_intrs > 0) {
403 dev->irq = node->intrs[0].line;
404 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
409 pci_parse_of_addrs(node, dev);
411 DBG(" adding to system ...\n");
413 pci_device_add(dev, bus);
415 /* XXX pci_scan_msi_device(dev); */
419 EXPORT_SYMBOL(of_create_pci_dev);
421 void __devinit of_scan_bus(struct device_node *node,
424 struct device_node *child = NULL;
429 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
431 while ((child = of_get_next_child(node, child)) != NULL) {
432 DBG(" * %s\n", child->full_name);
433 reg = (u32 *) get_property(child, "reg", ®len);
434 if (reg == NULL || reglen < 20)
436 devfn = (reg[0] >> 8) & 0xff;
438 /* create a new pci_dev for this device */
439 dev = of_create_pci_dev(child, bus, devfn);
442 DBG("dev header type: %x\n", dev->hdr_type);
444 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
445 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
446 of_scan_pci_bridge(child, dev);
451 EXPORT_SYMBOL(of_scan_bus);
453 void __devinit of_scan_pci_bridge(struct device_node *node,
457 u32 *busrange, *ranges;
459 struct resource *res;
463 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
465 /* parse bus-range property */
466 busrange = (u32 *) get_property(node, "bus-range", &len);
467 if (busrange == NULL || len != 8) {
468 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
472 ranges = (u32 *) get_property(node, "ranges", &len);
473 if (ranges == NULL) {
474 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
479 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
481 printk(KERN_ERR "Failed to create pci bus for %s\n",
486 bus->primary = dev->bus->number;
487 bus->subordinate = busrange[1];
491 /* parse ranges property */
492 /* PCI #address-cells == 3 and #size-cells == 2 always */
493 res = &dev->resource[PCI_BRIDGE_RESOURCES];
494 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
496 bus->resource[i] = res;
500 for (; len >= 32; len -= 32, ranges += 8) {
501 flags = pci_parse_of_flags(ranges[0]);
502 size = GET_64BIT(ranges, 6);
503 if (flags == 0 || size == 0)
505 if (flags & IORESOURCE_IO) {
506 res = bus->resource[0];
508 printk(KERN_ERR "PCI: ignoring extra I/O range"
509 " for bridge %s\n", node->full_name);
513 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
514 printk(KERN_ERR "PCI: too many memory ranges"
515 " for bridge %s\n", node->full_name);
518 res = bus->resource[i];
521 res->start = GET_64BIT(ranges, 1);
522 res->end = res->start + size - 1;
524 fixup_resource(res, dev);
526 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
528 DBG(" bus name: %s\n", bus->name);
530 mode = PCI_PROBE_NORMAL;
531 if (ppc_md.pci_probe_mode)
532 mode = ppc_md.pci_probe_mode(bus);
533 DBG(" probe mode: %d\n", mode);
535 if (mode == PCI_PROBE_DEVTREE)
536 of_scan_bus(node, bus);
537 else if (mode == PCI_PROBE_NORMAL)
538 pci_scan_child_bus(bus);
540 EXPORT_SYMBOL(of_scan_pci_bridge);
541 #endif /* CONFIG_PPC_MULTIPLATFORM */
543 void __devinit scan_phb(struct pci_controller *hose)
546 struct device_node *node = hose->arch_data;
548 struct resource *res;
550 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
552 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
554 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
555 hose->global_number);
558 bus->secondary = hose->first_busno;
561 bus->resource[0] = res = &hose->io_resource;
562 if (res->flags && request_resource(&ioport_resource, res))
563 printk(KERN_ERR "Failed to request PCI IO region "
564 "on PCI domain %04x\n", hose->global_number);
566 for (i = 0; i < 3; ++i) {
567 res = &hose->mem_resources[i];
568 bus->resource[i+1] = res;
569 if (res->flags && request_resource(&iomem_resource, res))
570 printk(KERN_ERR "Failed to request PCI memory region "
571 "on PCI domain %04x\n", hose->global_number);
574 mode = PCI_PROBE_NORMAL;
575 #ifdef CONFIG_PPC_MULTIPLATFORM
576 if (node && ppc_md.pci_probe_mode)
577 mode = ppc_md.pci_probe_mode(bus);
578 DBG(" probe mode: %d\n", mode);
579 if (mode == PCI_PROBE_DEVTREE) {
580 bus->subordinate = hose->last_busno;
581 of_scan_bus(node, bus);
583 #endif /* CONFIG_PPC_MULTIPLATFORM */
584 if (mode == PCI_PROBE_NORMAL)
585 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
588 static int __init pcibios_init(void)
590 struct pci_controller *hose, *tmp;
592 /* For now, override phys_mem_access_prot. If we need it,
593 * later, we may move that initialization to each ppc_md
595 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
597 #ifdef CONFIG_PPC_ISERIES
598 iSeries_pcibios_init();
601 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
603 /* Scan all of the recorded PCI controllers. */
604 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
606 pci_bus_add_devices(hose->bus);
609 #ifndef CONFIG_PPC_ISERIES
611 pcibios_claim_of_setup();
613 /* FIXME: `else' will be removed when
614 pci_assign_unassigned_resources() is able to work
615 correctly with [partially] allocated PCI tree. */
616 pci_assign_unassigned_resources();
617 #endif /* !CONFIG_PPC_ISERIES */
619 /* Call machine dependent final fixup */
620 if (ppc_md.pcibios_fixup)
621 ppc_md.pcibios_fixup();
623 /* Cache the location of the ISA bridge (if we have one) */
624 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
625 if (ppc64_isabridge_dev != NULL)
626 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
628 #ifdef CONFIG_PPC_MULTIPLATFORM
629 /* map in PCI I/O space */
633 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
638 subsys_initcall(pcibios_init);
640 char __init *pcibios_setup(char *str)
645 int pcibios_enable_device(struct pci_dev *dev, int mask)
650 pci_read_config_word(dev, PCI_COMMAND, &cmd);
653 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
654 struct resource *res = &dev->resource[i];
656 /* Only set up the requested stuff */
657 if (!(mask & (1<<i)))
660 if (res->flags & IORESOURCE_IO)
661 cmd |= PCI_COMMAND_IO;
662 if (res->flags & IORESOURCE_MEM)
663 cmd |= PCI_COMMAND_MEMORY;
667 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
669 /* Enable the appropriate bits in the PCI command register. */
670 pci_write_config_word(dev, PCI_COMMAND, cmd);
676 * Return the domain number for this bus.
678 int pci_domain_nr(struct pci_bus *bus)
680 #ifdef CONFIG_PPC_ISERIES
683 struct pci_controller *hose = pci_bus_to_host(bus);
685 return hose->global_number;
689 EXPORT_SYMBOL(pci_domain_nr);
691 /* Decide whether to display the domain number in /proc */
692 int pci_proc_domain(struct pci_bus *bus)
694 #ifdef CONFIG_PPC_ISERIES
697 struct pci_controller *hose = pci_bus_to_host(bus);
703 * Platform support for /proc/bus/pci/X/Y mmap()s,
704 * modelled on the sparc64 implementation by Dave Miller.
709 * Adjust vm_pgoff of VMA such that it is the physical page offset
710 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
712 * Basically, the user finds the base address for his device which he wishes
713 * to mmap. They read the 32-bit value from the config space base register,
714 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
715 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
717 * Returns negative error code on failure, zero on success.
719 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
720 unsigned long *offset,
721 enum pci_mmap_state mmap_state)
723 struct pci_controller *hose = pci_bus_to_host(dev->bus);
724 unsigned long io_offset = 0;
728 return NULL; /* should never happen */
730 /* If memory, add on the PCI bridge address offset */
731 if (mmap_state == pci_mmap_mem) {
732 *offset += hose->pci_mem_offset;
733 res_bit = IORESOURCE_MEM;
735 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
736 *offset += io_offset;
737 res_bit = IORESOURCE_IO;
741 * Check that the offset requested corresponds to one of the
742 * resources of the device.
744 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
745 struct resource *rp = &dev->resource[i];
746 int flags = rp->flags;
748 /* treat ROM as memory (should be already) */
749 if (i == PCI_ROM_RESOURCE)
750 flags |= IORESOURCE_MEM;
752 /* Active and same type? */
753 if ((flags & res_bit) == 0)
756 /* In the range of this resource? */
757 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
760 /* found it! construct the final physical address */
761 if (mmap_state == pci_mmap_io)
762 *offset += hose->io_base_phys - io_offset;
770 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
773 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
775 enum pci_mmap_state mmap_state,
778 unsigned long prot = pgprot_val(protection);
780 /* Write combine is always 0 on non-memory space mappings. On
781 * memory space, if the user didn't pass 1, we check for a
782 * "prefetchable" resource. This is a bit hackish, but we use
783 * this to workaround the inability of /sysfs to provide a write
786 if (mmap_state != pci_mmap_mem)
788 else if (write_combine == 0) {
789 if (rp->flags & IORESOURCE_PREFETCH)
793 /* XXX would be nice to have a way to ask for write-through */
794 prot |= _PAGE_NO_CACHE;
796 prot &= ~_PAGE_GUARDED;
798 prot |= _PAGE_GUARDED;
800 printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
803 return __pgprot(prot);
807 * This one is used by /dev/mem and fbdev who have no clue about the
808 * PCI device, it tries to find the PCI device first and calls the
811 pgprot_t pci_phys_mem_access_prot(struct file *file,
816 struct pci_dev *pdev = NULL;
817 struct resource *found = NULL;
818 unsigned long prot = pgprot_val(protection);
819 unsigned long offset = pfn << PAGE_SHIFT;
822 if (page_is_ram(pfn))
823 return __pgprot(prot);
825 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
827 for_each_pci_dev(pdev) {
828 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
829 struct resource *rp = &pdev->resource[i];
830 int flags = rp->flags;
832 /* Active and same type? */
833 if ((flags & IORESOURCE_MEM) == 0)
835 /* In the range of this resource? */
836 if (offset < (rp->start & PAGE_MASK) ||
846 if (found->flags & IORESOURCE_PREFETCH)
847 prot &= ~_PAGE_GUARDED;
851 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
853 return __pgprot(prot);
858 * Perform the actual remap of the pages for a PCI device mapping, as
859 * appropriate for this architecture. The region in the process to map
860 * is described by vm_start and vm_end members of VMA, the base physical
861 * address is found in vm_pgoff.
862 * The pci device structure is provided so that architectures may make mapping
863 * decisions on a per-device or per-bus basis.
865 * Returns a negative error code on failure, zero on success.
867 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
868 enum pci_mmap_state mmap_state, int write_combine)
870 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
874 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
878 vma->vm_pgoff = offset >> PAGE_SHIFT;
879 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
881 mmap_state, write_combine);
883 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
884 vma->vm_end - vma->vm_start, vma->vm_page_prot);
889 static ssize_t pci_show_devspec(struct device *dev,
890 struct device_attribute *attr, char *buf)
892 struct pci_dev *pdev;
893 struct device_node *np;
895 pdev = to_pci_dev (dev);
896 np = pci_device_to_OF_node(pdev);
897 if (np == NULL || np->full_name == NULL)
899 return sprintf(buf, "%s", np->full_name);
901 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
903 void pcibios_add_platform_entries(struct pci_dev *pdev)
905 device_create_file(&pdev->dev, &dev_attr_devspec);
908 #ifdef CONFIG_PPC_MULTIPLATFORM
910 #define ISA_SPACE_MASK 0x1
911 #define ISA_SPACE_IO 0x1
913 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
914 unsigned long phb_io_base_phys,
915 void __iomem * phb_io_base_virt)
917 /* Remove these asap */
931 struct isa_address isa_addr;
932 struct pci_address pci_addr;
936 struct isa_range *range;
937 unsigned long pci_addr;
938 unsigned int isa_addr;
942 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
943 if (range == NULL || (rlen < sizeof(struct isa_range))) {
944 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
946 __ioremap_explicit(phb_io_base_phys,
947 (unsigned long)phb_io_base_virt,
948 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
952 /* From "ISA Binding to 1275"
953 * The ranges property is laid out as an array of elements,
954 * each of which comprises:
955 * cells 0 - 1: an ISA address
956 * cells 2 - 4: a PCI address
957 * (size depending on dev->n_addr_cells)
958 * cell 5: the size of the range
960 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
961 isa_addr = range->isa_addr.a_lo;
962 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
963 range->pci_addr.a_lo;
965 /* Assume these are both zero */
966 if ((pci_addr != 0) || (isa_addr != 0)) {
967 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
972 size = PAGE_ALIGN(range->size);
974 __ioremap_explicit(phb_io_base_phys,
975 (unsigned long) phb_io_base_virt,
976 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
980 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
981 struct device_node *dev, int prim)
983 unsigned int *ranges, pci_space;
987 struct resource *res;
988 int np, na = prom_n_addr_cells(dev);
989 unsigned long pci_addr, cpu_phys_addr;
993 /* From "PCI Binding to 1275"
994 * The ranges property is laid out as an array of elements,
995 * each of which comprises:
996 * cells 0 - 2: a PCI address
997 * cells 3 or 3+4: a CPU physical address
998 * (size depending on dev->n_addr_cells)
999 * cells 4+5 or 5+6: the size of the range
1001 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
1004 hose->io_base_phys = 0;
1005 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
1007 pci_space = ranges[0];
1008 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1010 cpu_phys_addr = ranges[3];
1012 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
1014 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
1019 /* Now consume following elements while they are contiguous */
1020 while (rlen >= np * sizeof(unsigned int)) {
1021 unsigned long addr, phys;
1023 if (ranges[0] != pci_space)
1025 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1028 phys = (phys << 32) | ranges[4];
1029 if (addr != pci_addr + size ||
1030 phys != cpu_phys_addr + size)
1033 size += ((unsigned long)ranges[na+3] << 32)
1036 rlen -= np * sizeof(unsigned int);
1039 switch ((pci_space >> 24) & 0x3) {
1040 case 1: /* I/O space */
1041 hose->io_base_phys = cpu_phys_addr;
1042 hose->pci_io_size = size;
1044 res = &hose->io_resource;
1045 res->flags = IORESOURCE_IO;
1046 res->start = pci_addr;
1047 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1048 res->start, res->start + size - 1);
1050 case 2: /* memory space */
1052 while (memno < 3 && hose->mem_resources[memno].flags)
1056 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1058 res = &hose->mem_resources[memno];
1059 res->flags = IORESOURCE_MEM;
1060 res->start = cpu_phys_addr;
1061 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1062 res->start, res->start + size - 1);
1067 res->name = dev->full_name;
1068 res->end = res->start + size - 1;
1070 res->sibling = NULL;
1076 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1078 unsigned long size = hose->pci_io_size;
1079 unsigned long io_virt_offset;
1080 struct resource *res;
1081 struct device_node *isa_dn;
1083 hose->io_base_virt = reserve_phb_iospace(size);
1084 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1085 hose->global_number, hose->io_base_phys,
1086 (unsigned long) hose->io_base_virt);
1089 pci_io_base = (unsigned long)hose->io_base_virt;
1090 isa_dn = of_find_node_by_type(NULL, "isa");
1092 isa_io_base = pci_io_base;
1093 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1094 hose->io_base_virt);
1095 of_node_put(isa_dn);
1099 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1100 res = &hose->io_resource;
1101 res->start += io_virt_offset;
1102 res->end += io_virt_offset;
1105 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1108 unsigned long size = hose->pci_io_size;
1109 unsigned long io_virt_offset;
1110 struct resource *res;
1112 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1113 _PAGE_NO_CACHE | _PAGE_GUARDED);
1114 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1115 hose->global_number, hose->io_base_phys,
1116 (unsigned long) hose->io_base_virt);
1119 pci_io_base = (unsigned long)hose->io_base_virt;
1121 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1122 res = &hose->io_resource;
1123 res->start += io_virt_offset;
1124 res->end += io_virt_offset;
1128 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1129 unsigned long *start_virt, unsigned long *size)
1131 struct pci_controller *hose = pci_bus_to_host(bus);
1132 struct pci_bus_region region;
1133 struct resource *res;
1136 res = bus->resource[0];
1137 pcibios_resource_to_bus(bus->self, ®ion, res);
1138 *start_phys = hose->io_base_phys + region.start;
1139 *start_virt = (unsigned long) hose->io_base_virt +
1141 if (region.end > region.start)
1142 *size = region.end - region.start + 1;
1144 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1145 __FUNCTION__, region.start, region.end);
1151 res = &hose->io_resource;
1152 *start_phys = hose->io_base_phys;
1153 *start_virt = (unsigned long) hose->io_base_virt;
1154 if (res->end > res->start)
1155 *size = res->end - res->start + 1;
1157 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1158 __FUNCTION__, res->start, res->end);
1166 int unmap_bus_range(struct pci_bus *bus)
1168 unsigned long start_phys;
1169 unsigned long start_virt;
1173 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1177 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1179 if (iounmap_explicit((void __iomem *) start_virt, size))
1184 EXPORT_SYMBOL(unmap_bus_range);
1186 int remap_bus_range(struct pci_bus *bus)
1188 unsigned long start_phys;
1189 unsigned long start_virt;
1193 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1198 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1200 if (start_phys == 0)
1202 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1203 if (__ioremap_explicit(start_phys, start_virt, size,
1204 _PAGE_NO_CACHE | _PAGE_GUARDED))
1209 EXPORT_SYMBOL(remap_bus_range);
1211 static void phbs_remap_io(void)
1213 struct pci_controller *hose, *tmp;
1215 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1216 remap_bus_range(hose->bus);
1219 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1221 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1222 unsigned long offset;
1224 if (res->flags & IORESOURCE_IO) {
1225 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1227 res->start += offset;
1229 } else if (res->flags & IORESOURCE_MEM) {
1230 res->start += hose->pci_mem_offset;
1231 res->end += hose->pci_mem_offset;
1235 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1236 struct pci_bus *bus)
1238 /* Update device resources. */
1241 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1242 if (dev->resource[i].flags)
1243 fixup_resource(&dev->resource[i], dev);
1245 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1248 static void __devinit do_bus_setup(struct pci_bus *bus)
1250 struct pci_dev *dev;
1252 ppc_md.iommu_bus_setup(bus);
1254 list_for_each_entry(dev, &bus->devices, bus_list)
1255 ppc_md.iommu_dev_setup(dev);
1257 if (ppc_md.irq_bus_setup)
1258 ppc_md.irq_bus_setup(bus);
1261 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1263 struct pci_dev *dev = bus->self;
1265 if (dev && pci_probe_only &&
1266 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1267 /* This is a subordinate bridge */
1269 pci_read_bridge_bases(bus);
1270 pcibios_fixup_device_resources(dev, bus);
1275 if (!pci_probe_only)
1278 list_for_each_entry(dev, &bus->devices, bus_list)
1279 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1280 pcibios_fixup_device_resources(dev, bus);
1282 EXPORT_SYMBOL(pcibios_fixup_bus);
1285 * Reads the interrupt pin to determine if interrupt is use by card.
1286 * If the interrupt is used, then gets the interrupt line from the
1287 * openfirmware and sets it in the pci_dev and pci_config line.
1289 int pci_read_irq_line(struct pci_dev *pci_dev)
1292 struct device_node *node;
1294 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1298 node = pci_device_to_OF_node(pci_dev);
1302 if (node->n_intrs == 0)
1305 pci_dev->irq = node->intrs[0].line;
1307 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1311 EXPORT_SYMBOL(pci_read_irq_line);
1313 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1314 const struct resource *rsrc,
1315 u64 *start, u64 *end)
1317 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1318 unsigned long offset = 0;
1323 if (rsrc->flags & IORESOURCE_IO)
1324 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1327 *start = rsrc->start + offset;
1328 *end = rsrc->end + offset;
1331 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1336 struct pci_controller *hose, *tmp;
1337 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1338 if (hose->arch_data == node)
1340 node = node->parent;
1345 #endif /* CONFIG_PPC_MULTIPLATFORM */
1347 unsigned long pci_address_to_pio(phys_addr_t address)
1349 struct pci_controller *hose, *tmp;
1351 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1352 if (address >= hose->io_base_phys &&
1353 address < (hose->io_base_phys + hose->pci_io_size)) {
1354 unsigned long base =
1355 (unsigned long)hose->io_base_virt - pci_io_base;
1356 return base + (address - hose->io_base_phys);
1359 return (unsigned int)-1;
1361 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1364 #define IOBASE_BRIDGE_NUMBER 0
1365 #define IOBASE_MEMORY 1
1367 #define IOBASE_ISA_IO 3
1368 #define IOBASE_ISA_MEM 4
1370 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1371 unsigned long in_devfn)
1373 struct pci_controller* hose;
1374 struct list_head *ln;
1375 struct pci_bus *bus = NULL;
1376 struct device_node *hose_node;
1378 /* Argh ! Please forgive me for that hack, but that's the
1379 * simplest way to get existing XFree to not lockup on some
1380 * G5 machines... So when something asks for bus 0 io base
1381 * (bus 0 is HT root), we return the AGP one instead.
1383 if (machine_is_compatible("MacRISC4"))
1387 /* That syscall isn't quite compatible with PCI domains, but it's
1388 * used on pre-domains setup. We return the first match
1391 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1392 bus = pci_bus_b(ln);
1393 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1397 if (bus == NULL || bus->sysdata == NULL)
1400 hose_node = (struct device_node *)bus->sysdata;
1401 hose = PCI_DN(hose_node)->phb;
1404 case IOBASE_BRIDGE_NUMBER:
1405 return (long)hose->first_busno;
1407 return (long)hose->pci_mem_offset;
1409 return (long)hose->io_base_phys;
1411 return (long)isa_io_base;
1412 case IOBASE_ISA_MEM:
1420 int pcibus_to_node(struct pci_bus *bus)
1422 struct pci_controller *phb = pci_bus_to_host(bus);
1425 EXPORT_SYMBOL(pcibus_to_node);