2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/firmware.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
45 static void fixup_resource(struct resource *res, struct pci_dev *dev);
46 static void do_bus_setup(struct pci_bus *bus);
47 static void phbs_remap_io(void);
49 /* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
53 * page is mapped and isa_io_limit prevents access to it.
55 unsigned long isa_io_base; /* NULL if no ISA bus */
56 EXPORT_SYMBOL(isa_io_base);
57 unsigned long pci_io_base;
58 EXPORT_SYMBOL(pci_io_base);
60 void iSeries_pcibios_init(void);
64 struct dma_mapping_ops pci_dma_ops;
65 EXPORT_SYMBOL(pci_dma_ops);
67 int global_phb_number; /* Global phb counter */
69 /* Cached ISA bridge dev. */
70 struct pci_dev *ppc64_isabridge_dev = NULL;
71 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
73 static void fixup_broken_pcnet32(struct pci_dev* dev)
75 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
76 dev->vendor = PCI_VENDOR_ID_AMD;
77 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
80 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
82 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
85 unsigned long offset = 0;
86 struct pci_controller *hose = pci_bus_to_host(dev->bus);
91 if (res->flags & IORESOURCE_IO)
92 offset = (unsigned long)hose->io_base_virt - pci_io_base;
94 if (res->flags & IORESOURCE_MEM)
95 offset = hose->pci_mem_offset;
97 region->start = res->start - offset;
98 region->end = res->end - offset;
101 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
102 struct pci_bus_region *region)
104 unsigned long offset = 0;
105 struct pci_controller *hose = pci_bus_to_host(dev->bus);
110 if (res->flags & IORESOURCE_IO)
111 offset = (unsigned long)hose->io_base_virt - pci_io_base;
113 if (res->flags & IORESOURCE_MEM)
114 offset = hose->pci_mem_offset;
116 res->start = region->start + offset;
117 res->end = region->end + offset;
120 #ifdef CONFIG_HOTPLUG
121 EXPORT_SYMBOL(pcibios_resource_to_bus);
122 EXPORT_SYMBOL(pcibios_bus_to_resource);
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
138 void pcibios_align_resource(void *data, struct resource *res,
139 resource_size_t size, resource_size_t align)
141 struct pci_dev *dev = data;
142 struct pci_controller *hose = pci_bus_to_host(dev->bus);
143 resource_size_t start = res->start;
144 unsigned long alignto;
146 if (res->flags & IORESOURCE_IO) {
147 unsigned long offset = (unsigned long)hose->io_base_virt -
149 /* Make sure we start at our min on all hoses */
150 if (start - offset < PCIBIOS_MIN_IO)
151 start = PCIBIOS_MIN_IO + offset;
154 * Put everything into 0x00-0xff region modulo 0x400
157 start = (start + 0x3ff) & ~0x3ff;
159 } else if (res->flags & IORESOURCE_MEM) {
160 /* Make sure we start at our min on all hoses */
161 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
162 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
164 /* Align to multiple of size of minimum base. */
165 alignto = max(0x1000UL, align);
166 start = ALIGN(start, alignto);
172 static DEFINE_SPINLOCK(hose_spinlock);
175 * pci_controller(phb) initialized common variables.
177 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
179 memset(hose, 0, sizeof(struct pci_controller));
181 spin_lock(&hose_spinlock);
182 hose->global_number = global_phb_number++;
183 list_add_tail(&hose->list_node, &hose_list);
184 spin_unlock(&hose_spinlock);
187 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
189 struct pci_controller *phb;
192 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
194 phb = alloc_bootmem(sizeof (struct pci_controller));
197 pci_setup_pci_controller(phb);
198 phb->arch_data = dev;
199 phb->is_dynamic = mem_init_done;
201 int nid = of_node_to_nid(dev);
203 if (nid < 0 || !node_online(nid))
206 PHB_SET_NODE(phb, nid);
211 void pcibios_free_controller(struct pci_controller *phb)
217 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
220 struct pci_bus *child_bus;
222 list_for_each_entry(dev, &b->devices, bus_list) {
225 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
226 struct resource *r = &dev->resource[i];
228 if (r->parent || !r->start || !r->flags)
230 pci_claim_resource(dev, i);
234 list_for_each_entry(child_bus, &b->children, node)
235 pcibios_claim_one_bus(child_bus);
237 #ifdef CONFIG_HOTPLUG
238 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
241 static void __init pcibios_claim_of_setup(void)
245 if (firmware_has_feature(FW_FEATURE_ISERIES))
248 list_for_each_entry(b, &pci_root_buses, node)
249 pcibios_claim_one_bus(b);
252 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
257 prop = get_property(np, name, &len);
258 if (prop && len >= 4)
263 static unsigned int pci_parse_of_flags(u32 addr0)
265 unsigned int flags = 0;
267 if (addr0 & 0x02000000) {
268 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
269 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
270 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
271 if (addr0 & 0x40000000)
272 flags |= IORESOURCE_PREFETCH
273 | PCI_BASE_ADDRESS_MEM_PREFETCH;
274 } else if (addr0 & 0x01000000)
275 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
279 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
281 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
285 struct resource *res;
290 addrs = get_property(node, "assigned-addresses", &proplen);
293 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
294 for (; proplen >= 20; proplen -= 20, addrs += 5) {
295 flags = pci_parse_of_flags(addrs[0]);
298 base = GET_64BIT(addrs, 1);
299 size = GET_64BIT(addrs, 3);
303 DBG(" base: %llx, size: %llx, i: %x\n",
304 (unsigned long long)base, (unsigned long long)size, i);
306 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
307 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
308 } else if (i == dev->rom_base_reg) {
309 res = &dev->resource[PCI_ROM_RESOURCE];
310 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
312 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
316 res->end = base + size - 1;
318 res->name = pci_name(dev);
319 fixup_resource(res, dev);
323 struct pci_dev *of_create_pci_dev(struct device_node *node,
324 struct pci_bus *bus, int devfn)
329 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
332 type = get_property(node, "device_type", NULL);
336 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
338 memset(dev, 0, sizeof(struct pci_dev));
341 dev->dev.parent = bus->bridge;
342 dev->dev.bus = &pci_bus_type;
344 dev->multifunction = 0; /* maybe a lie? */
346 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
347 dev->device = get_int_prop(node, "device-id", 0xffff);
348 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
349 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
351 dev->cfg_size = pci_cfg_space_size(dev);
353 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
354 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
355 dev->class = get_int_prop(node, "class-code", 0);
357 DBG(" class: 0x%x\n", dev->class);
359 dev->current_state = 4; /* unknown power state */
361 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
362 /* a PCI-PCI bridge */
363 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
364 dev->rom_base_reg = PCI_ROM_ADDRESS1;
365 } else if (!strcmp(type, "cardbus")) {
366 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
368 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
369 dev->rom_base_reg = PCI_ROM_ADDRESS;
370 /* Maybe do a default OF mapping here */
374 pci_parse_of_addrs(node, dev);
376 DBG(" adding to system ...\n");
378 pci_device_add(dev, bus);
380 /* XXX pci_scan_msi_device(dev); */
384 EXPORT_SYMBOL(of_create_pci_dev);
386 void __devinit of_scan_bus(struct device_node *node,
389 struct device_node *child = NULL;
394 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
396 while ((child = of_get_next_child(node, child)) != NULL) {
397 DBG(" * %s\n", child->full_name);
398 reg = get_property(child, "reg", ®len);
399 if (reg == NULL || reglen < 20)
401 devfn = (reg[0] >> 8) & 0xff;
403 /* create a new pci_dev for this device */
404 dev = of_create_pci_dev(child, bus, devfn);
407 DBG("dev header type: %x\n", dev->hdr_type);
409 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
410 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
411 of_scan_pci_bridge(child, dev);
416 EXPORT_SYMBOL(of_scan_bus);
418 void __devinit of_scan_pci_bridge(struct device_node *node,
422 const u32 *busrange, *ranges;
424 struct resource *res;
428 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
430 /* parse bus-range property */
431 busrange = get_property(node, "bus-range", &len);
432 if (busrange == NULL || len != 8) {
433 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
437 ranges = get_property(node, "ranges", &len);
438 if (ranges == NULL) {
439 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
444 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
446 printk(KERN_ERR "Failed to create pci bus for %s\n",
451 bus->primary = dev->bus->number;
452 bus->subordinate = busrange[1];
456 /* parse ranges property */
457 /* PCI #address-cells == 3 and #size-cells == 2 always */
458 res = &dev->resource[PCI_BRIDGE_RESOURCES];
459 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
461 bus->resource[i] = res;
465 for (; len >= 32; len -= 32, ranges += 8) {
466 flags = pci_parse_of_flags(ranges[0]);
467 size = GET_64BIT(ranges, 6);
468 if (flags == 0 || size == 0)
470 if (flags & IORESOURCE_IO) {
471 res = bus->resource[0];
473 printk(KERN_ERR "PCI: ignoring extra I/O range"
474 " for bridge %s\n", node->full_name);
478 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
479 printk(KERN_ERR "PCI: too many memory ranges"
480 " for bridge %s\n", node->full_name);
483 res = bus->resource[i];
486 res->start = GET_64BIT(ranges, 1);
487 res->end = res->start + size - 1;
489 fixup_resource(res, dev);
491 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
493 DBG(" bus name: %s\n", bus->name);
495 mode = PCI_PROBE_NORMAL;
496 if (ppc_md.pci_probe_mode)
497 mode = ppc_md.pci_probe_mode(bus);
498 DBG(" probe mode: %d\n", mode);
500 if (mode == PCI_PROBE_DEVTREE)
501 of_scan_bus(node, bus);
502 else if (mode == PCI_PROBE_NORMAL)
503 pci_scan_child_bus(bus);
505 EXPORT_SYMBOL(of_scan_pci_bridge);
507 void __devinit scan_phb(struct pci_controller *hose)
510 struct device_node *node = hose->arch_data;
512 struct resource *res;
514 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
516 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
518 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
519 hose->global_number);
522 bus->secondary = hose->first_busno;
525 bus->resource[0] = res = &hose->io_resource;
526 if (res->flags && request_resource(&ioport_resource, res))
527 printk(KERN_ERR "Failed to request PCI IO region "
528 "on PCI domain %04x\n", hose->global_number);
530 for (i = 0; i < 3; ++i) {
531 res = &hose->mem_resources[i];
532 bus->resource[i+1] = res;
533 if (res->flags && request_resource(&iomem_resource, res))
534 printk(KERN_ERR "Failed to request PCI memory region "
535 "on PCI domain %04x\n", hose->global_number);
538 mode = PCI_PROBE_NORMAL;
540 if (node && ppc_md.pci_probe_mode)
541 mode = ppc_md.pci_probe_mode(bus);
542 DBG(" probe mode: %d\n", mode);
543 if (mode == PCI_PROBE_DEVTREE) {
544 bus->subordinate = hose->last_busno;
545 of_scan_bus(node, bus);
548 if (mode == PCI_PROBE_NORMAL)
549 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
552 static int __init pcibios_init(void)
554 struct pci_controller *hose, *tmp;
556 /* For now, override phys_mem_access_prot. If we need it,
557 * later, we may move that initialization to each ppc_md
559 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
561 if (firmware_has_feature(FW_FEATURE_ISERIES))
562 iSeries_pcibios_init();
564 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
566 /* Scan all of the recorded PCI controllers. */
567 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
569 pci_bus_add_devices(hose->bus);
572 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
574 pcibios_claim_of_setup();
576 /* FIXME: `else' will be removed when
577 pci_assign_unassigned_resources() is able to work
578 correctly with [partially] allocated PCI tree. */
579 pci_assign_unassigned_resources();
582 /* Call machine dependent final fixup */
583 if (ppc_md.pcibios_fixup)
584 ppc_md.pcibios_fixup();
586 /* Cache the location of the ISA bridge (if we have one) */
587 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
588 if (ppc64_isabridge_dev != NULL)
589 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
591 if (!firmware_has_feature(FW_FEATURE_ISERIES))
592 /* map in PCI I/O space */
595 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
600 subsys_initcall(pcibios_init);
602 char __init *pcibios_setup(char *str)
607 int pcibios_enable_device(struct pci_dev *dev, int mask)
612 pci_read_config_word(dev, PCI_COMMAND, &cmd);
615 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
616 struct resource *res = &dev->resource[i];
618 /* Only set up the requested stuff */
619 if (!(mask & (1<<i)))
622 if (res->flags & IORESOURCE_IO)
623 cmd |= PCI_COMMAND_IO;
624 if (res->flags & IORESOURCE_MEM)
625 cmd |= PCI_COMMAND_MEMORY;
629 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
631 /* Enable the appropriate bits in the PCI command register. */
632 pci_write_config_word(dev, PCI_COMMAND, cmd);
638 * Return the domain number for this bus.
640 int pci_domain_nr(struct pci_bus *bus)
642 if (firmware_has_feature(FW_FEATURE_ISERIES))
645 struct pci_controller *hose = pci_bus_to_host(bus);
647 return hose->global_number;
651 EXPORT_SYMBOL(pci_domain_nr);
653 /* Decide whether to display the domain number in /proc */
654 int pci_proc_domain(struct pci_bus *bus)
656 if (firmware_has_feature(FW_FEATURE_ISERIES))
659 struct pci_controller *hose = pci_bus_to_host(bus);
665 * Platform support for /proc/bus/pci/X/Y mmap()s,
666 * modelled on the sparc64 implementation by Dave Miller.
671 * Adjust vm_pgoff of VMA such that it is the physical page offset
672 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
674 * Basically, the user finds the base address for his device which he wishes
675 * to mmap. They read the 32-bit value from the config space base register,
676 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
677 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
679 * Returns negative error code on failure, zero on success.
681 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
682 unsigned long *offset,
683 enum pci_mmap_state mmap_state)
685 struct pci_controller *hose = pci_bus_to_host(dev->bus);
686 unsigned long io_offset = 0;
690 return NULL; /* should never happen */
692 /* If memory, add on the PCI bridge address offset */
693 if (mmap_state == pci_mmap_mem) {
694 *offset += hose->pci_mem_offset;
695 res_bit = IORESOURCE_MEM;
697 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
698 *offset += io_offset;
699 res_bit = IORESOURCE_IO;
703 * Check that the offset requested corresponds to one of the
704 * resources of the device.
706 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
707 struct resource *rp = &dev->resource[i];
708 int flags = rp->flags;
710 /* treat ROM as memory (should be already) */
711 if (i == PCI_ROM_RESOURCE)
712 flags |= IORESOURCE_MEM;
714 /* Active and same type? */
715 if ((flags & res_bit) == 0)
718 /* In the range of this resource? */
719 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
722 /* found it! construct the final physical address */
723 if (mmap_state == pci_mmap_io)
724 *offset += hose->io_base_phys - io_offset;
732 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
735 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
737 enum pci_mmap_state mmap_state,
740 unsigned long prot = pgprot_val(protection);
742 /* Write combine is always 0 on non-memory space mappings. On
743 * memory space, if the user didn't pass 1, we check for a
744 * "prefetchable" resource. This is a bit hackish, but we use
745 * this to workaround the inability of /sysfs to provide a write
748 if (mmap_state != pci_mmap_mem)
750 else if (write_combine == 0) {
751 if (rp->flags & IORESOURCE_PREFETCH)
755 /* XXX would be nice to have a way to ask for write-through */
756 prot |= _PAGE_NO_CACHE;
758 prot &= ~_PAGE_GUARDED;
760 prot |= _PAGE_GUARDED;
762 printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
765 return __pgprot(prot);
769 * This one is used by /dev/mem and fbdev who have no clue about the
770 * PCI device, it tries to find the PCI device first and calls the
773 pgprot_t pci_phys_mem_access_prot(struct file *file,
778 struct pci_dev *pdev = NULL;
779 struct resource *found = NULL;
780 unsigned long prot = pgprot_val(protection);
781 unsigned long offset = pfn << PAGE_SHIFT;
784 if (page_is_ram(pfn))
785 return __pgprot(prot);
787 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
789 for_each_pci_dev(pdev) {
790 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
791 struct resource *rp = &pdev->resource[i];
792 int flags = rp->flags;
794 /* Active and same type? */
795 if ((flags & IORESOURCE_MEM) == 0)
797 /* In the range of this resource? */
798 if (offset < (rp->start & PAGE_MASK) ||
808 if (found->flags & IORESOURCE_PREFETCH)
809 prot &= ~_PAGE_GUARDED;
813 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
815 return __pgprot(prot);
820 * Perform the actual remap of the pages for a PCI device mapping, as
821 * appropriate for this architecture. The region in the process to map
822 * is described by vm_start and vm_end members of VMA, the base physical
823 * address is found in vm_pgoff.
824 * The pci device structure is provided so that architectures may make mapping
825 * decisions on a per-device or per-bus basis.
827 * Returns a negative error code on failure, zero on success.
829 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
830 enum pci_mmap_state mmap_state, int write_combine)
832 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
836 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
840 vma->vm_pgoff = offset >> PAGE_SHIFT;
841 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
843 mmap_state, write_combine);
845 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
846 vma->vm_end - vma->vm_start, vma->vm_page_prot);
851 static ssize_t pci_show_devspec(struct device *dev,
852 struct device_attribute *attr, char *buf)
854 struct pci_dev *pdev;
855 struct device_node *np;
857 pdev = to_pci_dev (dev);
858 np = pci_device_to_OF_node(pdev);
859 if (np == NULL || np->full_name == NULL)
861 return sprintf(buf, "%s", np->full_name);
863 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
865 void pcibios_add_platform_entries(struct pci_dev *pdev)
867 device_create_file(&pdev->dev, &dev_attr_devspec);
870 #define ISA_SPACE_MASK 0x1
871 #define ISA_SPACE_IO 0x1
873 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
874 unsigned long phb_io_base_phys,
875 void __iomem * phb_io_base_virt)
877 /* Remove these asap */
891 struct isa_address isa_addr;
892 struct pci_address pci_addr;
896 const struct isa_range *range;
897 unsigned long pci_addr;
898 unsigned int isa_addr;
902 range = get_property(isa_node, "ranges", &rlen);
903 if (range == NULL || (rlen < sizeof(struct isa_range))) {
904 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
906 __ioremap_explicit(phb_io_base_phys,
907 (unsigned long)phb_io_base_virt,
908 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
912 /* From "ISA Binding to 1275"
913 * The ranges property is laid out as an array of elements,
914 * each of which comprises:
915 * cells 0 - 1: an ISA address
916 * cells 2 - 4: a PCI address
917 * (size depending on dev->n_addr_cells)
918 * cell 5: the size of the range
920 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
921 isa_addr = range->isa_addr.a_lo;
922 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
923 range->pci_addr.a_lo;
925 /* Assume these are both zero */
926 if ((pci_addr != 0) || (isa_addr != 0)) {
927 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
932 size = PAGE_ALIGN(range->size);
934 __ioremap_explicit(phb_io_base_phys,
935 (unsigned long) phb_io_base_virt,
936 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
940 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
941 struct device_node *dev, int prim)
943 const unsigned int *ranges;
944 unsigned int pci_space;
948 struct resource *res;
949 int np, na = prom_n_addr_cells(dev);
950 unsigned long pci_addr, cpu_phys_addr;
954 /* From "PCI Binding to 1275"
955 * The ranges property is laid out as an array of elements,
956 * each of which comprises:
957 * cells 0 - 2: a PCI address
958 * cells 3 or 3+4: a CPU physical address
959 * (size depending on dev->n_addr_cells)
960 * cells 4+5 or 5+6: the size of the range
962 ranges = get_property(dev, "ranges", &rlen);
965 hose->io_base_phys = 0;
966 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
968 pci_space = ranges[0];
969 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
971 cpu_phys_addr = ranges[3];
973 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
975 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
980 /* Now consume following elements while they are contiguous */
981 while (rlen >= np * sizeof(unsigned int)) {
982 unsigned long addr, phys;
984 if (ranges[0] != pci_space)
986 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
989 phys = (phys << 32) | ranges[4];
990 if (addr != pci_addr + size ||
991 phys != cpu_phys_addr + size)
994 size += ((unsigned long)ranges[na+3] << 32)
997 rlen -= np * sizeof(unsigned int);
1000 switch ((pci_space >> 24) & 0x3) {
1001 case 1: /* I/O space */
1002 hose->io_base_phys = cpu_phys_addr;
1003 hose->pci_io_size = size;
1005 res = &hose->io_resource;
1006 res->flags = IORESOURCE_IO;
1007 res->start = pci_addr;
1008 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1009 res->start, res->start + size - 1);
1011 case 2: /* memory space */
1013 while (memno < 3 && hose->mem_resources[memno].flags)
1017 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1019 res = &hose->mem_resources[memno];
1020 res->flags = IORESOURCE_MEM;
1021 res->start = cpu_phys_addr;
1022 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1023 res->start, res->start + size - 1);
1028 res->name = dev->full_name;
1029 res->end = res->start + size - 1;
1031 res->sibling = NULL;
1037 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1039 unsigned long size = hose->pci_io_size;
1040 unsigned long io_virt_offset;
1041 struct resource *res;
1042 struct device_node *isa_dn;
1044 hose->io_base_virt = reserve_phb_iospace(size);
1045 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1046 hose->global_number, hose->io_base_phys,
1047 (unsigned long) hose->io_base_virt);
1050 pci_io_base = (unsigned long)hose->io_base_virt;
1051 isa_dn = of_find_node_by_type(NULL, "isa");
1053 isa_io_base = pci_io_base;
1054 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1055 hose->io_base_virt);
1056 of_node_put(isa_dn);
1060 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1061 res = &hose->io_resource;
1062 res->start += io_virt_offset;
1063 res->end += io_virt_offset;
1066 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1069 unsigned long size = hose->pci_io_size;
1070 unsigned long io_virt_offset;
1071 struct resource *res;
1073 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1074 _PAGE_NO_CACHE | _PAGE_GUARDED);
1075 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1076 hose->global_number, hose->io_base_phys,
1077 (unsigned long) hose->io_base_virt);
1080 pci_io_base = (unsigned long)hose->io_base_virt;
1082 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1083 res = &hose->io_resource;
1084 res->start += io_virt_offset;
1085 res->end += io_virt_offset;
1089 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1090 unsigned long *start_virt, unsigned long *size)
1092 struct pci_controller *hose = pci_bus_to_host(bus);
1093 struct pci_bus_region region;
1094 struct resource *res;
1097 res = bus->resource[0];
1098 pcibios_resource_to_bus(bus->self, ®ion, res);
1099 *start_phys = hose->io_base_phys + region.start;
1100 *start_virt = (unsigned long) hose->io_base_virt +
1102 if (region.end > region.start)
1103 *size = region.end - region.start + 1;
1105 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1106 __FUNCTION__, region.start, region.end);
1112 res = &hose->io_resource;
1113 *start_phys = hose->io_base_phys;
1114 *start_virt = (unsigned long) hose->io_base_virt;
1115 if (res->end > res->start)
1116 *size = res->end - res->start + 1;
1118 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1119 __FUNCTION__, res->start, res->end);
1127 int unmap_bus_range(struct pci_bus *bus)
1129 unsigned long start_phys;
1130 unsigned long start_virt;
1134 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1138 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1140 if (iounmap_explicit((void __iomem *) start_virt, size))
1145 EXPORT_SYMBOL(unmap_bus_range);
1147 int remap_bus_range(struct pci_bus *bus)
1149 unsigned long start_phys;
1150 unsigned long start_virt;
1154 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1159 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1161 if (start_phys == 0)
1163 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1164 if (__ioremap_explicit(start_phys, start_virt, size,
1165 _PAGE_NO_CACHE | _PAGE_GUARDED))
1170 EXPORT_SYMBOL(remap_bus_range);
1172 static void phbs_remap_io(void)
1174 struct pci_controller *hose, *tmp;
1176 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1177 remap_bus_range(hose->bus);
1180 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1182 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1183 unsigned long offset;
1185 if (res->flags & IORESOURCE_IO) {
1186 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1188 res->start += offset;
1190 } else if (res->flags & IORESOURCE_MEM) {
1191 res->start += hose->pci_mem_offset;
1192 res->end += hose->pci_mem_offset;
1196 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1197 struct pci_bus *bus)
1199 /* Update device resources. */
1202 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1203 if (dev->resource[i].flags)
1204 fixup_resource(&dev->resource[i], dev);
1206 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1209 static void __devinit do_bus_setup(struct pci_bus *bus)
1211 struct pci_dev *dev;
1213 ppc_md.iommu_bus_setup(bus);
1215 list_for_each_entry(dev, &bus->devices, bus_list)
1216 ppc_md.iommu_dev_setup(dev);
1218 if (ppc_md.irq_bus_setup)
1219 ppc_md.irq_bus_setup(bus);
1222 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1224 struct pci_dev *dev = bus->self;
1226 if (dev && pci_probe_only &&
1227 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1228 /* This is a subordinate bridge */
1230 pci_read_bridge_bases(bus);
1231 pcibios_fixup_device_resources(dev, bus);
1236 if (!pci_probe_only)
1239 list_for_each_entry(dev, &bus->devices, bus_list)
1240 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1241 pcibios_fixup_device_resources(dev, bus);
1243 EXPORT_SYMBOL(pcibios_fixup_bus);
1246 * Reads the interrupt pin to determine if interrupt is use by card.
1247 * If the interrupt is used, then gets the interrupt line from the
1248 * openfirmware and sets it in the pci_dev and pci_config line.
1250 int pci_read_irq_line(struct pci_dev *pci_dev)
1255 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1258 memset(&oirq, 0xff, sizeof(oirq));
1260 /* Try to get a mapping from the device-tree */
1261 if (of_irq_map_pci(pci_dev, &oirq)) {
1264 /* If that fails, lets fallback to what is in the config
1265 * space and map that through the default controller. We
1266 * also set the type to level low since that's what PCI
1267 * interrupts are. If your platform does differently, then
1268 * either provide a proper interrupt tree or don't use this
1271 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1275 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1279 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1281 virq = irq_create_mapping(NULL, line);
1283 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1285 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1286 oirq.size, oirq.specifier[0], oirq.specifier[1],
1287 oirq.controller->full_name);
1289 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1292 if(virq == NO_IRQ) {
1293 DBG(" -> failed to map !\n");
1297 DBG(" -> mapped to linux irq %d\n", virq);
1299 pci_dev->irq = virq;
1300 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1304 EXPORT_SYMBOL(pci_read_irq_line);
1306 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1307 const struct resource *rsrc,
1308 u64 *start, u64 *end)
1310 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1311 unsigned long offset = 0;
1316 if (rsrc->flags & IORESOURCE_IO)
1317 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1320 *start = rsrc->start + offset;
1321 *end = rsrc->end + offset;
1324 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1329 struct pci_controller *hose, *tmp;
1330 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1331 if (hose->arch_data == node)
1333 node = node->parent;
1338 unsigned long pci_address_to_pio(phys_addr_t address)
1340 struct pci_controller *hose, *tmp;
1342 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1343 if (address >= hose->io_base_phys &&
1344 address < (hose->io_base_phys + hose->pci_io_size)) {
1345 unsigned long base =
1346 (unsigned long)hose->io_base_virt - pci_io_base;
1347 return base + (address - hose->io_base_phys);
1350 return (unsigned int)-1;
1352 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1355 #define IOBASE_BRIDGE_NUMBER 0
1356 #define IOBASE_MEMORY 1
1358 #define IOBASE_ISA_IO 3
1359 #define IOBASE_ISA_MEM 4
1361 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1362 unsigned long in_devfn)
1364 struct pci_controller* hose;
1365 struct list_head *ln;
1366 struct pci_bus *bus = NULL;
1367 struct device_node *hose_node;
1369 /* Argh ! Please forgive me for that hack, but that's the
1370 * simplest way to get existing XFree to not lockup on some
1371 * G5 machines... So when something asks for bus 0 io base
1372 * (bus 0 is HT root), we return the AGP one instead.
1374 if (machine_is_compatible("MacRISC4"))
1378 /* That syscall isn't quite compatible with PCI domains, but it's
1379 * used on pre-domains setup. We return the first match
1382 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1383 bus = pci_bus_b(ln);
1384 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1388 if (bus == NULL || bus->sysdata == NULL)
1391 hose_node = (struct device_node *)bus->sysdata;
1392 hose = PCI_DN(hose_node)->phb;
1395 case IOBASE_BRIDGE_NUMBER:
1396 return (long)hose->first_busno;
1398 return (long)hose->pci_mem_offset;
1400 return (long)hose->io_base_phys;
1402 return (long)isa_io_base;
1403 case IOBASE_ISA_MEM:
1411 int pcibus_to_node(struct pci_bus *bus)
1413 struct pci_controller *phb = pci_bus_to_host(bus);
1416 EXPORT_SYMBOL(pcibus_to_node);