2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
34 #include <asm/firmware.h>
38 #define DBG(fmt...) printk(fmt)
43 unsigned long pci_probe_only = 1;
44 int pci_assign_all_buses = 0;
46 static void fixup_resource(struct resource *res, struct pci_dev *dev);
47 static void do_bus_setup(struct pci_bus *bus);
49 /* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists nothing
53 * is mapped on the first 64K of IO space
55 unsigned long pci_io_base = ISA_IO_BASE;
56 EXPORT_SYMBOL(pci_io_base);
60 static struct dma_mapping_ops *pci_dma_ops;
62 /* XXX kill that some day ... */
63 int global_phb_number; /* Global phb counter */
65 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
67 pci_dma_ops = dma_ops;
70 struct dma_mapping_ops *get_pci_dma_ops(void)
74 EXPORT_SYMBOL(get_pci_dma_ops);
76 static void fixup_broken_pcnet32(struct pci_dev* dev)
78 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
79 dev->vendor = PCI_VENDOR_ID_AMD;
80 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
83 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
85 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
88 unsigned long offset = 0;
89 struct pci_controller *hose = pci_bus_to_host(dev->bus);
94 if (res->flags & IORESOURCE_IO)
95 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
97 if (res->flags & IORESOURCE_MEM)
98 offset = hose->pci_mem_offset;
100 region->start = res->start - offset;
101 region->end = res->end - offset;
104 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
105 struct pci_bus_region *region)
107 unsigned long offset = 0;
108 struct pci_controller *hose = pci_bus_to_host(dev->bus);
113 if (res->flags & IORESOURCE_IO)
114 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
116 if (res->flags & IORESOURCE_MEM)
117 offset = hose->pci_mem_offset;
119 res->start = region->start + offset;
120 res->end = region->end + offset;
123 #ifdef CONFIG_HOTPLUG
124 EXPORT_SYMBOL(pcibios_resource_to_bus);
125 EXPORT_SYMBOL(pcibios_bus_to_resource);
129 * We need to avoid collisions with `mirrored' VGA ports
130 * and other strange ISA hardware, so we always want the
131 * addresses to be allocated in the 0x000-0x0ff region
134 * Why? Because some silly external IO cards only decode
135 * the low 10 bits of the IO address. The 0x00-0xff region
136 * is reserved for motherboard devices that decode all 16
137 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
138 * but we want to try to avoid allocating at 0x2900-0x2bff
139 * which might have be mirrored at 0x0100-0x03ff..
141 void pcibios_align_resource(void *data, struct resource *res,
142 resource_size_t size, resource_size_t align)
144 struct pci_dev *dev = data;
145 struct pci_controller *hose = pci_bus_to_host(dev->bus);
146 resource_size_t start = res->start;
147 unsigned long alignto;
149 if (res->flags & IORESOURCE_IO) {
150 unsigned long offset = (unsigned long)hose->io_base_virt -
152 /* Make sure we start at our min on all hoses */
153 if (start - offset < PCIBIOS_MIN_IO)
154 start = PCIBIOS_MIN_IO + offset;
157 * Put everything into 0x00-0xff region modulo 0x400
160 start = (start + 0x3ff) & ~0x3ff;
162 } else if (res->flags & IORESOURCE_MEM) {
163 /* Make sure we start at our min on all hoses */
164 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
165 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
167 /* Align to multiple of size of minimum base. */
168 alignto = max(0x1000UL, align);
169 start = ALIGN(start, alignto);
175 static DEFINE_SPINLOCK(hose_spinlock);
178 * pci_controller(phb) initialized common variables.
180 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
182 memset(hose, 0, sizeof(struct pci_controller));
184 spin_lock(&hose_spinlock);
185 hose->global_number = global_phb_number++;
186 list_add_tail(&hose->list_node, &hose_list);
187 spin_unlock(&hose_spinlock);
190 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
192 struct pci_controller *phb;
195 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
197 phb = alloc_bootmem(sizeof (struct pci_controller));
200 pci_setup_pci_controller(phb);
201 phb->arch_data = dev;
202 phb->is_dynamic = mem_init_done;
204 int nid = of_node_to_nid(dev);
206 if (nid < 0 || !node_online(nid))
209 PHB_SET_NODE(phb, nid);
214 void pcibios_free_controller(struct pci_controller *phb)
216 spin_lock(&hose_spinlock);
217 list_del(&phb->list_node);
218 spin_unlock(&hose_spinlock);
224 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
227 struct pci_bus *child_bus;
229 list_for_each_entry(dev, &b->devices, bus_list) {
232 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
233 struct resource *r = &dev->resource[i];
235 if (r->parent || !r->start || !r->flags)
237 pci_claim_resource(dev, i);
241 list_for_each_entry(child_bus, &b->children, node)
242 pcibios_claim_one_bus(child_bus);
244 #ifdef CONFIG_HOTPLUG
245 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
248 static void __init pcibios_claim_of_setup(void)
252 if (firmware_has_feature(FW_FEATURE_ISERIES))
255 list_for_each_entry(b, &pci_root_buses, node)
256 pcibios_claim_one_bus(b);
259 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
264 prop = of_get_property(np, name, &len);
265 if (prop && len >= 4)
270 static unsigned int pci_parse_of_flags(u32 addr0)
272 unsigned int flags = 0;
274 if (addr0 & 0x02000000) {
275 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
276 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
277 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
278 if (addr0 & 0x40000000)
279 flags |= IORESOURCE_PREFETCH
280 | PCI_BASE_ADDRESS_MEM_PREFETCH;
281 } else if (addr0 & 0x01000000)
282 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
286 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
288 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
292 struct resource *res;
297 addrs = of_get_property(node, "assigned-addresses", &proplen);
300 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
301 for (; proplen >= 20; proplen -= 20, addrs += 5) {
302 flags = pci_parse_of_flags(addrs[0]);
305 base = GET_64BIT(addrs, 1);
306 size = GET_64BIT(addrs, 3);
310 DBG(" base: %llx, size: %llx, i: %x\n",
311 (unsigned long long)base, (unsigned long long)size, i);
313 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
314 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
315 } else if (i == dev->rom_base_reg) {
316 res = &dev->resource[PCI_ROM_RESOURCE];
317 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
319 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
323 res->end = base + size - 1;
325 res->name = pci_name(dev);
326 fixup_resource(res, dev);
330 struct pci_dev *of_create_pci_dev(struct device_node *node,
331 struct pci_bus *bus, int devfn)
336 dev = alloc_pci_dev();
339 type = of_get_property(node, "device_type", NULL);
343 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
347 dev->dev.parent = bus->bridge;
348 dev->dev.bus = &pci_bus_type;
350 dev->multifunction = 0; /* maybe a lie? */
352 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
353 dev->device = get_int_prop(node, "device-id", 0xffff);
354 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
355 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
357 dev->cfg_size = pci_cfg_space_size(dev);
359 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
360 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
361 dev->class = get_int_prop(node, "class-code", 0);
363 DBG(" class: 0x%x\n", dev->class);
365 dev->current_state = 4; /* unknown power state */
366 dev->error_state = pci_channel_io_normal;
368 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
369 /* a PCI-PCI bridge */
370 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
371 dev->rom_base_reg = PCI_ROM_ADDRESS1;
372 } else if (!strcmp(type, "cardbus")) {
373 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
375 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
376 dev->rom_base_reg = PCI_ROM_ADDRESS;
377 /* Maybe do a default OF mapping here */
381 pci_parse_of_addrs(node, dev);
383 DBG(" adding to system ...\n");
385 pci_device_add(dev, bus);
389 EXPORT_SYMBOL(of_create_pci_dev);
391 void __devinit of_scan_bus(struct device_node *node,
394 struct device_node *child = NULL;
399 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
401 while ((child = of_get_next_child(node, child)) != NULL) {
402 DBG(" * %s\n", child->full_name);
403 reg = of_get_property(child, "reg", ®len);
404 if (reg == NULL || reglen < 20)
406 devfn = (reg[0] >> 8) & 0xff;
408 /* create a new pci_dev for this device */
409 dev = of_create_pci_dev(child, bus, devfn);
412 DBG("dev header type: %x\n", dev->hdr_type);
414 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
415 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
416 of_scan_pci_bridge(child, dev);
421 EXPORT_SYMBOL(of_scan_bus);
423 void __devinit of_scan_pci_bridge(struct device_node *node,
427 const u32 *busrange, *ranges;
429 struct resource *res;
433 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
435 /* parse bus-range property */
436 busrange = of_get_property(node, "bus-range", &len);
437 if (busrange == NULL || len != 8) {
438 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
442 ranges = of_get_property(node, "ranges", &len);
443 if (ranges == NULL) {
444 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
449 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
451 printk(KERN_ERR "Failed to create pci bus for %s\n",
456 bus->primary = dev->bus->number;
457 bus->subordinate = busrange[1];
461 /* parse ranges property */
462 /* PCI #address-cells == 3 and #size-cells == 2 always */
463 res = &dev->resource[PCI_BRIDGE_RESOURCES];
464 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
466 bus->resource[i] = res;
470 for (; len >= 32; len -= 32, ranges += 8) {
471 flags = pci_parse_of_flags(ranges[0]);
472 size = GET_64BIT(ranges, 6);
473 if (flags == 0 || size == 0)
475 if (flags & IORESOURCE_IO) {
476 res = bus->resource[0];
478 printk(KERN_ERR "PCI: ignoring extra I/O range"
479 " for bridge %s\n", node->full_name);
483 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
484 printk(KERN_ERR "PCI: too many memory ranges"
485 " for bridge %s\n", node->full_name);
488 res = bus->resource[i];
491 res->start = GET_64BIT(ranges, 1);
492 res->end = res->start + size - 1;
494 fixup_resource(res, dev);
496 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
498 DBG(" bus name: %s\n", bus->name);
500 mode = PCI_PROBE_NORMAL;
501 if (ppc_md.pci_probe_mode)
502 mode = ppc_md.pci_probe_mode(bus);
503 DBG(" probe mode: %d\n", mode);
505 if (mode == PCI_PROBE_DEVTREE)
506 of_scan_bus(node, bus);
507 else if (mode == PCI_PROBE_NORMAL)
508 pci_scan_child_bus(bus);
510 EXPORT_SYMBOL(of_scan_pci_bridge);
512 void __devinit scan_phb(struct pci_controller *hose)
515 struct device_node *node = hose->arch_data;
517 struct resource *res;
519 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
521 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
523 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
524 hose->global_number);
527 bus->secondary = hose->first_busno;
530 if (!firmware_has_feature(FW_FEATURE_ISERIES))
531 pcibios_map_io_space(bus);
533 bus->resource[0] = res = &hose->io_resource;
534 if (res->flags && request_resource(&ioport_resource, res)) {
535 printk(KERN_ERR "Failed to request PCI IO region "
536 "on PCI domain %04x\n", hose->global_number);
537 DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
538 res->start, res->end);
541 for (i = 0; i < 3; ++i) {
542 res = &hose->mem_resources[i];
543 bus->resource[i+1] = res;
544 if (res->flags && request_resource(&iomem_resource, res))
545 printk(KERN_ERR "Failed to request PCI memory region "
546 "on PCI domain %04x\n", hose->global_number);
549 mode = PCI_PROBE_NORMAL;
551 if (node && ppc_md.pci_probe_mode)
552 mode = ppc_md.pci_probe_mode(bus);
553 DBG(" probe mode: %d\n", mode);
554 if (mode == PCI_PROBE_DEVTREE) {
555 bus->subordinate = hose->last_busno;
556 of_scan_bus(node, bus);
559 if (mode == PCI_PROBE_NORMAL)
560 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
563 static int __init pcibios_init(void)
565 struct pci_controller *hose, *tmp;
567 /* For now, override phys_mem_access_prot. If we need it,
568 * later, we may move that initialization to each ppc_md
570 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
572 if (firmware_has_feature(FW_FEATURE_ISERIES))
573 iSeries_pcibios_init();
575 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
577 /* Scan all of the recorded PCI controllers. */
578 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
580 pci_bus_add_devices(hose->bus);
583 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
585 pcibios_claim_of_setup();
587 /* FIXME: `else' will be removed when
588 pci_assign_unassigned_resources() is able to work
589 correctly with [partially] allocated PCI tree. */
590 pci_assign_unassigned_resources();
593 /* Call machine dependent final fixup */
594 if (ppc_md.pcibios_fixup)
595 ppc_md.pcibios_fixup();
597 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
602 subsys_initcall(pcibios_init);
604 int pcibios_enable_device(struct pci_dev *dev, int mask)
609 pci_read_config_word(dev, PCI_COMMAND, &cmd);
612 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
613 struct resource *res = &dev->resource[i];
615 /* Only set up the requested stuff */
616 if (!(mask & (1<<i)))
619 if (res->flags & IORESOURCE_IO)
620 cmd |= PCI_COMMAND_IO;
621 if (res->flags & IORESOURCE_MEM)
622 cmd |= PCI_COMMAND_MEMORY;
626 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
628 /* Enable the appropriate bits in the PCI command register. */
629 pci_write_config_word(dev, PCI_COMMAND, cmd);
634 /* Decide whether to display the domain number in /proc */
635 int pci_proc_domain(struct pci_bus *bus)
637 if (firmware_has_feature(FW_FEATURE_ISERIES))
640 struct pci_controller *hose = pci_bus_to_host(bus);
645 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
646 struct device_node *dev, int prim)
648 const unsigned int *ranges;
649 unsigned int pci_space;
653 struct resource *res;
654 int np, na = of_n_addr_cells(dev);
655 unsigned long pci_addr, cpu_phys_addr;
659 /* From "PCI Binding to 1275"
660 * The ranges property is laid out as an array of elements,
661 * each of which comprises:
662 * cells 0 - 2: a PCI address
663 * cells 3 or 3+4: a CPU physical address
664 * (size depending on dev->n_addr_cells)
665 * cells 4+5 or 5+6: the size of the range
667 ranges = of_get_property(dev, "ranges", &rlen);
670 hose->io_base_phys = 0;
671 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
673 pci_space = ranges[0];
674 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
675 cpu_phys_addr = of_translate_address(dev, &ranges[3]);
676 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
681 /* Now consume following elements while they are contiguous */
682 while (rlen >= np * sizeof(unsigned int)) {
683 unsigned long addr, phys;
685 if (ranges[0] != pci_space)
687 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
690 phys = (phys << 32) | ranges[4];
691 if (addr != pci_addr + size ||
692 phys != cpu_phys_addr + size)
695 size += ((unsigned long)ranges[na+3] << 32)
698 rlen -= np * sizeof(unsigned int);
701 switch ((pci_space >> 24) & 0x3) {
702 case 1: /* I/O space */
703 hose->io_base_phys = cpu_phys_addr - pci_addr;
704 /* handle from 0 to top of I/O window */
705 hose->pci_io_size = pci_addr + size;
707 res = &hose->io_resource;
708 res->flags = IORESOURCE_IO;
709 res->start = pci_addr;
710 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
711 res->start, res->start + size - 1);
713 case 2: /* memory space */
715 while (memno < 3 && hose->mem_resources[memno].flags)
719 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
721 res = &hose->mem_resources[memno];
722 res->flags = IORESOURCE_MEM;
723 res->start = cpu_phys_addr;
724 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
725 res->start, res->start + size - 1);
730 res->name = dev->full_name;
731 res->end = res->start + size - 1;
739 #ifdef CONFIG_HOTPLUG
741 int pcibios_unmap_io_space(struct pci_bus *bus)
743 struct pci_controller *hose;
745 WARN_ON(bus == NULL);
747 /* If this is not a PHB, we only flush the hash table over
748 * the area mapped by this bridge. We don't play with the PTE
749 * mappings since we might have to deal with sub-page alignemnts
750 * so flushing the hash table is the only sane way to make sure
751 * that no hash entries are covering that removed bridge area
752 * while still allowing other busses overlapping those pages
755 struct resource *res = bus->resource[0];
757 DBG("IO unmapping for PCI-PCI bridge %s\n",
758 pci_name(bus->self));
760 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
761 res->end - res->start + 1);
765 /* Get the host bridge */
766 hose = pci_bus_to_host(bus);
768 /* Check if we have IOs allocated */
769 if (hose->io_base_alloc == 0)
772 DBG("IO unmapping for PHB %s\n",
773 ((struct device_node *)hose->arch_data)->full_name);
774 DBG(" alloc=0x%p\n", hose->io_base_alloc);
776 /* This is a PHB, we fully unmap the IO area */
777 vunmap(hose->io_base_alloc);
781 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
783 #endif /* CONFIG_HOTPLUG */
785 int __devinit pcibios_map_io_space(struct pci_bus *bus)
787 struct vm_struct *area;
788 unsigned long phys_page;
789 unsigned long size_page;
790 unsigned long io_virt_offset;
791 struct pci_controller *hose;
793 WARN_ON(bus == NULL);
795 /* If this not a PHB, nothing to do, page tables still exist and
796 * thus HPTEs will be faulted in when needed
799 DBG("IO mapping for PCI-PCI bridge %s\n",
800 pci_name(bus->self));
801 DBG(" virt=0x%016lx...0x%016lx\n",
802 bus->resource[0]->start + _IO_BASE,
803 bus->resource[0]->end + _IO_BASE);
807 /* Get the host bridge */
808 hose = pci_bus_to_host(bus);
809 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
810 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
812 /* Make sure IO area address is clear */
813 hose->io_base_alloc = NULL;
815 /* If there's no IO to map on that bus, get away too */
816 if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
819 /* Let's allocate some IO space for that guy. We don't pass
820 * VM_IOREMAP because we don't care about alignment tricks that
821 * the core does in that case. Maybe we should due to stupid card
822 * with incomplete address decoding but I'd rather not deal with
823 * those outside of the reserved 64K legacy region.
825 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
828 hose->io_base_alloc = area->addr;
829 hose->io_base_virt = (void __iomem *)(area->addr +
830 hose->io_base_phys - phys_page);
832 DBG("IO mapping for PHB %s\n",
833 ((struct device_node *)hose->arch_data)->full_name);
834 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
835 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
836 DBG(" size=0x%016lx (alloc=0x%016lx)\n",
837 hose->pci_io_size, size_page);
839 /* Establish the mapping */
840 if (__ioremap_at(phys_page, area->addr, size_page,
841 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
844 /* Fixup hose IO resource */
845 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
846 hose->io_resource.start += io_virt_offset;
847 hose->io_resource.end += io_virt_offset;
849 DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
850 hose->io_resource.start, hose->io_resource.end);
854 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
856 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
858 struct pci_controller *hose = pci_bus_to_host(dev->bus);
859 unsigned long offset;
861 if (res->flags & IORESOURCE_IO) {
862 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
863 res->start += offset;
865 } else if (res->flags & IORESOURCE_MEM) {
866 res->start += hose->pci_mem_offset;
867 res->end += hose->pci_mem_offset;
871 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
874 /* Update device resources. */
877 DBG("%s: Fixup resources:\n", pci_name(dev));
878 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
879 struct resource *res = &dev->resource[i];
883 DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
884 i, res->flags, res->start, res->end);
886 fixup_resource(res, dev);
888 DBG(" > %08lx:0x%016lx...0x%016lx\n",
889 res->flags, res->start, res->end);
892 EXPORT_SYMBOL(pcibios_fixup_device_resources);
894 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
896 struct dev_archdata *sd = &dev->dev.archdata;
898 sd->of_node = pci_device_to_OF_node(dev);
900 DBG("PCI device %s OF node: %s\n", pci_name(dev),
901 sd->of_node ? sd->of_node->full_name : "<none>");
903 sd->dma_ops = pci_dma_ops;
905 sd->numa_node = pcibus_to_node(dev->bus);
909 if (ppc_md.pci_dma_dev_setup)
910 ppc_md.pci_dma_dev_setup(dev);
912 EXPORT_SYMBOL(pcibios_setup_new_device);
914 static void __devinit do_bus_setup(struct pci_bus *bus)
918 if (ppc_md.pci_dma_bus_setup)
919 ppc_md.pci_dma_bus_setup(bus);
921 list_for_each_entry(dev, &bus->devices, bus_list)
922 pcibios_setup_new_device(dev);
924 /* Read default IRQs and fixup if necessary */
925 list_for_each_entry(dev, &bus->devices, bus_list) {
926 pci_read_irq_line(dev);
927 if (ppc_md.pci_irq_fixup)
928 ppc_md.pci_irq_fixup(dev);
932 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
934 struct pci_dev *dev = bus->self;
935 struct device_node *np;
937 np = pci_bus_to_OF_node(bus);
939 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
941 if (dev && pci_probe_only &&
942 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
943 /* This is a subordinate bridge */
945 pci_read_bridge_bases(bus);
946 pcibios_fixup_device_resources(dev, bus);
954 list_for_each_entry(dev, &bus->devices, bus_list)
955 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
956 pcibios_fixup_device_resources(dev, bus);
958 EXPORT_SYMBOL(pcibios_fixup_bus);
960 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
965 struct pci_controller *hose, *tmp;
966 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
967 if (hose->arch_data == node)
974 unsigned long pci_address_to_pio(phys_addr_t address)
976 struct pci_controller *hose, *tmp;
978 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
979 if (address >= hose->io_base_phys &&
980 address < (hose->io_base_phys + hose->pci_io_size)) {
982 (unsigned long)hose->io_base_virt - _IO_BASE;
983 return base + (address - hose->io_base_phys);
986 return (unsigned int)-1;
988 EXPORT_SYMBOL_GPL(pci_address_to_pio);
991 #define IOBASE_BRIDGE_NUMBER 0
992 #define IOBASE_MEMORY 1
994 #define IOBASE_ISA_IO 3
995 #define IOBASE_ISA_MEM 4
997 long sys_pciconfig_iobase(long which, unsigned long in_bus,
998 unsigned long in_devfn)
1000 struct pci_controller* hose;
1001 struct list_head *ln;
1002 struct pci_bus *bus = NULL;
1003 struct device_node *hose_node;
1005 /* Argh ! Please forgive me for that hack, but that's the
1006 * simplest way to get existing XFree to not lockup on some
1007 * G5 machines... So when something asks for bus 0 io base
1008 * (bus 0 is HT root), we return the AGP one instead.
1010 if (machine_is_compatible("MacRISC4"))
1014 /* That syscall isn't quite compatible with PCI domains, but it's
1015 * used on pre-domains setup. We return the first match
1018 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1019 bus = pci_bus_b(ln);
1020 if (in_bus >= bus->number && in_bus <= bus->subordinate)
1024 if (bus == NULL || bus->sysdata == NULL)
1027 hose_node = (struct device_node *)bus->sysdata;
1028 hose = PCI_DN(hose_node)->phb;
1031 case IOBASE_BRIDGE_NUMBER:
1032 return (long)hose->first_busno;
1034 return (long)hose->pci_mem_offset;
1036 return (long)hose->io_base_phys;
1038 return (long)isa_io_base;
1039 case IOBASE_ISA_MEM:
1047 int pcibus_to_node(struct pci_bus *bus)
1049 struct pci_controller *phb = pci_bus_to_host(bus);
1052 EXPORT_SYMBOL(pcibus_to_node);