2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 /* Default PCI flags is 0 */
39 unsigned int ppc_pci_flags;
41 void pcibios_make_OF_bus_map(void);
43 static void pcibios_fixup_resources(struct pci_dev* dev);
44 static void fixup_broken_pcnet32(struct pci_dev* dev);
45 static int reparent_resources(struct resource *parent, struct resource *res);
46 static void fixup_cpc710_pci64(struct pci_dev* dev);
48 static u8* pci_to_OF_bus_map;
51 /* By default, we don't re-assign bus numbers. We do this only on
54 static int pci_assign_all_buses;
58 static int pci_bus_count;
61 fixup_hide_host_resource_fsl(struct pci_dev* dev)
63 int i, class = dev->class >> 8;
65 if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
66 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
67 (dev->bus->parent == NULL)) {
68 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
69 dev->resource[i].start = 0;
70 dev->resource[i].end = 0;
71 dev->resource[i].flags = 0;
75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
79 fixup_broken_pcnet32(struct pci_dev* dev)
81 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
82 dev->vendor = PCI_VENDOR_ID_AMD;
83 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
89 fixup_cpc710_pci64(struct pci_dev* dev)
91 /* Hide the PCI64 BARs from the kernel as their content doesn't
92 * fit well in the resource management
94 dev->resource[0].start = dev->resource[0].end = 0;
95 dev->resource[0].flags = 0;
96 dev->resource[1].start = dev->resource[1].end = 0;
97 dev->resource[1].flags = 0;
99 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
102 pcibios_fixup_resources(struct pci_dev *dev)
104 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
106 resource_size_t offset, mask;
109 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
112 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
113 struct resource *res = dev->resource + i;
116 if (res->end == 0xffffffff) {
117 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
118 pci_name(dev), i, (u64)res->start, (u64)res->end);
119 res->end -= res->start;
121 res->flags |= IORESOURCE_UNSET;
125 mask = (resource_size_t)-1;
126 if (res->flags & IORESOURCE_MEM) {
127 offset = hose->pci_mem_offset;
128 } else if (res->flags & IORESOURCE_IO) {
129 offset = (unsigned long) hose->io_base_virt
134 res->start = (res->start + offset) & mask;
135 res->end = (res->end + offset) & mask;
136 DBG("PCI: Fixup res %d (0x%lx) of dev %s: %llx -> %llx\n",
137 i, res->flags, pci_name(dev),
138 (u64)res->start - offset, (u64)res->start);
142 /* Call machine specific resource fixup */
143 if (ppc_md.pcibios_fixup_resources)
144 ppc_md.pcibios_fixup_resources(dev);
146 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
148 static int skip_isa_ioresource_align(struct pci_dev *dev)
150 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
151 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
157 * We need to avoid collisions with `mirrored' VGA ports
158 * and other strange ISA hardware, so we always want the
159 * addresses to be allocated in the 0x000-0x0ff region
162 * Why? Because some silly external IO cards only decode
163 * the low 10 bits of the IO address. The 0x00-0xff region
164 * is reserved for motherboard devices that decode all 16
165 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
166 * but we want to try to avoid allocating at 0x2900-0x2bff
167 * which might have be mirrored at 0x0100-0x03ff..
169 void pcibios_align_resource(void *data, struct resource *res,
170 resource_size_t size, resource_size_t align)
172 struct pci_dev *dev = data;
174 if (res->flags & IORESOURCE_IO) {
175 resource_size_t start = res->start;
177 if (skip_isa_ioresource_align(dev))
180 start = (start + 0x3ff) & ~0x3ff;
185 EXPORT_SYMBOL(pcibios_align_resource);
188 * Handle resources of PCI devices. If the world were perfect, we could
189 * just allocate all the resource regions and do nothing more. It isn't.
190 * On the other hand, we cannot just re-allocate all devices, as it would
191 * require us to know lots of host bridge internals. So we attempt to
192 * keep as much of the original configuration as possible, but tweak it
193 * when it's found to be wrong.
195 * Known BIOS problems we have to work around:
196 * - I/O or memory regions not configured
197 * - regions configured, but not enabled in the command register
198 * - bogus I/O addresses above 64K used
199 * - expansion ROMs left enabled (this may sound harmless, but given
200 * the fact the PCI specs explicitly allow address decoders to be
201 * shared between expansion ROMs and other resource regions, it's
202 * at least dangerous)
205 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
206 * This gives us fixed barriers on where we can allocate.
207 * (2) Allocate resources for all enabled devices. If there is
208 * a collision, just mark the resource as unallocated. Also
209 * disable expansion ROMs during this step.
210 * (3) Try to allocate resources for disabled devices. If the
211 * resources were assigned correctly, everything goes well,
212 * if they weren't, they won't disturb allocation of other
214 * (4) Assign new addresses to resources which were either
215 * not configured at all or misconfigured. If explicitly
216 * requested by the user, configure expansion ROM address
221 pcibios_allocate_bus_resources(struct list_head *bus_list)
225 struct resource *res, *pr;
227 /* Depth-First Search on bus tree */
228 list_for_each_entry(bus, bus_list, node) {
229 for (i = 0; i < 4; ++i) {
230 if ((res = bus->resource[i]) == NULL || !res->flags
231 || res->start > res->end)
233 if (bus->parent == NULL)
234 pr = (res->flags & IORESOURCE_IO)?
235 &ioport_resource : &iomem_resource;
237 /* Don't bother with non-root busses when
238 * re-assigning all resources.
240 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
242 pr = pci_find_parent_resource(bus->self, res);
244 /* this happens when the generic PCI
245 * code (wrongly) decides that this
246 * bridge is transparent -- paulus
252 DBG("PCI: dev %s (bus 0x%02x) bridge rsrc %d: %016llx..%016llx "
253 "(f:0x%08lx), parent %p\n",
254 bus->self ? pci_name(bus->self) : "PHB", bus->number, i,
255 (u64)res->start, (u64)res->end, res->flags, pr);
257 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
258 if (request_resource(pr, res) == 0)
261 * Must be a conflict with an existing entry.
262 * Move that entry (or entries) under the
263 * bridge resource and try again.
265 if (reparent_resources(pr, res) == 0)
269 "PCI: Cannot allocate resource region "
270 "%d of PCI bridge %d, will remap\n",
272 res->flags |= IORESOURCE_UNSET;
274 pcibios_allocate_bus_resources(&bus->children);
279 * Reparent resource children of pr that conflict with res
280 * under res, and make res replace those children.
283 reparent_resources(struct resource *parent, struct resource *res)
285 struct resource *p, **pp;
286 struct resource **firstpp = NULL;
288 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
289 if (p->end < res->start)
291 if (res->end < p->start)
293 if (p->start < res->start || p->end > res->end)
294 return -1; /* not completely contained */
299 return -1; /* didn't find any conflicting entries? */
300 res->parent = parent;
301 res->child = *firstpp;
305 for (p = res->child; p != NULL; p = p->sibling) {
307 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
308 p->name, (u64)p->start, (u64)p->end, res->name);
314 update_bridge_resource(struct pci_dev *dev, struct resource *res)
316 u8 io_base_lo, io_limit_lo;
317 u16 mem_base, mem_limit;
319 resource_size_t start, end, off;
320 struct pci_controller *hose = dev->sysdata;
323 printk("update_bridge_base: no hose?\n");
326 pci_read_config_word(dev, PCI_COMMAND, &cmd);
327 pci_write_config_word(dev, PCI_COMMAND,
328 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
329 if (res->flags & IORESOURCE_IO) {
330 off = (unsigned long) hose->io_base_virt - isa_io_base;
331 start = res->start - off;
332 end = res->end - off;
333 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
334 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
336 io_base_lo |= PCI_IO_RANGE_TYPE_32;
338 io_base_lo |= PCI_IO_RANGE_TYPE_16;
339 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
341 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
343 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
344 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
346 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
348 off = hose->pci_mem_offset;
349 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
350 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
351 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
352 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
354 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
355 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
356 off = hose->pci_mem_offset;
357 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
358 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
359 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
360 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
363 DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
364 pci_name(dev), res->flags);
366 pci_write_config_word(dev, PCI_COMMAND, cmd);
369 static inline void alloc_resource(struct pci_dev *dev, int idx)
371 struct resource *pr, *r = &dev->resource[idx];
373 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx (f=%lx)\n",
374 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
375 pr = pci_find_parent_resource(dev, r);
376 if (!pr || (pr->flags & IORESOURCE_UNSET) || request_resource(pr, r) < 0) {
377 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
378 " of device %s, will remap\n", idx, pci_name(dev));
380 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
381 pr, (u64)pr->start, (u64)pr->end, pr->flags);
382 /* We'll assign a new address later */
383 r->flags |= IORESOURCE_UNSET;
390 pcibios_allocate_resources(int pass)
392 struct pci_dev *dev = NULL;
397 for_each_pci_dev(dev) {
398 pci_read_config_word(dev, PCI_COMMAND, &command);
399 for (idx = 0; idx < 6; idx++) {
400 r = &dev->resource[idx];
401 if (r->parent) /* Already allocated */
403 if (!r->flags || (r->flags & IORESOURCE_UNSET))
404 continue; /* Not assigned at all */
405 if (r->flags & IORESOURCE_IO)
406 disabled = !(command & PCI_COMMAND_IO);
408 disabled = !(command & PCI_COMMAND_MEMORY);
409 if (pass == disabled)
410 alloc_resource(dev, idx);
414 r = &dev->resource[PCI_ROM_RESOURCE];
415 if (r->flags & IORESOURCE_ROM_ENABLE) {
416 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
418 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
419 r->flags &= ~IORESOURCE_ROM_ENABLE;
420 pci_read_config_dword(dev, dev->rom_base_reg, ®);
421 pci_write_config_dword(dev, dev->rom_base_reg,
422 reg & ~PCI_ROM_ADDRESS_ENABLE);
429 * Functions below are used on OpenFirmware machines.
432 make_one_node_map(struct device_node* node, u8 pci_bus)
434 const int *bus_range;
437 if (pci_bus >= pci_bus_count)
439 bus_range = of_get_property(node, "bus-range", &len);
440 if (bus_range == NULL || len < 2 * sizeof(int)) {
441 printk(KERN_WARNING "Can't get bus-range for %s, "
442 "assuming it starts at 0\n", node->full_name);
443 pci_to_OF_bus_map[pci_bus] = 0;
445 pci_to_OF_bus_map[pci_bus] = bus_range[0];
447 for (node=node->child; node != 0;node = node->sibling) {
449 const unsigned int *class_code, *reg;
451 class_code = of_get_property(node, "class-code", NULL);
452 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
453 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
455 reg = of_get_property(node, "reg", NULL);
458 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
459 if (!dev || !dev->subordinate) {
463 make_one_node_map(node, dev->subordinate->number);
469 pcibios_make_OF_bus_map(void)
472 struct pci_controller *hose, *tmp;
473 struct property *map_prop;
474 struct device_node *dn;
476 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
477 if (!pci_to_OF_bus_map) {
478 printk(KERN_ERR "Can't allocate OF bus map !\n");
482 /* We fill the bus map with invalid values, that helps
485 for (i=0; i<pci_bus_count; i++)
486 pci_to_OF_bus_map[i] = 0xff;
488 /* For each hose, we begin searching bridges */
489 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
490 struct device_node* node = hose->dn;
494 make_one_node_map(node, hose->first_busno);
496 dn = of_find_node_by_path("/");
497 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
499 BUG_ON(pci_bus_count > map_prop->length);
500 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
504 printk("PCI->OF bus map:\n");
505 for (i=0; i<pci_bus_count; i++) {
506 if (pci_to_OF_bus_map[i] == 0xff)
508 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
513 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
515 static struct device_node*
516 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
518 struct device_node* sub_node;
520 for (; node != 0;node = node->sibling) {
521 const unsigned int *class_code;
523 if (filter(node, data))
526 /* For PCI<->PCI bridges or CardBus bridges, we go down
527 * Note: some OFs create a parent node "multifunc-device" as
528 * a fake root for all functions of a multi-function device,
529 * we go down them as well.
531 class_code = of_get_property(node, "class-code", NULL);
532 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
533 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
534 strcmp(node->name, "multifunc-device"))
536 sub_node = scan_OF_pci_childs(node->child, filter, data);
543 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
546 struct device_node *np = NULL;
550 while ((np = of_get_next_child(parent, np)) != NULL) {
551 reg = of_get_property(np, "reg", &psize);
552 if (reg == NULL || psize < 4)
554 if (((reg[0] >> 8) & 0xff) == devfn)
561 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
563 struct device_node *parent, *np;
565 /* Are we a root bus ? */
566 if (bus->self == NULL || bus->parent == NULL) {
567 struct pci_controller *hose = pci_bus_to_host(bus);
570 return of_node_get(hose->dn);
573 /* not a root bus, we need to get our parent */
574 parent = scan_OF_for_pci_bus(bus->parent);
578 /* now iterate for children for a match */
579 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
586 * Scans the OF tree for a device node matching a PCI device
589 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
591 struct device_node *parent, *np;
596 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
597 parent = scan_OF_for_pci_bus(bus);
600 DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
601 np = scan_OF_for_pci_dev(parent, devfn);
603 DBG(" result is %s\n", np ? np->full_name : "<NULL>");
605 /* XXX most callers don't release the returned node
606 * mostly because ppc64 doesn't increase the refcount,
607 * we need to fix that.
611 EXPORT_SYMBOL(pci_busdev_to_OF_node);
614 pci_device_to_OF_node(struct pci_dev *dev)
616 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
618 EXPORT_SYMBOL(pci_device_to_OF_node);
621 find_OF_pci_device_filter(struct device_node* node, void* data)
623 return ((void *)node == data);
627 * Returns the PCI device matching a given OF node
630 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
632 const unsigned int *reg;
633 struct pci_controller* hose;
634 struct pci_dev* dev = NULL;
638 /* Make sure it's really a PCI device */
639 hose = pci_find_hose_for_OF_device(node);
640 if (!hose || !hose->dn)
642 if (!scan_OF_pci_childs(hose->dn->child,
643 find_OF_pci_device_filter, (void *)node))
645 reg = of_get_property(node, "reg", NULL);
648 *bus = (reg[0] >> 16) & 0xff;
649 *devfn = ((reg[0] >> 8) & 0xff);
651 /* Ok, here we need some tweak. If we have already renumbered
652 * all busses, we can't rely on the OF bus number any more.
653 * the pci_to_OF_bus_map is not enough as several PCI busses
654 * may match the same OF bus number.
656 if (!pci_to_OF_bus_map)
659 for_each_pci_dev(dev)
660 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
661 dev->devfn == *devfn) {
662 *bus = dev->bus->number;
669 EXPORT_SYMBOL(pci_device_from_OF_node);
671 /* We create the "pci-OF-bus-map" property now so it appears in the
675 pci_create_OF_bus_map(void)
677 struct property* of_prop;
678 struct device_node *dn;
680 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
683 dn = of_find_node_by_path("/");
685 memset(of_prop, -1, sizeof(struct property) + 256);
686 of_prop->name = "pci-OF-bus-map";
687 of_prop->length = 256;
688 of_prop->value = &of_prop[1];
689 prom_add_property(dn, of_prop);
694 #else /* CONFIG_PPC_OF */
695 void pcibios_make_OF_bus_map(void)
698 #endif /* CONFIG_PPC_OF */
703 struct pci_controller *hose, *tmp;
707 printk(KERN_INFO "PCI: Probing PCI hardware\n");
709 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS)
710 pci_assign_all_buses = 1;
712 /* Scan all of the recorded PCI controllers. */
713 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
714 if (pci_assign_all_buses)
715 hose->first_busno = next_busno;
716 hose->last_busno = 0xff;
717 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
720 pci_bus_add_devices(bus);
721 hose->last_busno = bus->subordinate;
722 if (pci_assign_all_buses || next_busno <= hose->last_busno)
723 next_busno = hose->last_busno + pcibios_assign_bus_offset;
725 pci_bus_count = next_busno;
727 /* OpenFirmware based machines need a map of OF bus
728 * numbers vs. kernel bus numbers since we may have to
731 if (pci_assign_all_buses && have_of)
732 pcibios_make_OF_bus_map();
734 /* Call machine dependent fixup */
735 if (ppc_md.pcibios_fixup)
736 ppc_md.pcibios_fixup();
738 /* Allocate and assign resources. If we re-assign everything, then
739 * we skip the allocate phase
741 pcibios_allocate_bus_resources(&pci_root_buses);
742 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
743 pcibios_allocate_resources(0);
744 pcibios_allocate_resources(1);
746 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
747 DBG("PCI: Assigning unassigned resouces...\n");
748 pci_assign_unassigned_resources();
751 /* Call machine dependent post-init code */
752 if (ppc_md.pcibios_after_init)
753 ppc_md.pcibios_after_init();
758 subsys_initcall(pcibios_init);
760 void pcibios_fixup_bus(struct pci_bus *bus)
762 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
763 unsigned long io_offset;
764 struct resource *res;
768 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
769 if (bus->parent == NULL) {
770 /* This is a host bridge - fill in its resources */
773 bus->resource[0] = res = &hose->io_resource;
776 printk(KERN_ERR "I/O resource not set for host"
777 " bridge %d\n", hose->global_number);
779 res->end = IO_SPACE_LIMIT;
780 res->flags = IORESOURCE_IO;
782 res->start = (res->start + io_offset) & 0xffffffffu;
783 res->end = (res->end + io_offset) & 0xffffffffu;
785 for (i = 0; i < 3; ++i) {
786 res = &hose->mem_resources[i];
790 printk(KERN_ERR "Memory resource not set for "
791 "host bridge %d\n", hose->global_number);
792 res->start = hose->pci_mem_offset;
794 res->flags = IORESOURCE_MEM;
796 bus->resource[i+1] = res;
799 /* This is a subordinate bridge */
800 pci_read_bridge_bases(bus);
802 for (i = 0; i < 4; ++i) {
803 if ((res = bus->resource[i]) == NULL)
805 if (!res->flags || bus->self->transparent)
807 if (io_offset && (res->flags & IORESOURCE_IO)) {
808 res->start = (res->start + io_offset) &
810 res->end = (res->end + io_offset) &
812 } else if (hose->pci_mem_offset
813 && (res->flags & IORESOURCE_MEM)) {
814 res->start += hose->pci_mem_offset;
815 res->end += hose->pci_mem_offset;
820 /* Platform specific bus fixups */
821 if (ppc_md.pcibios_fixup_bus)
822 ppc_md.pcibios_fixup_bus(bus);
824 /* Read default IRQs and fixup if necessary */
825 list_for_each_entry(dev, &bus->devices, bus_list) {
826 pci_read_irq_line(dev);
827 if (ppc_md.pci_irq_fixup)
828 ppc_md.pci_irq_fixup(dev);
832 /* the next one is stolen from the alpha port... */
834 pcibios_update_irq(struct pci_dev *dev, int irq)
836 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
837 /* XXX FIXME - update OF device tree node interrupt property */
840 int pcibios_enable_device(struct pci_dev *dev, int mask)
846 if (ppc_md.pcibios_enable_device_hook)
847 if (ppc_md.pcibios_enable_device_hook(dev, 0))
850 pci_read_config_word(dev, PCI_COMMAND, &cmd);
852 for (idx=0; idx<6; idx++) {
853 r = &dev->resource[idx];
854 if (r->flags & IORESOURCE_UNSET) {
855 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
858 if (r->flags & IORESOURCE_IO)
859 cmd |= PCI_COMMAND_IO;
860 if (r->flags & IORESOURCE_MEM)
861 cmd |= PCI_COMMAND_MEMORY;
863 if (cmd != old_cmd) {
864 printk("PCI: Enabling device %s (%04x -> %04x)\n",
865 pci_name(dev), old_cmd, cmd);
866 pci_write_config_word(dev, PCI_COMMAND, cmd);
871 static struct pci_controller*
872 pci_bus_to_hose(int bus)
874 struct pci_controller *hose, *tmp;
876 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
877 if (bus >= hose->first_busno && bus <= hose->last_busno)
882 /* Provide information on locations of various I/O regions in physical
883 * memory. Do this on a per-card basis so that we choose the right
885 * Note that the returned IO or memory base is a physical address
888 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
890 struct pci_controller* hose;
891 long result = -EOPNOTSUPP;
893 hose = pci_bus_to_hose(bus);
898 case IOBASE_BRIDGE_NUMBER:
899 return (long)hose->first_busno;
901 return (long)hose->pci_mem_offset;
903 return (long)hose->io_base_phys;
905 return (long)isa_io_base;
907 return (long)isa_mem_base;
913 unsigned long pci_address_to_pio(phys_addr_t address)
915 struct pci_controller *hose, *tmp;
917 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
918 unsigned int size = hose->io_resource.end -
919 hose->io_resource.start + 1;
920 if (address >= hose->io_base_phys &&
921 address < (hose->io_base_phys + size)) {
923 (unsigned long)hose->io_base_virt - _IO_BASE;
924 return base + (address - hose->io_base_phys);
927 return (unsigned int)-1;
929 EXPORT_SYMBOL(pci_address_to_pio);
932 * Null PCI config access functions, for the case when we can't
935 #define NULL_PCI_OP(rw, size, type) \
937 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
939 return PCIBIOS_DEVICE_NOT_FOUND; \
943 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
946 return PCIBIOS_DEVICE_NOT_FOUND;
950 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
953 return PCIBIOS_DEVICE_NOT_FOUND;
956 static struct pci_ops null_pci_ops =
958 .read = null_read_config,
959 .write = null_write_config,
963 * These functions are used early on before PCI scanning is done
964 * and all of the pci_dev and pci_bus structures have been created.
966 static struct pci_bus *
967 fake_pci_bus(struct pci_controller *hose, int busnr)
969 static struct pci_bus bus;
972 hose = pci_bus_to_hose(busnr);
974 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
978 bus.ops = hose? hose->ops: &null_pci_ops;
982 #define EARLY_PCI_OP(rw, size, type) \
983 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
984 int devfn, int offset, type value) \
986 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
987 devfn, offset, value); \
990 EARLY_PCI_OP(read, byte, u8 *)
991 EARLY_PCI_OP(read, word, u16 *)
992 EARLY_PCI_OP(read, dword, u32 *)
993 EARLY_PCI_OP(write, byte, u8)
994 EARLY_PCI_OP(write, word, u16)
995 EARLY_PCI_OP(write, dword, u32)
997 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
998 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1001 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);