2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 void pcibios_make_OF_bus_map(void);
40 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41 static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43 static void update_bridge_base(struct pci_bus *bus, int i);
44 static void pcibios_fixup_resources(struct pci_dev* dev);
45 static void fixup_broken_pcnet32(struct pci_dev* dev);
46 static int reparent_resources(struct resource *parent, struct resource *res);
47 static void fixup_cpc710_pci64(struct pci_dev* dev);
49 static u8* pci_to_OF_bus_map;
52 /* By default, we don't re-assign bus numbers. We do this only on
55 int pci_assign_all_buses;
59 static int pci_bus_count;
62 fixup_hide_host_resource_fsl(struct pci_dev* dev)
64 int i, class = dev->class >> 8;
66 if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
67 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
68 (dev->bus->parent == NULL)) {
69 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
70 dev->resource[i].start = 0;
71 dev->resource[i].end = 0;
72 dev->resource[i].flags = 0;
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
77 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
80 fixup_broken_pcnet32(struct pci_dev* dev)
82 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
83 dev->vendor = PCI_VENDOR_ID_AMD;
84 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
87 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
90 fixup_cpc710_pci64(struct pci_dev* dev)
92 /* Hide the PCI64 BARs from the kernel as their content doesn't
93 * fit well in the resource management
95 dev->resource[0].start = dev->resource[0].end = 0;
96 dev->resource[0].flags = 0;
97 dev->resource[1].start = dev->resource[1].end = 0;
98 dev->resource[1].flags = 0;
100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
103 pcibios_fixup_resources(struct pci_dev *dev)
105 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
107 resource_size_t offset, mask;
110 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
113 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
114 struct resource *res = dev->resource + i;
117 if (res->end == 0xffffffff) {
118 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
119 pci_name(dev), i, (u64)res->start, (u64)res->end);
120 res->end -= res->start;
122 res->flags |= IORESOURCE_UNSET;
126 mask = (resource_size_t)-1;
127 if (res->flags & IORESOURCE_MEM) {
128 offset = hose->pci_mem_offset;
129 } else if (res->flags & IORESOURCE_IO) {
130 offset = (unsigned long) hose->io_base_virt
135 res->start = (res->start + offset) & mask;
136 res->end = (res->end + offset) & mask;
137 DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
138 i, res->flags, pci_name(dev),
139 (u64)res->start - offset, (u64)res->start);
143 /* Call machine specific resource fixup */
144 if (ppc_md.pcibios_fixup_resources)
145 ppc_md.pcibios_fixup_resources(dev);
147 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
149 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
150 struct resource *res)
152 resource_size_t offset = 0, mask = (resource_size_t)-1;
153 struct pci_controller *hose = dev->sysdata;
155 if (hose && res->flags & IORESOURCE_IO) {
156 offset = (unsigned long)hose->io_base_virt - isa_io_base;
158 } else if (hose && res->flags & IORESOURCE_MEM)
159 offset = hose->pci_mem_offset;
160 region->start = (res->start - offset) & mask;
161 region->end = (res->end - offset) & mask;
163 EXPORT_SYMBOL(pcibios_resource_to_bus);
165 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
166 struct pci_bus_region *region)
168 resource_size_t offset = 0, mask = (resource_size_t)-1;
169 struct pci_controller *hose = dev->sysdata;
171 if (hose && res->flags & IORESOURCE_IO) {
172 offset = (unsigned long)hose->io_base_virt - isa_io_base;
174 } else if (hose && res->flags & IORESOURCE_MEM)
175 offset = hose->pci_mem_offset;
176 res->start = (region->start + offset) & mask;
177 res->end = (region->end + offset) & mask;
179 EXPORT_SYMBOL(pcibios_bus_to_resource);
182 * We need to avoid collisions with `mirrored' VGA ports
183 * and other strange ISA hardware, so we always want the
184 * addresses to be allocated in the 0x000-0x0ff region
187 * Why? Because some silly external IO cards only decode
188 * the low 10 bits of the IO address. The 0x00-0xff region
189 * is reserved for motherboard devices that decode all 16
190 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
191 * but we want to try to avoid allocating at 0x2900-0x2bff
192 * which might have be mirrored at 0x0100-0x03ff..
194 void pcibios_align_resource(void *data, struct resource *res,
195 resource_size_t size, resource_size_t align)
197 struct pci_dev *dev = data;
199 if (res->flags & IORESOURCE_IO) {
200 resource_size_t start = res->start;
203 start = (start + 0x3ff) & ~0x3ff;
208 EXPORT_SYMBOL(pcibios_align_resource);
211 * Handle resources of PCI devices. If the world were perfect, we could
212 * just allocate all the resource regions and do nothing more. It isn't.
213 * On the other hand, we cannot just re-allocate all devices, as it would
214 * require us to know lots of host bridge internals. So we attempt to
215 * keep as much of the original configuration as possible, but tweak it
216 * when it's found to be wrong.
218 * Known BIOS problems we have to work around:
219 * - I/O or memory regions not configured
220 * - regions configured, but not enabled in the command register
221 * - bogus I/O addresses above 64K used
222 * - expansion ROMs left enabled (this may sound harmless, but given
223 * the fact the PCI specs explicitly allow address decoders to be
224 * shared between expansion ROMs and other resource regions, it's
225 * at least dangerous)
228 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
229 * This gives us fixed barriers on where we can allocate.
230 * (2) Allocate resources for all enabled devices. If there is
231 * a collision, just mark the resource as unallocated. Also
232 * disable expansion ROMs during this step.
233 * (3) Try to allocate resources for disabled devices. If the
234 * resources were assigned correctly, everything goes well,
235 * if they weren't, they won't disturb allocation of other
237 * (4) Assign new addresses to resources which were either
238 * not configured at all or misconfigured. If explicitly
239 * requested by the user, configure expansion ROM address
244 pcibios_allocate_bus_resources(struct list_head *bus_list)
248 struct resource *res, *pr;
250 /* Depth-First Search on bus tree */
251 list_for_each_entry(bus, bus_list, node) {
252 for (i = 0; i < 4; ++i) {
253 if ((res = bus->resource[i]) == NULL || !res->flags
254 || res->start > res->end)
256 if (bus->parent == NULL)
257 pr = (res->flags & IORESOURCE_IO)?
258 &ioport_resource: &iomem_resource;
260 pr = pci_find_parent_resource(bus->self, res);
262 /* this happens when the generic PCI
263 * code (wrongly) decides that this
264 * bridge is transparent -- paulus
270 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
271 (u64)res->start, (u64)res->end, res->flags, pr);
273 if (request_resource(pr, res) == 0)
276 * Must be a conflict with an existing entry.
277 * Move that entry (or entries) under the
278 * bridge resource and try again.
280 if (reparent_resources(pr, res) == 0)
283 printk(KERN_ERR "PCI: Cannot allocate resource region "
284 "%d of PCI bridge %d\n", i, bus->number);
285 if (pci_relocate_bridge_resource(bus, i))
286 bus->resource[i] = NULL;
288 pcibios_allocate_bus_resources(&bus->children);
293 * Reparent resource children of pr that conflict with res
294 * under res, and make res replace those children.
297 reparent_resources(struct resource *parent, struct resource *res)
299 struct resource *p, **pp;
300 struct resource **firstpp = NULL;
302 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
303 if (p->end < res->start)
305 if (res->end < p->start)
307 if (p->start < res->start || p->end > res->end)
308 return -1; /* not completely contained */
313 return -1; /* didn't find any conflicting entries? */
314 res->parent = parent;
315 res->child = *firstpp;
319 for (p = res->child; p != NULL; p = p->sibling) {
321 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
322 p->name, (u64)p->start, (u64)p->end, res->name);
328 * A bridge has been allocated a range which is outside the range
329 * of its parent bridge, so it needs to be moved.
332 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
334 struct resource *res, *pr, *conflict;
335 resource_size_t try, size;
336 struct pci_bus *parent = bus->parent;
339 if (parent == NULL) {
340 /* shouldn't ever happen */
341 printk(KERN_ERR "PCI: can't move host bridge resource\n");
344 res = bus->resource[i];
348 for (j = 0; j < 4; j++) {
349 struct resource *r = parent->resource[j];
352 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
354 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
358 if (res->flags & IORESOURCE_PREFETCH)
363 size = res->end - res->start;
364 if (pr->start > pr->end || size > pr->end - pr->start)
368 res->start = try - size;
370 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
372 if (conflict->start <= pr->start + size)
374 try = conflict->start - 1;
376 if (request_resource(pr, res)) {
377 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
378 (u64)res->start, (u64)res->end);
379 return -1; /* "can't happen" */
381 update_bridge_base(bus, i);
382 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
383 bus->number, i, (unsigned long long)res->start,
384 (unsigned long long)res->end);
389 probe_resource(struct pci_bus *parent, struct resource *pr,
390 struct resource *res, struct resource **conflict)
397 for (r = pr->child; r != NULL; r = r->sibling) {
398 if (r->end >= res->start && res->end >= r->start) {
403 list_for_each_entry(bus, &parent->children, node) {
404 for (i = 0; i < 4; ++i) {
405 if ((r = bus->resource[i]) == NULL)
407 if (!r->flags || r->start > r->end || r == res)
409 if (pci_find_parent_resource(bus->self, r) != pr)
411 if (r->end >= res->start && res->end >= r->start) {
417 list_for_each_entry(dev, &parent->devices, bus_list) {
418 for (i = 0; i < 6; ++i) {
419 r = &dev->resource[i];
420 if (!r->flags || (r->flags & IORESOURCE_UNSET))
422 if (pci_find_parent_resource(dev, r) != pr)
424 if (r->end >= res->start && res->end >= r->start) {
434 update_bridge_resource(struct pci_dev *dev, struct resource *res)
436 u8 io_base_lo, io_limit_lo;
437 u16 mem_base, mem_limit;
439 resource_size_t start, end, off;
440 struct pci_controller *hose = dev->sysdata;
443 printk("update_bridge_base: no hose?\n");
446 pci_read_config_word(dev, PCI_COMMAND, &cmd);
447 pci_write_config_word(dev, PCI_COMMAND,
448 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
449 if (res->flags & IORESOURCE_IO) {
450 off = (unsigned long) hose->io_base_virt - isa_io_base;
451 start = res->start - off;
452 end = res->end - off;
453 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
454 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
456 io_base_lo |= PCI_IO_RANGE_TYPE_32;
458 io_base_lo |= PCI_IO_RANGE_TYPE_16;
459 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
461 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
463 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
464 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
466 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
468 off = hose->pci_mem_offset;
469 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
470 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
471 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
472 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
474 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
475 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
476 off = hose->pci_mem_offset;
477 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
478 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
479 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
480 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
483 DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
484 pci_name(dev), res->flags);
486 pci_write_config_word(dev, PCI_COMMAND, cmd);
490 update_bridge_base(struct pci_bus *bus, int i)
492 struct resource *res = bus->resource[i];
493 struct pci_dev *dev = bus->self;
494 update_bridge_resource(dev, res);
497 static inline void alloc_resource(struct pci_dev *dev, int idx)
499 struct resource *pr, *r = &dev->resource[idx];
501 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
502 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
503 pr = pci_find_parent_resource(dev, r);
504 if (!pr || request_resource(pr, r) < 0) {
505 printk(KERN_WARNING "PCI: Remapping resource region %d"
506 " of device %s\n", idx, pci_name(dev));
508 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
509 pr, (u64)pr->start, (u64)pr->end, pr->flags);
510 /* We'll assign a new address later */
511 r->flags |= IORESOURCE_UNSET;
518 pcibios_allocate_resources(int pass)
520 struct pci_dev *dev = NULL;
525 for_each_pci_dev(dev) {
526 pci_read_config_word(dev, PCI_COMMAND, &command);
527 for (idx = 0; idx < 6; idx++) {
528 r = &dev->resource[idx];
529 if (r->parent) /* Already allocated */
531 if (!r->flags || (r->flags & IORESOURCE_UNSET))
532 continue; /* Not assigned at all */
533 if (r->flags & IORESOURCE_IO)
534 disabled = !(command & PCI_COMMAND_IO);
536 disabled = !(command & PCI_COMMAND_MEMORY);
537 if (pass == disabled)
538 alloc_resource(dev, idx);
542 r = &dev->resource[PCI_ROM_RESOURCE];
543 if (r->flags & IORESOURCE_ROM_ENABLE) {
544 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
546 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
547 r->flags &= ~IORESOURCE_ROM_ENABLE;
548 pci_read_config_dword(dev, dev->rom_base_reg, ®);
549 pci_write_config_dword(dev, dev->rom_base_reg,
550 reg & ~PCI_ROM_ADDRESS_ENABLE);
556 pcibios_assign_resources(void)
558 struct pci_dev *dev = NULL;
562 for_each_pci_dev(dev) {
563 int class = dev->class >> 8;
565 /* Don't touch classless devices and host bridges */
566 if (!class || class == PCI_CLASS_BRIDGE_HOST)
569 for (idx = 0; idx < 6; idx++) {
570 r = &dev->resource[idx];
573 * We shall assign a new address to this resource,
574 * either because the BIOS (sic) forgot to do so
575 * or because we have decided the old address was
576 * unusable for some reason.
578 if ((r->flags & IORESOURCE_UNSET) && r->end &&
579 (!ppc_md.pcibios_enable_device_hook ||
580 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
583 r->flags &= ~IORESOURCE_UNSET;
584 rc = pci_assign_resource(dev, idx);
589 #if 0 /* don't assign ROMs */
590 r = &dev->resource[PCI_ROM_RESOURCE];
594 pci_assign_resource(dev, PCI_ROM_RESOURCE);
601 * Functions below are used on OpenFirmware machines.
604 make_one_node_map(struct device_node* node, u8 pci_bus)
606 const int *bus_range;
609 if (pci_bus >= pci_bus_count)
611 bus_range = of_get_property(node, "bus-range", &len);
612 if (bus_range == NULL || len < 2 * sizeof(int)) {
613 printk(KERN_WARNING "Can't get bus-range for %s, "
614 "assuming it starts at 0\n", node->full_name);
615 pci_to_OF_bus_map[pci_bus] = 0;
617 pci_to_OF_bus_map[pci_bus] = bus_range[0];
619 for (node=node->child; node != 0;node = node->sibling) {
621 const unsigned int *class_code, *reg;
623 class_code = of_get_property(node, "class-code", NULL);
624 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
625 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
627 reg = of_get_property(node, "reg", NULL);
630 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
631 if (!dev || !dev->subordinate) {
635 make_one_node_map(node, dev->subordinate->number);
641 pcibios_make_OF_bus_map(void)
644 struct pci_controller *hose, *tmp;
645 struct property *map_prop;
646 struct device_node *dn;
648 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
649 if (!pci_to_OF_bus_map) {
650 printk(KERN_ERR "Can't allocate OF bus map !\n");
654 /* We fill the bus map with invalid values, that helps
657 for (i=0; i<pci_bus_count; i++)
658 pci_to_OF_bus_map[i] = 0xff;
660 /* For each hose, we begin searching bridges */
661 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
662 struct device_node* node = hose->dn;
666 make_one_node_map(node, hose->first_busno);
668 dn = of_find_node_by_path("/");
669 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
671 BUG_ON(pci_bus_count > map_prop->length);
672 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
676 printk("PCI->OF bus map:\n");
677 for (i=0; i<pci_bus_count; i++) {
678 if (pci_to_OF_bus_map[i] == 0xff)
680 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
685 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
687 static struct device_node*
688 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
690 struct device_node* sub_node;
692 for (; node != 0;node = node->sibling) {
693 const unsigned int *class_code;
695 if (filter(node, data))
698 /* For PCI<->PCI bridges or CardBus bridges, we go down
699 * Note: some OFs create a parent node "multifunc-device" as
700 * a fake root for all functions of a multi-function device,
701 * we go down them as well.
703 class_code = of_get_property(node, "class-code", NULL);
704 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
705 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
706 strcmp(node->name, "multifunc-device"))
708 sub_node = scan_OF_pci_childs(node->child, filter, data);
715 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
718 struct device_node *np = NULL;
722 while ((np = of_get_next_child(parent, np)) != NULL) {
723 reg = of_get_property(np, "reg", &psize);
724 if (reg == NULL || psize < 4)
726 if (((reg[0] >> 8) & 0xff) == devfn)
733 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
735 struct device_node *parent, *np;
737 /* Are we a root bus ? */
738 if (bus->self == NULL || bus->parent == NULL) {
739 struct pci_controller *hose = pci_bus_to_host(bus);
742 return of_node_get(hose->dn);
745 /* not a root bus, we need to get our parent */
746 parent = scan_OF_for_pci_bus(bus->parent);
750 /* now iterate for children for a match */
751 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
758 * Scans the OF tree for a device node matching a PCI device
761 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
763 struct device_node *parent, *np;
768 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
769 parent = scan_OF_for_pci_bus(bus);
772 DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
773 np = scan_OF_for_pci_dev(parent, devfn);
775 DBG(" result is %s\n", np ? np->full_name : "<NULL>");
777 /* XXX most callers don't release the returned node
778 * mostly because ppc64 doesn't increase the refcount,
779 * we need to fix that.
783 EXPORT_SYMBOL(pci_busdev_to_OF_node);
786 pci_device_to_OF_node(struct pci_dev *dev)
788 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
790 EXPORT_SYMBOL(pci_device_to_OF_node);
793 find_OF_pci_device_filter(struct device_node* node, void* data)
795 return ((void *)node == data);
799 * Returns the PCI device matching a given OF node
802 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
804 const unsigned int *reg;
805 struct pci_controller* hose;
806 struct pci_dev* dev = NULL;
810 /* Make sure it's really a PCI device */
811 hose = pci_find_hose_for_OF_device(node);
812 if (!hose || !hose->dn)
814 if (!scan_OF_pci_childs(hose->dn->child,
815 find_OF_pci_device_filter, (void *)node))
817 reg = of_get_property(node, "reg", NULL);
820 *bus = (reg[0] >> 16) & 0xff;
821 *devfn = ((reg[0] >> 8) & 0xff);
823 /* Ok, here we need some tweak. If we have already renumbered
824 * all busses, we can't rely on the OF bus number any more.
825 * the pci_to_OF_bus_map is not enough as several PCI busses
826 * may match the same OF bus number.
828 if (!pci_to_OF_bus_map)
831 for_each_pci_dev(dev)
832 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
833 dev->devfn == *devfn) {
834 *bus = dev->bus->number;
841 EXPORT_SYMBOL(pci_device_from_OF_node);
843 /* We create the "pci-OF-bus-map" property now so it appears in the
847 pci_create_OF_bus_map(void)
849 struct property* of_prop;
850 struct device_node *dn;
852 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
855 dn = of_find_node_by_path("/");
857 memset(of_prop, -1, sizeof(struct property) + 256);
858 of_prop->name = "pci-OF-bus-map";
859 of_prop->length = 256;
860 of_prop->value = &of_prop[1];
861 prom_add_property(dn, of_prop);
866 #else /* CONFIG_PPC_OF */
867 void pcibios_make_OF_bus_map(void)
870 #endif /* CONFIG_PPC_OF */
872 #ifdef CONFIG_PPC_PMAC
874 * This set of routines checks for PCI<->PCI bridges that have closed
875 * IO resources and have child devices. It tries to re-open an IO
878 * This is a _temporary_ fix to workaround a problem with Apple's OF
879 * closing IO windows on P2P bridges when the OF drivers of cards
880 * below this bridge don't claim any IO range (typically ATI or
883 * A more complete fix would be to use drivers/pci/setup-bus.c, which
884 * involves a working pcibios_fixup_pbus_ranges(), some more care about
885 * ordering when creating the host bus resources, and maybe a few more
889 /* Initialize bridges with base/limit values we have collected */
891 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
893 struct pci_dev *bridge = bus->self;
894 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
899 if (bus->resource[0] == NULL)
901 res = *(bus->resource[0]);
903 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
904 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
905 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
906 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
908 /* Set up the top and bottom of the PCI I/O segment for this bus. */
909 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
911 l |= (res.start >> 8) & 0x00f0;
912 l |= res.end & 0xf000;
913 pci_write_config_dword(bridge, PCI_IO_BASE, l);
915 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
916 l = (res.start >> 16) | (res.end & 0xffff0000);
917 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
920 pci_read_config_word(bridge, PCI_COMMAND, &w);
922 pci_write_config_word(bridge, PCI_COMMAND, w);
924 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
926 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
927 w |= PCI_BRIDGE_CTL_VGA;
928 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
933 /* This function is pretty basic and actually quite broken for the
934 * general case, it's enough for us right now though. It's supposed
935 * to tell us if we need to open an IO range at all or not and what
939 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
945 #define push_end(res, mask) do { \
946 BUG_ON((mask+1) & mask); \
947 res->end = (res->end + mask) | mask; \
950 list_for_each_entry(dev, &bus->devices, bus_list) {
951 u16 class = dev->class >> 8;
953 if (class == PCI_CLASS_DISPLAY_VGA ||
954 class == PCI_CLASS_NOT_DEFINED_VGA)
956 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
957 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
958 if (class == PCI_CLASS_BRIDGE_CARDBUS)
959 push_end(res, 0xfff);
961 for (i=0; i<PCI_NUM_RESOURCES; i++) {
963 unsigned long r_size;
965 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
966 && i >= PCI_BRIDGE_RESOURCES)
968 r = &dev->resource[i];
969 r_size = r->end - r->start;
972 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
974 push_end(res, r_size);
982 /* Here we scan all P2P bridges of a given level that have a closed
983 * IO window. Note that the test for the presence of a VGA card should
984 * be improved to take into account already configured P2P bridges,
985 * currently, we don't see them and might end up configuring 2 bridges
986 * with VGA pass through enabled
989 do_fixup_p2p_level(struct pci_bus *bus)
995 for (parent_io=0; parent_io<4; parent_io++)
996 if (bus->resource[parent_io]
997 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1002 list_for_each_entry(b, &bus->children, node) {
1003 struct pci_dev *d = b->self;
1004 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1005 struct resource *res = b->resource[0];
1006 struct resource tmp_res;
1010 memset(&tmp_res, 0, sizeof(tmp_res));
1011 tmp_res.start = bus->resource[parent_io]->start;
1013 /* We don't let low addresses go through that closed P2P bridge, well,
1014 * that may not be necessary but I feel safer that way
1016 if (tmp_res.start == 0)
1017 tmp_res.start = 0x1000;
1019 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1020 res != bus->resource[parent_io] &&
1021 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1022 check_for_io_childs(b, &tmp_res, &found_vga)) {
1025 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1029 printk(KERN_WARNING "Skipping VGA, already active"
1030 " on bus segment\n");
1035 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1037 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1038 max = ((unsigned long) hose->io_base_virt
1039 - isa_io_base) + 0xffffffff;
1041 max = ((unsigned long) hose->io_base_virt
1042 - isa_io_base) + 0xffff;
1045 res->flags = IORESOURCE_IO;
1046 res->name = b->name;
1048 /* Find a resource in the parent where we can allocate */
1049 for (i = 0 ; i < 4; i++) {
1050 struct resource *r = bus->resource[i];
1053 if ((r->flags & IORESOURCE_IO) == 0)
1055 DBG("Trying to allocate from %016llx, size %016llx from parent"
1056 " res %d: %016llx -> %016llx\n",
1057 res->start, res->end, i, r->start, r->end);
1059 if (allocate_resource(r, res, res->end + 1, res->start, max,
1060 res->end + 1, NULL, NULL) < 0) {
1064 do_update_p2p_io_resource(b, found_vga);
1068 do_fixup_p2p_level(b);
1073 pcibios_fixup_p2p_bridges(void)
1077 list_for_each_entry(b, &pci_root_buses, node)
1078 do_fixup_p2p_level(b);
1081 #endif /* CONFIG_PPC_PMAC */
1086 struct pci_controller *hose, *tmp;
1087 struct pci_bus *bus;
1090 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1092 /* Scan all of the recorded PCI controllers. */
1093 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1094 if (pci_assign_all_buses)
1095 hose->first_busno = next_busno;
1096 hose->last_busno = 0xff;
1097 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
1100 pci_bus_add_devices(bus);
1101 hose->last_busno = bus->subordinate;
1102 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1103 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1105 pci_bus_count = next_busno;
1107 /* OpenFirmware based machines need a map of OF bus
1108 * numbers vs. kernel bus numbers since we may have to
1111 if (pci_assign_all_buses && have_of)
1112 pcibios_make_OF_bus_map();
1114 /* Call machine dependent fixup */
1115 if (ppc_md.pcibios_fixup)
1116 ppc_md.pcibios_fixup();
1118 /* Allocate and assign resources */
1119 pcibios_allocate_bus_resources(&pci_root_buses);
1120 pcibios_allocate_resources(0);
1121 pcibios_allocate_resources(1);
1122 #ifdef CONFIG_PPC_PMAC
1123 pcibios_fixup_p2p_bridges();
1124 #endif /* CONFIG_PPC_PMAC */
1125 pcibios_assign_resources();
1127 /* Call machine dependent post-init code */
1128 if (ppc_md.pcibios_after_init)
1129 ppc_md.pcibios_after_init();
1134 subsys_initcall(pcibios_init);
1136 void pcibios_fixup_bus(struct pci_bus *bus)
1138 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1139 unsigned long io_offset;
1140 struct resource *res;
1141 struct pci_dev *dev;
1144 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1145 if (bus->parent == NULL) {
1146 /* This is a host bridge - fill in its resources */
1149 bus->resource[0] = res = &hose->io_resource;
1152 printk(KERN_ERR "I/O resource not set for host"
1153 " bridge %d\n", hose->global_number);
1155 res->end = IO_SPACE_LIMIT;
1156 res->flags = IORESOURCE_IO;
1158 res->start = (res->start + io_offset) & 0xffffffffu;
1159 res->end = (res->end + io_offset) & 0xffffffffu;
1161 for (i = 0; i < 3; ++i) {
1162 res = &hose->mem_resources[i];
1166 printk(KERN_ERR "Memory resource not set for "
1167 "host bridge %d\n", hose->global_number);
1168 res->start = hose->pci_mem_offset;
1170 res->flags = IORESOURCE_MEM;
1172 bus->resource[i+1] = res;
1175 /* This is a subordinate bridge */
1176 pci_read_bridge_bases(bus);
1178 for (i = 0; i < 4; ++i) {
1179 if ((res = bus->resource[i]) == NULL)
1181 if (!res->flags || bus->self->transparent)
1183 if (io_offset && (res->flags & IORESOURCE_IO)) {
1184 res->start = (res->start + io_offset) &
1186 res->end = (res->end + io_offset) &
1188 } else if (hose->pci_mem_offset
1189 && (res->flags & IORESOURCE_MEM)) {
1190 res->start += hose->pci_mem_offset;
1191 res->end += hose->pci_mem_offset;
1196 /* Platform specific bus fixups */
1197 if (ppc_md.pcibios_fixup_bus)
1198 ppc_md.pcibios_fixup_bus(bus);
1200 /* Read default IRQs and fixup if necessary */
1201 list_for_each_entry(dev, &bus->devices, bus_list) {
1202 pci_read_irq_line(dev);
1203 if (ppc_md.pci_irq_fixup)
1204 ppc_md.pci_irq_fixup(dev);
1208 /* the next one is stolen from the alpha port... */
1210 pcibios_update_irq(struct pci_dev *dev, int irq)
1212 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1213 /* XXX FIXME - update OF device tree node interrupt property */
1216 int pcibios_enable_device(struct pci_dev *dev, int mask)
1222 if (ppc_md.pcibios_enable_device_hook)
1223 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1226 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1228 for (idx=0; idx<6; idx++) {
1229 r = &dev->resource[idx];
1230 if (r->flags & IORESOURCE_UNSET) {
1231 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1234 if (r->flags & IORESOURCE_IO)
1235 cmd |= PCI_COMMAND_IO;
1236 if (r->flags & IORESOURCE_MEM)
1237 cmd |= PCI_COMMAND_MEMORY;
1239 if (cmd != old_cmd) {
1240 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1241 pci_name(dev), old_cmd, cmd);
1242 pci_write_config_word(dev, PCI_COMMAND, cmd);
1247 static struct pci_controller*
1248 pci_bus_to_hose(int bus)
1250 struct pci_controller *hose, *tmp;
1252 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1253 if (bus >= hose->first_busno && bus <= hose->last_busno)
1258 /* Provide information on locations of various I/O regions in physical
1259 * memory. Do this on a per-card basis so that we choose the right
1261 * Note that the returned IO or memory base is a physical address
1264 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1266 struct pci_controller* hose;
1267 long result = -EOPNOTSUPP;
1269 /* Argh ! Please forgive me for that hack, but that's the
1270 * simplest way to get existing XFree to not lockup on some
1271 * G5 machines... So when something asks for bus 0 io base
1272 * (bus 0 is HT root), we return the AGP one instead.
1274 #ifdef CONFIG_PPC_PMAC
1275 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1278 #endif /* CONFIG_PPC_PMAC */
1280 hose = pci_bus_to_hose(bus);
1285 case IOBASE_BRIDGE_NUMBER:
1286 return (long)hose->first_busno;
1288 return (long)hose->pci_mem_offset;
1290 return (long)hose->io_base_phys;
1292 return (long)isa_io_base;
1293 case IOBASE_ISA_MEM:
1294 return (long)isa_mem_base;
1300 unsigned long pci_address_to_pio(phys_addr_t address)
1302 struct pci_controller *hose, *tmp;
1304 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1305 unsigned int size = hose->io_resource.end -
1306 hose->io_resource.start + 1;
1307 if (address >= hose->io_base_phys &&
1308 address < (hose->io_base_phys + size)) {
1309 unsigned long base =
1310 (unsigned long)hose->io_base_virt - _IO_BASE;
1311 return base + (address - hose->io_base_phys);
1314 return (unsigned int)-1;
1316 EXPORT_SYMBOL(pci_address_to_pio);
1319 * Null PCI config access functions, for the case when we can't
1322 #define NULL_PCI_OP(rw, size, type) \
1324 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1326 return PCIBIOS_DEVICE_NOT_FOUND; \
1330 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1333 return PCIBIOS_DEVICE_NOT_FOUND;
1337 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1340 return PCIBIOS_DEVICE_NOT_FOUND;
1343 static struct pci_ops null_pci_ops =
1345 .read = null_read_config,
1346 .write = null_write_config,
1350 * These functions are used early on before PCI scanning is done
1351 * and all of the pci_dev and pci_bus structures have been created.
1353 static struct pci_bus *
1354 fake_pci_bus(struct pci_controller *hose, int busnr)
1356 static struct pci_bus bus;
1359 hose = pci_bus_to_hose(busnr);
1361 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1365 bus.ops = hose? hose->ops: &null_pci_ops;
1369 #define EARLY_PCI_OP(rw, size, type) \
1370 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1371 int devfn, int offset, type value) \
1373 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1374 devfn, offset, value); \
1377 EARLY_PCI_OP(read, byte, u8 *)
1378 EARLY_PCI_OP(read, word, u16 *)
1379 EARLY_PCI_OP(read, dword, u32 *)
1380 EARLY_PCI_OP(write, byte, u8)
1381 EARLY_PCI_OP(write, word, u16)
1382 EARLY_PCI_OP(write, dword, u32)
1384 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1385 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1388 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);