2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long isa_mem_base = 0;
36 unsigned long pci_dram_offset = 0;
37 int pcibios_assign_bus_offset = 1;
39 void pcibios_make_OF_bus_map(void);
41 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
42 static int probe_resource(struct pci_bus *parent, struct resource *pr,
43 struct resource *res, struct resource **conflict);
44 static void update_bridge_base(struct pci_bus *bus, int i);
45 static void pcibios_fixup_resources(struct pci_dev* dev);
46 static void fixup_broken_pcnet32(struct pci_dev* dev);
47 static int reparent_resources(struct resource *parent, struct resource *res);
48 static void fixup_cpc710_pci64(struct pci_dev* dev);
50 static u8* pci_to_OF_bus_map;
53 /* By default, we don't re-assign bus numbers. We do this only on
56 int pci_assign_all_buses;
58 struct pci_controller* hose_head;
59 struct pci_controller** hose_tail = &hose_head;
61 static int pci_bus_count;
64 fixup_broken_pcnet32(struct pci_dev* dev)
66 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
67 dev->vendor = PCI_VENDOR_ID_AMD;
68 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
71 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
74 fixup_cpc710_pci64(struct pci_dev* dev)
76 /* Hide the PCI64 BARs from the kernel as their content doesn't
77 * fit well in the resource management
79 dev->resource[0].start = dev->resource[0].end = 0;
80 dev->resource[0].flags = 0;
81 dev->resource[1].start = dev->resource[1].end = 0;
82 dev->resource[1].flags = 0;
84 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
87 pcibios_fixup_resources(struct pci_dev *dev)
89 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
94 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
97 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
98 struct resource *res = dev->resource + i;
101 if (res->end == 0xffffffff) {
102 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
103 pci_name(dev), i, (u64)res->start, (u64)res->end);
104 res->end -= res->start;
106 res->flags |= IORESOURCE_UNSET;
110 if (res->flags & IORESOURCE_MEM) {
111 offset = hose->pci_mem_offset;
112 } else if (res->flags & IORESOURCE_IO) {
113 offset = (unsigned long) hose->io_base_virt
117 res->start += offset;
119 DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
120 i, res->flags, pci_name(dev),
121 (u64)res->start - offset, (u64)res->start);
125 /* Call machine specific resource fixup */
126 if (ppc_md.pcibios_fixup_resources)
127 ppc_md.pcibios_fixup_resources(dev);
129 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
131 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
132 struct resource *res)
134 unsigned long offset = 0;
135 struct pci_controller *hose = dev->sysdata;
137 if (hose && res->flags & IORESOURCE_IO)
138 offset = (unsigned long)hose->io_base_virt - isa_io_base;
139 else if (hose && res->flags & IORESOURCE_MEM)
140 offset = hose->pci_mem_offset;
141 region->start = res->start - offset;
142 region->end = res->end - offset;
144 EXPORT_SYMBOL(pcibios_resource_to_bus);
146 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
147 struct pci_bus_region *region)
149 unsigned long offset = 0;
150 struct pci_controller *hose = dev->sysdata;
152 if (hose && res->flags & IORESOURCE_IO)
153 offset = (unsigned long)hose->io_base_virt - isa_io_base;
154 else if (hose && res->flags & IORESOURCE_MEM)
155 offset = hose->pci_mem_offset;
156 res->start = region->start + offset;
157 res->end = region->end + offset;
159 EXPORT_SYMBOL(pcibios_bus_to_resource);
162 * We need to avoid collisions with `mirrored' VGA ports
163 * and other strange ISA hardware, so we always want the
164 * addresses to be allocated in the 0x000-0x0ff region
167 * Why? Because some silly external IO cards only decode
168 * the low 10 bits of the IO address. The 0x00-0xff region
169 * is reserved for motherboard devices that decode all 16
170 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
171 * but we want to try to avoid allocating at 0x2900-0x2bff
172 * which might have be mirrored at 0x0100-0x03ff..
174 void pcibios_align_resource(void *data, struct resource *res,
175 resource_size_t size, resource_size_t align)
177 struct pci_dev *dev = data;
179 if (res->flags & IORESOURCE_IO) {
180 resource_size_t start = res->start;
183 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
184 " (%lld bytes)\n", pci_name(dev),
185 dev->resource - res, (unsigned long long)size);
189 start = (start + 0x3ff) & ~0x3ff;
194 EXPORT_SYMBOL(pcibios_align_resource);
197 * Handle resources of PCI devices. If the world were perfect, we could
198 * just allocate all the resource regions and do nothing more. It isn't.
199 * On the other hand, we cannot just re-allocate all devices, as it would
200 * require us to know lots of host bridge internals. So we attempt to
201 * keep as much of the original configuration as possible, but tweak it
202 * when it's found to be wrong.
204 * Known BIOS problems we have to work around:
205 * - I/O or memory regions not configured
206 * - regions configured, but not enabled in the command register
207 * - bogus I/O addresses above 64K used
208 * - expansion ROMs left enabled (this may sound harmless, but given
209 * the fact the PCI specs explicitly allow address decoders to be
210 * shared between expansion ROMs and other resource regions, it's
211 * at least dangerous)
214 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
215 * This gives us fixed barriers on where we can allocate.
216 * (2) Allocate resources for all enabled devices. If there is
217 * a collision, just mark the resource as unallocated. Also
218 * disable expansion ROMs during this step.
219 * (3) Try to allocate resources for disabled devices. If the
220 * resources were assigned correctly, everything goes well,
221 * if they weren't, they won't disturb allocation of other
223 * (4) Assign new addresses to resources which were either
224 * not configured at all or misconfigured. If explicitly
225 * requested by the user, configure expansion ROM address
230 pcibios_allocate_bus_resources(struct list_head *bus_list)
234 struct resource *res, *pr;
236 /* Depth-First Search on bus tree */
237 list_for_each_entry(bus, bus_list, node) {
238 for (i = 0; i < 4; ++i) {
239 if ((res = bus->resource[i]) == NULL || !res->flags
240 || res->start > res->end)
242 if (bus->parent == NULL)
243 pr = (res->flags & IORESOURCE_IO)?
244 &ioport_resource: &iomem_resource;
246 pr = pci_find_parent_resource(bus->self, res);
248 /* this happens when the generic PCI
249 * code (wrongly) decides that this
250 * bridge is transparent -- paulus
256 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
257 (u64)res->start, (u64)res->end, res->flags, pr);
259 if (request_resource(pr, res) == 0)
262 * Must be a conflict with an existing entry.
263 * Move that entry (or entries) under the
264 * bridge resource and try again.
266 if (reparent_resources(pr, res) == 0)
269 printk(KERN_ERR "PCI: Cannot allocate resource region "
270 "%d of PCI bridge %d\n", i, bus->number);
271 if (pci_relocate_bridge_resource(bus, i))
272 bus->resource[i] = NULL;
274 pcibios_allocate_bus_resources(&bus->children);
279 * Reparent resource children of pr that conflict with res
280 * under res, and make res replace those children.
283 reparent_resources(struct resource *parent, struct resource *res)
285 struct resource *p, **pp;
286 struct resource **firstpp = NULL;
288 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
289 if (p->end < res->start)
291 if (res->end < p->start)
293 if (p->start < res->start || p->end > res->end)
294 return -1; /* not completely contained */
299 return -1; /* didn't find any conflicting entries? */
300 res->parent = parent;
301 res->child = *firstpp;
305 for (p = res->child; p != NULL; p = p->sibling) {
307 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
308 p->name, (u64)p->start, (u64)p->end, res->name);
314 * A bridge has been allocated a range which is outside the range
315 * of its parent bridge, so it needs to be moved.
318 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
320 struct resource *res, *pr, *conflict;
321 unsigned long try, size;
323 struct pci_bus *parent = bus->parent;
325 if (parent == NULL) {
326 /* shouldn't ever happen */
327 printk(KERN_ERR "PCI: can't move host bridge resource\n");
330 res = bus->resource[i];
334 for (j = 0; j < 4; j++) {
335 struct resource *r = parent->resource[j];
338 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
340 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
344 if (res->flags & IORESOURCE_PREFETCH)
349 size = res->end - res->start;
350 if (pr->start > pr->end || size > pr->end - pr->start)
354 res->start = try - size;
356 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
358 if (conflict->start <= pr->start + size)
360 try = conflict->start - 1;
362 if (request_resource(pr, res)) {
363 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
364 (u64)res->start, (u64)res->end);
365 return -1; /* "can't happen" */
367 update_bridge_base(bus, i);
368 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
369 bus->number, i, (unsigned long long)res->start,
370 (unsigned long long)res->end);
375 probe_resource(struct pci_bus *parent, struct resource *pr,
376 struct resource *res, struct resource **conflict)
383 for (r = pr->child; r != NULL; r = r->sibling) {
384 if (r->end >= res->start && res->end >= r->start) {
389 list_for_each_entry(bus, &parent->children, node) {
390 for (i = 0; i < 4; ++i) {
391 if ((r = bus->resource[i]) == NULL)
393 if (!r->flags || r->start > r->end || r == res)
395 if (pci_find_parent_resource(bus->self, r) != pr)
397 if (r->end >= res->start && res->end >= r->start) {
403 list_for_each_entry(dev, &parent->devices, bus_list) {
404 for (i = 0; i < 6; ++i) {
405 r = &dev->resource[i];
406 if (!r->flags || (r->flags & IORESOURCE_UNSET))
408 if (pci_find_parent_resource(dev, r) != pr)
410 if (r->end >= res->start && res->end >= r->start) {
420 update_bridge_base(struct pci_bus *bus, int i)
422 struct resource *res = bus->resource[i];
423 u8 io_base_lo, io_limit_lo;
424 u16 mem_base, mem_limit;
426 unsigned long start, end, off;
427 struct pci_dev *dev = bus->self;
428 struct pci_controller *hose = dev->sysdata;
431 printk("update_bridge_base: no hose?\n");
434 pci_read_config_word(dev, PCI_COMMAND, &cmd);
435 pci_write_config_word(dev, PCI_COMMAND,
436 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
437 if (res->flags & IORESOURCE_IO) {
438 off = (unsigned long) hose->io_base_virt - isa_io_base;
439 start = res->start - off;
440 end = res->end - off;
441 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
442 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
444 io_base_lo |= PCI_IO_RANGE_TYPE_32;
446 io_base_lo |= PCI_IO_RANGE_TYPE_16;
447 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
449 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
451 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
452 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
454 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
456 off = hose->pci_mem_offset;
457 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
458 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
459 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
460 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
462 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
463 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
464 off = hose->pci_mem_offset;
465 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
466 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
467 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
468 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
471 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
472 pci_name(dev), i, res->flags);
474 pci_write_config_word(dev, PCI_COMMAND, cmd);
477 static inline void alloc_resource(struct pci_dev *dev, int idx)
479 struct resource *pr, *r = &dev->resource[idx];
481 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
482 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
483 pr = pci_find_parent_resource(dev, r);
484 if (!pr || request_resource(pr, r) < 0) {
485 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
486 " of device %s\n", idx, pci_name(dev));
488 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
489 pr, (u64)pr->start, (u64)pr->end, pr->flags);
490 /* We'll assign a new address later */
491 r->flags |= IORESOURCE_UNSET;
498 pcibios_allocate_resources(int pass)
500 struct pci_dev *dev = NULL;
505 for_each_pci_dev(dev) {
506 pci_read_config_word(dev, PCI_COMMAND, &command);
507 for (idx = 0; idx < 6; idx++) {
508 r = &dev->resource[idx];
509 if (r->parent) /* Already allocated */
511 if (!r->flags || (r->flags & IORESOURCE_UNSET))
512 continue; /* Not assigned at all */
513 if (r->flags & IORESOURCE_IO)
514 disabled = !(command & PCI_COMMAND_IO);
516 disabled = !(command & PCI_COMMAND_MEMORY);
517 if (pass == disabled)
518 alloc_resource(dev, idx);
522 r = &dev->resource[PCI_ROM_RESOURCE];
523 if (r->flags & IORESOURCE_ROM_ENABLE) {
524 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
526 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
527 r->flags &= ~IORESOURCE_ROM_ENABLE;
528 pci_read_config_dword(dev, dev->rom_base_reg, ®);
529 pci_write_config_dword(dev, dev->rom_base_reg,
530 reg & ~PCI_ROM_ADDRESS_ENABLE);
536 pcibios_assign_resources(void)
538 struct pci_dev *dev = NULL;
542 for_each_pci_dev(dev) {
543 int class = dev->class >> 8;
545 /* Don't touch classless devices and host bridges */
546 if (!class || class == PCI_CLASS_BRIDGE_HOST)
549 for (idx = 0; idx < 6; idx++) {
550 r = &dev->resource[idx];
553 * We shall assign a new address to this resource,
554 * either because the BIOS (sic) forgot to do so
555 * or because we have decided the old address was
556 * unusable for some reason.
558 if ((r->flags & IORESOURCE_UNSET) && r->end &&
559 (!ppc_md.pcibios_enable_device_hook ||
560 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
561 r->flags &= ~IORESOURCE_UNSET;
562 pci_assign_resource(dev, idx);
566 #if 0 /* don't assign ROMs */
567 r = &dev->resource[PCI_ROM_RESOURCE];
571 pci_assign_resource(dev, PCI_ROM_RESOURCE);
578 pcibios_enable_resources(struct pci_dev *dev, int mask)
584 pci_read_config_word(dev, PCI_COMMAND, &cmd);
586 for (idx=0; idx<6; idx++) {
587 /* Only set up the requested stuff */
588 if (!(mask & (1<<idx)))
591 r = &dev->resource[idx];
592 if (r->flags & IORESOURCE_UNSET) {
593 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
596 if (r->flags & IORESOURCE_IO)
597 cmd |= PCI_COMMAND_IO;
598 if (r->flags & IORESOURCE_MEM)
599 cmd |= PCI_COMMAND_MEMORY;
601 if (dev->resource[PCI_ROM_RESOURCE].start)
602 cmd |= PCI_COMMAND_MEMORY;
603 if (cmd != old_cmd) {
604 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
605 pci_write_config_word(dev, PCI_COMMAND, cmd);
610 static int next_controller_index;
612 struct pci_controller * __init
613 pcibios_alloc_controller(struct device_node *dev)
615 struct pci_controller *hose;
617 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
618 memset(hose, 0, sizeof(struct pci_controller));
621 hose_tail = &hose->next;
623 hose->global_number = next_controller_index++;
624 hose->arch_data = dev;
631 * Functions below are used on OpenFirmware machines.
634 make_one_node_map(struct device_node* node, u8 pci_bus)
636 const int *bus_range;
639 if (pci_bus >= pci_bus_count)
641 bus_range = of_get_property(node, "bus-range", &len);
642 if (bus_range == NULL || len < 2 * sizeof(int)) {
643 printk(KERN_WARNING "Can't get bus-range for %s, "
644 "assuming it starts at 0\n", node->full_name);
645 pci_to_OF_bus_map[pci_bus] = 0;
647 pci_to_OF_bus_map[pci_bus] = bus_range[0];
649 for (node=node->child; node != 0;node = node->sibling) {
651 const unsigned int *class_code, *reg;
653 class_code = of_get_property(node, "class-code", NULL);
654 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
655 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
657 reg = of_get_property(node, "reg", NULL);
660 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
661 if (!dev || !dev->subordinate) {
665 make_one_node_map(node, dev->subordinate->number);
671 pcibios_make_OF_bus_map(void)
674 struct pci_controller* hose;
675 struct property *map_prop;
676 struct device_node *dn;
678 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
679 if (!pci_to_OF_bus_map) {
680 printk(KERN_ERR "Can't allocate OF bus map !\n");
684 /* We fill the bus map with invalid values, that helps
687 for (i=0; i<pci_bus_count; i++)
688 pci_to_OF_bus_map[i] = 0xff;
690 /* For each hose, we begin searching bridges */
691 for(hose=hose_head; hose; hose=hose->next) {
692 struct device_node* node;
693 node = (struct device_node *)hose->arch_data;
696 make_one_node_map(node, hose->first_busno);
698 dn = of_find_node_by_path("/");
699 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
701 BUG_ON(pci_bus_count > map_prop->length);
702 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
706 printk("PCI->OF bus map:\n");
707 for (i=0; i<pci_bus_count; i++) {
708 if (pci_to_OF_bus_map[i] == 0xff)
710 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
715 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
717 static struct device_node*
718 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
720 struct device_node* sub_node;
722 for (; node != 0;node = node->sibling) {
723 const unsigned int *class_code;
725 if (filter(node, data))
728 /* For PCI<->PCI bridges or CardBus bridges, we go down
729 * Note: some OFs create a parent node "multifunc-device" as
730 * a fake root for all functions of a multi-function device,
731 * we go down them as well.
733 class_code = of_get_property(node, "class-code", NULL);
734 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
735 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
736 strcmp(node->name, "multifunc-device"))
738 sub_node = scan_OF_pci_childs(node->child, filter, data);
745 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
748 struct device_node *np = NULL;
752 while ((np = of_get_next_child(parent, np)) != NULL) {
753 reg = of_get_property(np, "reg", &psize);
754 if (reg == NULL || psize < 4)
756 if (((reg[0] >> 8) & 0xff) == devfn)
763 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
765 struct device_node *parent, *np;
767 /* Are we a root bus ? */
768 if (bus->self == NULL || bus->parent == NULL) {
769 struct pci_controller *hose = pci_bus_to_host(bus);
772 return of_node_get(hose->arch_data);
775 /* not a root bus, we need to get our parent */
776 parent = scan_OF_for_pci_bus(bus->parent);
780 /* now iterate for children for a match */
781 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
788 * Scans the OF tree for a device node matching a PCI device
791 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
793 struct device_node *parent, *np;
798 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
799 parent = scan_OF_for_pci_bus(bus);
802 DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
803 np = scan_OF_for_pci_dev(parent, devfn);
805 DBG(" result is %s\n", np ? np->full_name : "<NULL>");
807 /* XXX most callers don't release the returned node
808 * mostly because ppc64 doesn't increase the refcount,
809 * we need to fix that.
813 EXPORT_SYMBOL(pci_busdev_to_OF_node);
816 pci_device_to_OF_node(struct pci_dev *dev)
818 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
820 EXPORT_SYMBOL(pci_device_to_OF_node);
822 /* This routine is meant to be used early during boot, when the
823 * PCI bus numbers have not yet been assigned, and you need to
824 * issue PCI config cycles to an OF device.
825 * It could also be used to "fix" RTAS config cycles if you want
826 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
829 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
834 struct pci_controller* hose;
835 for (hose=hose_head;hose;hose=hose->next)
836 if (hose->arch_data == node)
844 find_OF_pci_device_filter(struct device_node* node, void* data)
846 return ((void *)node == data);
850 * Returns the PCI device matching a given OF node
853 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
855 const unsigned int *reg;
856 struct pci_controller* hose;
857 struct pci_dev* dev = NULL;
861 /* Make sure it's really a PCI device */
862 hose = pci_find_hose_for_OF_device(node);
863 if (!hose || !hose->arch_data)
865 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
866 find_OF_pci_device_filter, (void *)node))
868 reg = of_get_property(node, "reg", NULL);
871 *bus = (reg[0] >> 16) & 0xff;
872 *devfn = ((reg[0] >> 8) & 0xff);
874 /* Ok, here we need some tweak. If we have already renumbered
875 * all busses, we can't rely on the OF bus number any more.
876 * the pci_to_OF_bus_map is not enough as several PCI busses
877 * may match the same OF bus number.
879 if (!pci_to_OF_bus_map)
882 for_each_pci_dev(dev)
883 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
884 dev->devfn == *devfn) {
885 *bus = dev->bus->number;
892 EXPORT_SYMBOL(pci_device_from_OF_node);
895 pci_process_bridge_OF_ranges(struct pci_controller *hose,
896 struct device_node *dev, int primary)
898 static unsigned int static_lc_ranges[256] __initdata;
899 const unsigned int *dt_ranges;
900 unsigned int *lc_ranges, *ranges, *prev, size;
901 int rlen = 0, orig_rlen;
903 struct resource *res;
904 int np, na = of_n_addr_cells(dev);
907 /* First we try to merge ranges to fix a problem with some pmacs
908 * that can have more than 3 ranges, fortunately using contiguous
911 dt_ranges = of_get_property(dev, "ranges", &rlen);
914 /* Sanity check, though hopefully that never happens */
915 if (rlen > sizeof(static_lc_ranges)) {
916 printk(KERN_WARNING "OF ranges property too large !\n");
917 rlen = sizeof(static_lc_ranges);
919 lc_ranges = static_lc_ranges;
920 memcpy(lc_ranges, dt_ranges, rlen);
923 /* Let's work on a copy of the "ranges" property instead of damaging
924 * the device-tree image in memory
928 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
930 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
931 (prev[2] + prev[na+4]) == ranges[2] &&
932 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
933 prev[na+4] += ranges[na+4];
944 * The ranges property is laid out as an array of elements,
945 * each of which comprises:
946 * cells 0 - 2: a PCI address
947 * cells 3 or 3+4: a CPU physical address
948 * (size depending on dev->n_addr_cells)
949 * cells 4+5 or 5+6: the size of the range
953 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
956 switch ((ranges[0] >> 24) & 0x3) {
957 case 1: /* I/O space */
960 hose->io_base_phys = ranges[na+2];
961 /* limit I/O space to 16MB */
962 if (size > 0x01000000)
964 hose->io_base_virt = ioremap(ranges[na+2], size);
966 isa_io_base = (unsigned long) hose->io_base_virt;
967 res = &hose->io_resource;
968 res->flags = IORESOURCE_IO;
969 res->start = ranges[2];
970 DBG("PCI: IO 0x%llx -> 0x%llx\n",
971 (u64)res->start, (u64)res->start + size - 1);
973 case 2: /* memory space */
975 if (ranges[1] == 0 && ranges[2] == 0
976 && ranges[na+4] <= (16 << 20)) {
977 /* 1st 16MB, i.e. ISA memory area */
979 isa_mem_base = ranges[na+2];
982 while (memno < 3 && hose->mem_resources[memno].flags)
985 hose->pci_mem_offset = ranges[na+2] - ranges[2];
987 res = &hose->mem_resources[memno];
988 res->flags = IORESOURCE_MEM;
989 if(ranges[0] & 0x40000000)
990 res->flags |= IORESOURCE_PREFETCH;
991 res->start = ranges[na+2];
992 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
993 (u64)res->start, (u64)res->start + size - 1);
998 res->name = dev->full_name;
999 res->end = res->start + size - 1;
1001 res->sibling = NULL;
1008 /* We create the "pci-OF-bus-map" property now so it appears in the
1012 pci_create_OF_bus_map(void)
1014 struct property* of_prop;
1015 struct device_node *dn;
1017 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1020 dn = of_find_node_by_path("/");
1022 memset(of_prop, -1, sizeof(struct property) + 256);
1023 of_prop->name = "pci-OF-bus-map";
1024 of_prop->length = 256;
1025 of_prop->value = &of_prop[1];
1026 prom_add_property(dn, of_prop);
1031 #else /* CONFIG_PPC_OF */
1032 void pcibios_make_OF_bus_map(void)
1035 #endif /* CONFIG_PPC_OF */
1037 #ifdef CONFIG_PPC_PMAC
1039 * This set of routines checks for PCI<->PCI bridges that have closed
1040 * IO resources and have child devices. It tries to re-open an IO
1043 * This is a _temporary_ fix to workaround a problem with Apple's OF
1044 * closing IO windows on P2P bridges when the OF drivers of cards
1045 * below this bridge don't claim any IO range (typically ATI or
1048 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1049 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1050 * ordering when creating the host bus resources, and maybe a few more
1054 /* Initialize bridges with base/limit values we have collected */
1056 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1058 struct pci_dev *bridge = bus->self;
1059 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1062 struct resource res;
1064 if (bus->resource[0] == NULL)
1066 res = *(bus->resource[0]);
1068 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1069 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1070 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1071 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
1073 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1074 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1076 l |= (res.start >> 8) & 0x00f0;
1077 l |= res.end & 0xf000;
1078 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1080 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1081 l = (res.start >> 16) | (res.end & 0xffff0000);
1082 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1085 pci_read_config_word(bridge, PCI_COMMAND, &w);
1086 w |= PCI_COMMAND_IO;
1087 pci_write_config_word(bridge, PCI_COMMAND, w);
1089 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1091 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1092 w |= PCI_BRIDGE_CTL_VGA;
1093 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1098 /* This function is pretty basic and actually quite broken for the
1099 * general case, it's enough for us right now though. It's supposed
1100 * to tell us if we need to open an IO range at all or not and what
1104 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1106 struct pci_dev *dev;
1110 #define push_end(res, mask) do { \
1111 BUG_ON((mask+1) & mask); \
1112 res->end = (res->end + mask) | mask; \
1115 list_for_each_entry(dev, &bus->devices, bus_list) {
1116 u16 class = dev->class >> 8;
1118 if (class == PCI_CLASS_DISPLAY_VGA ||
1119 class == PCI_CLASS_NOT_DEFINED_VGA)
1121 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1122 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1123 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1124 push_end(res, 0xfff);
1126 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1128 unsigned long r_size;
1130 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1131 && i >= PCI_BRIDGE_RESOURCES)
1133 r = &dev->resource[i];
1134 r_size = r->end - r->start;
1137 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1139 push_end(res, r_size);
1147 /* Here we scan all P2P bridges of a given level that have a closed
1148 * IO window. Note that the test for the presence of a VGA card should
1149 * be improved to take into account already configured P2P bridges,
1150 * currently, we don't see them and might end up configuring 2 bridges
1151 * with VGA pass through enabled
1154 do_fixup_p2p_level(struct pci_bus *bus)
1160 for (parent_io=0; parent_io<4; parent_io++)
1161 if (bus->resource[parent_io]
1162 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1167 list_for_each_entry(b, &bus->children, node) {
1168 struct pci_dev *d = b->self;
1169 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1170 struct resource *res = b->resource[0];
1171 struct resource tmp_res;
1175 memset(&tmp_res, 0, sizeof(tmp_res));
1176 tmp_res.start = bus->resource[parent_io]->start;
1178 /* We don't let low addresses go through that closed P2P bridge, well,
1179 * that may not be necessary but I feel safer that way
1181 if (tmp_res.start == 0)
1182 tmp_res.start = 0x1000;
1184 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1185 res != bus->resource[parent_io] &&
1186 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1187 check_for_io_childs(b, &tmp_res, &found_vga)) {
1190 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1194 printk(KERN_WARNING "Skipping VGA, already active"
1195 " on bus segment\n");
1200 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1202 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1203 max = ((unsigned long) hose->io_base_virt
1204 - isa_io_base) + 0xffffffff;
1206 max = ((unsigned long) hose->io_base_virt
1207 - isa_io_base) + 0xffff;
1210 res->flags = IORESOURCE_IO;
1211 res->name = b->name;
1213 /* Find a resource in the parent where we can allocate */
1214 for (i = 0 ; i < 4; i++) {
1215 struct resource *r = bus->resource[i];
1218 if ((r->flags & IORESOURCE_IO) == 0)
1220 DBG("Trying to allocate from %016llx, size %016llx from parent"
1221 " res %d: %016llx -> %016llx\n",
1222 res->start, res->end, i, r->start, r->end);
1224 if (allocate_resource(r, res, res->end + 1, res->start, max,
1225 res->end + 1, NULL, NULL) < 0) {
1229 do_update_p2p_io_resource(b, found_vga);
1233 do_fixup_p2p_level(b);
1238 pcibios_fixup_p2p_bridges(void)
1242 list_for_each_entry(b, &pci_root_buses, node)
1243 do_fixup_p2p_level(b);
1246 #endif /* CONFIG_PPC_PMAC */
1251 struct pci_controller *hose;
1252 struct pci_bus *bus;
1255 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1257 /* Scan all of the recorded PCI controllers. */
1258 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1259 if (pci_assign_all_buses)
1260 hose->first_busno = next_busno;
1261 hose->last_busno = 0xff;
1262 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
1265 pci_bus_add_devices(bus);
1266 hose->last_busno = bus->subordinate;
1267 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1268 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1270 pci_bus_count = next_busno;
1272 /* OpenFirmware based machines need a map of OF bus
1273 * numbers vs. kernel bus numbers since we may have to
1276 if (pci_assign_all_buses && have_of)
1277 pcibios_make_OF_bus_map();
1279 /* Call machine dependent fixup */
1280 if (ppc_md.pcibios_fixup)
1281 ppc_md.pcibios_fixup();
1283 /* Allocate and assign resources */
1284 pcibios_allocate_bus_resources(&pci_root_buses);
1285 pcibios_allocate_resources(0);
1286 pcibios_allocate_resources(1);
1287 #ifdef CONFIG_PPC_PMAC
1288 pcibios_fixup_p2p_bridges();
1289 #endif /* CONFIG_PPC_PMAC */
1290 pcibios_assign_resources();
1292 /* Call machine dependent post-init code */
1293 if (ppc_md.pcibios_after_init)
1294 ppc_md.pcibios_after_init();
1299 subsys_initcall(pcibios_init);
1301 void __init pcibios_fixup_bus(struct pci_bus *bus)
1303 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1304 unsigned long io_offset;
1305 struct resource *res;
1306 struct pci_dev *dev;
1309 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1310 if (bus->parent == NULL) {
1311 /* This is a host bridge - fill in its resources */
1314 bus->resource[0] = res = &hose->io_resource;
1317 printk(KERN_ERR "I/O resource not set for host"
1318 " bridge %d\n", hose->global_number);
1320 res->end = IO_SPACE_LIMIT;
1321 res->flags = IORESOURCE_IO;
1323 res->start += io_offset;
1324 res->end += io_offset;
1326 for (i = 0; i < 3; ++i) {
1327 res = &hose->mem_resources[i];
1331 printk(KERN_ERR "Memory resource not set for "
1332 "host bridge %d\n", hose->global_number);
1333 res->start = hose->pci_mem_offset;
1335 res->flags = IORESOURCE_MEM;
1337 bus->resource[i+1] = res;
1340 /* This is a subordinate bridge */
1341 pci_read_bridge_bases(bus);
1343 for (i = 0; i < 4; ++i) {
1344 if ((res = bus->resource[i]) == NULL)
1346 if (!res->flags || bus->self->transparent)
1348 if (io_offset && (res->flags & IORESOURCE_IO)) {
1349 res->start += io_offset;
1350 res->end += io_offset;
1351 } else if (hose->pci_mem_offset
1352 && (res->flags & IORESOURCE_MEM)) {
1353 res->start += hose->pci_mem_offset;
1354 res->end += hose->pci_mem_offset;
1359 /* Platform specific bus fixups */
1360 if (ppc_md.pcibios_fixup_bus)
1361 ppc_md.pcibios_fixup_bus(bus);
1363 /* Read default IRQs and fixup if necessary */
1364 list_for_each_entry(dev, &bus->devices, bus_list) {
1365 pci_read_irq_line(dev);
1366 if (ppc_md.pci_irq_fixup)
1367 ppc_md.pci_irq_fixup(dev);
1371 /* the next one is stolen from the alpha port... */
1373 pcibios_update_irq(struct pci_dev *dev, int irq)
1375 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1376 /* XXX FIXME - update OF device tree node interrupt property */
1379 int pcibios_enable_device(struct pci_dev *dev, int mask)
1385 if (ppc_md.pcibios_enable_device_hook)
1386 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1389 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1391 for (idx=0; idx<6; idx++) {
1392 r = &dev->resource[idx];
1393 if (r->flags & IORESOURCE_UNSET) {
1394 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1397 if (r->flags & IORESOURCE_IO)
1398 cmd |= PCI_COMMAND_IO;
1399 if (r->flags & IORESOURCE_MEM)
1400 cmd |= PCI_COMMAND_MEMORY;
1402 if (cmd != old_cmd) {
1403 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1404 pci_name(dev), old_cmd, cmd);
1405 pci_write_config_word(dev, PCI_COMMAND, cmd);
1410 static struct pci_controller*
1411 pci_bus_to_hose(int bus)
1413 struct pci_controller* hose = hose_head;
1415 for (; hose; hose = hose->next)
1416 if (bus >= hose->first_busno && bus <= hose->last_busno)
1421 /* Provide information on locations of various I/O regions in physical
1422 * memory. Do this on a per-card basis so that we choose the right
1424 * Note that the returned IO or memory base is a physical address
1427 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1429 struct pci_controller* hose;
1430 long result = -EOPNOTSUPP;
1432 /* Argh ! Please forgive me for that hack, but that's the
1433 * simplest way to get existing XFree to not lockup on some
1434 * G5 machines... So when something asks for bus 0 io base
1435 * (bus 0 is HT root), we return the AGP one instead.
1437 #ifdef CONFIG_PPC_PMAC
1438 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1441 #endif /* CONFIG_PPC_PMAC */
1443 hose = pci_bus_to_hose(bus);
1448 case IOBASE_BRIDGE_NUMBER:
1449 return (long)hose->first_busno;
1451 return (long)hose->pci_mem_offset;
1453 return (long)hose->io_base_phys;
1455 return (long)isa_io_base;
1456 case IOBASE_ISA_MEM:
1457 return (long)isa_mem_base;
1463 unsigned long pci_address_to_pio(phys_addr_t address)
1465 struct pci_controller* hose = hose_head;
1467 for (; hose; hose = hose->next) {
1468 unsigned int size = hose->io_resource.end -
1469 hose->io_resource.start + 1;
1470 if (address >= hose->io_base_phys &&
1471 address < (hose->io_base_phys + size)) {
1472 unsigned long base =
1473 (unsigned long)hose->io_base_virt - _IO_BASE;
1474 return base + (address - hose->io_base_phys);
1477 return (unsigned int)-1;
1479 EXPORT_SYMBOL(pci_address_to_pio);
1482 * Null PCI config access functions, for the case when we can't
1485 #define NULL_PCI_OP(rw, size, type) \
1487 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1489 return PCIBIOS_DEVICE_NOT_FOUND; \
1493 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1496 return PCIBIOS_DEVICE_NOT_FOUND;
1500 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1503 return PCIBIOS_DEVICE_NOT_FOUND;
1506 static struct pci_ops null_pci_ops =
1513 * These functions are used early on before PCI scanning is done
1514 * and all of the pci_dev and pci_bus structures have been created.
1516 static struct pci_bus *
1517 fake_pci_bus(struct pci_controller *hose, int busnr)
1519 static struct pci_bus bus;
1522 hose = pci_bus_to_hose(busnr);
1524 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1528 bus.ops = hose? hose->ops: &null_pci_ops;
1532 #define EARLY_PCI_OP(rw, size, type) \
1533 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1534 int devfn, int offset, type value) \
1536 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1537 devfn, offset, value); \
1540 EARLY_PCI_OP(read, byte, u8 *)
1541 EARLY_PCI_OP(read, word, u16 *)
1542 EARLY_PCI_OP(read, dword, u32 *)
1543 EARLY_PCI_OP(write, byte, u8)
1544 EARLY_PCI_OP(write, word, u16)
1545 EARLY_PCI_OP(write, dword, u32)