2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 void pcibios_make_OF_bus_map(void);
40 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41 static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43 static void update_bridge_base(struct pci_bus *bus, int i);
44 static void pcibios_fixup_resources(struct pci_dev* dev);
45 static void fixup_broken_pcnet32(struct pci_dev* dev);
46 static int reparent_resources(struct resource *parent, struct resource *res);
47 static void fixup_cpc710_pci64(struct pci_dev* dev);
49 static u8* pci_to_OF_bus_map;
52 /* By default, we don't re-assign bus numbers. We do this only on
55 int pci_assign_all_buses;
59 static int pci_bus_count;
62 fixup_hide_host_resource_fsl(struct pci_dev* dev)
64 int i, class = dev->class >> 8;
66 if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
67 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
68 (dev->bus->parent == NULL)) {
69 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
70 dev->resource[i].start = 0;
71 dev->resource[i].end = 0;
72 dev->resource[i].flags = 0;
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
77 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
80 fixup_broken_pcnet32(struct pci_dev* dev)
82 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
83 dev->vendor = PCI_VENDOR_ID_AMD;
84 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
87 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
90 fixup_cpc710_pci64(struct pci_dev* dev)
92 /* Hide the PCI64 BARs from the kernel as their content doesn't
93 * fit well in the resource management
95 dev->resource[0].start = dev->resource[0].end = 0;
96 dev->resource[0].flags = 0;
97 dev->resource[1].start = dev->resource[1].end = 0;
98 dev->resource[1].flags = 0;
100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
103 pcibios_fixup_resources(struct pci_dev *dev)
105 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
107 resource_size_t offset, mask;
110 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
113 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
114 struct resource *res = dev->resource + i;
117 if (res->end == 0xffffffff) {
118 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
119 pci_name(dev), i, (u64)res->start, (u64)res->end);
120 res->end -= res->start;
122 res->flags |= IORESOURCE_UNSET;
126 mask = (resource_size_t)-1;
127 if (res->flags & IORESOURCE_MEM) {
128 offset = hose->pci_mem_offset;
129 } else if (res->flags & IORESOURCE_IO) {
130 offset = (unsigned long) hose->io_base_virt
135 res->start = (res->start + offset) & mask;
136 res->end = (res->end + offset) & mask;
137 DBG("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
138 i, res->flags, pci_name(dev),
139 (u64)res->start - offset, (u64)res->start);
143 /* Call machine specific resource fixup */
144 if (ppc_md.pcibios_fixup_resources)
145 ppc_md.pcibios_fixup_resources(dev);
147 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
149 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
150 struct resource *res)
152 resource_size_t offset = 0, mask = (resource_size_t)-1;
153 struct pci_controller *hose = dev->sysdata;
155 if (hose && res->flags & IORESOURCE_IO) {
156 offset = (unsigned long)hose->io_base_virt - isa_io_base;
158 } else if (hose && res->flags & IORESOURCE_MEM)
159 offset = hose->pci_mem_offset;
160 region->start = (res->start - offset) & mask;
161 region->end = (res->end - offset) & mask;
163 EXPORT_SYMBOL(pcibios_resource_to_bus);
165 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
166 struct pci_bus_region *region)
168 resource_size_t offset = 0, mask = (resource_size_t)-1;
169 struct pci_controller *hose = dev->sysdata;
171 if (hose && res->flags & IORESOURCE_IO) {
172 offset = (unsigned long)hose->io_base_virt - isa_io_base;
174 } else if (hose && res->flags & IORESOURCE_MEM)
175 offset = hose->pci_mem_offset;
176 res->start = (region->start + offset) & mask;
177 res->end = (region->end + offset) & mask;
179 EXPORT_SYMBOL(pcibios_bus_to_resource);
182 * We need to avoid collisions with `mirrored' VGA ports
183 * and other strange ISA hardware, so we always want the
184 * addresses to be allocated in the 0x000-0x0ff region
187 * Why? Because some silly external IO cards only decode
188 * the low 10 bits of the IO address. The 0x00-0xff region
189 * is reserved for motherboard devices that decode all 16
190 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
191 * but we want to try to avoid allocating at 0x2900-0x2bff
192 * which might have be mirrored at 0x0100-0x03ff..
194 void pcibios_align_resource(void *data, struct resource *res,
195 resource_size_t size, resource_size_t align)
197 struct pci_dev *dev = data;
199 if (res->flags & IORESOURCE_IO) {
200 resource_size_t start = res->start;
203 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
204 " (%lld bytes)\n", pci_name(dev),
205 dev->resource - res, (unsigned long long)size);
209 start = (start + 0x3ff) & ~0x3ff;
214 EXPORT_SYMBOL(pcibios_align_resource);
217 * Handle resources of PCI devices. If the world were perfect, we could
218 * just allocate all the resource regions and do nothing more. It isn't.
219 * On the other hand, we cannot just re-allocate all devices, as it would
220 * require us to know lots of host bridge internals. So we attempt to
221 * keep as much of the original configuration as possible, but tweak it
222 * when it's found to be wrong.
224 * Known BIOS problems we have to work around:
225 * - I/O or memory regions not configured
226 * - regions configured, but not enabled in the command register
227 * - bogus I/O addresses above 64K used
228 * - expansion ROMs left enabled (this may sound harmless, but given
229 * the fact the PCI specs explicitly allow address decoders to be
230 * shared between expansion ROMs and other resource regions, it's
231 * at least dangerous)
234 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
235 * This gives us fixed barriers on where we can allocate.
236 * (2) Allocate resources for all enabled devices. If there is
237 * a collision, just mark the resource as unallocated. Also
238 * disable expansion ROMs during this step.
239 * (3) Try to allocate resources for disabled devices. If the
240 * resources were assigned correctly, everything goes well,
241 * if they weren't, they won't disturb allocation of other
243 * (4) Assign new addresses to resources which were either
244 * not configured at all or misconfigured. If explicitly
245 * requested by the user, configure expansion ROM address
250 pcibios_allocate_bus_resources(struct list_head *bus_list)
254 struct resource *res, *pr;
256 /* Depth-First Search on bus tree */
257 list_for_each_entry(bus, bus_list, node) {
258 for (i = 0; i < 4; ++i) {
259 if ((res = bus->resource[i]) == NULL || !res->flags
260 || res->start > res->end)
262 if (bus->parent == NULL)
263 pr = (res->flags & IORESOURCE_IO)?
264 &ioport_resource: &iomem_resource;
266 pr = pci_find_parent_resource(bus->self, res);
268 /* this happens when the generic PCI
269 * code (wrongly) decides that this
270 * bridge is transparent -- paulus
276 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
277 (u64)res->start, (u64)res->end, res->flags, pr);
279 if (request_resource(pr, res) == 0)
282 * Must be a conflict with an existing entry.
283 * Move that entry (or entries) under the
284 * bridge resource and try again.
286 if (reparent_resources(pr, res) == 0)
289 printk(KERN_ERR "PCI: Cannot allocate resource region "
290 "%d of PCI bridge %d\n", i, bus->number);
291 if (pci_relocate_bridge_resource(bus, i))
292 bus->resource[i] = NULL;
294 pcibios_allocate_bus_resources(&bus->children);
299 * Reparent resource children of pr that conflict with res
300 * under res, and make res replace those children.
303 reparent_resources(struct resource *parent, struct resource *res)
305 struct resource *p, **pp;
306 struct resource **firstpp = NULL;
308 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
309 if (p->end < res->start)
311 if (res->end < p->start)
313 if (p->start < res->start || p->end > res->end)
314 return -1; /* not completely contained */
319 return -1; /* didn't find any conflicting entries? */
320 res->parent = parent;
321 res->child = *firstpp;
325 for (p = res->child; p != NULL; p = p->sibling) {
327 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
328 p->name, (u64)p->start, (u64)p->end, res->name);
334 * A bridge has been allocated a range which is outside the range
335 * of its parent bridge, so it needs to be moved.
338 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
340 struct resource *res, *pr, *conflict;
341 resource_size_t try, size;
342 struct pci_bus *parent = bus->parent;
345 if (parent == NULL) {
346 /* shouldn't ever happen */
347 printk(KERN_ERR "PCI: can't move host bridge resource\n");
350 res = bus->resource[i];
354 for (j = 0; j < 4; j++) {
355 struct resource *r = parent->resource[j];
358 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
360 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
364 if (res->flags & IORESOURCE_PREFETCH)
369 size = res->end - res->start;
370 if (pr->start > pr->end || size > pr->end - pr->start)
374 res->start = try - size;
376 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
378 if (conflict->start <= pr->start + size)
380 try = conflict->start - 1;
382 if (request_resource(pr, res)) {
383 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
384 (u64)res->start, (u64)res->end);
385 return -1; /* "can't happen" */
387 update_bridge_base(bus, i);
388 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
389 bus->number, i, (unsigned long long)res->start,
390 (unsigned long long)res->end);
395 probe_resource(struct pci_bus *parent, struct resource *pr,
396 struct resource *res, struct resource **conflict)
403 for (r = pr->child; r != NULL; r = r->sibling) {
404 if (r->end >= res->start && res->end >= r->start) {
409 list_for_each_entry(bus, &parent->children, node) {
410 for (i = 0; i < 4; ++i) {
411 if ((r = bus->resource[i]) == NULL)
413 if (!r->flags || r->start > r->end || r == res)
415 if (pci_find_parent_resource(bus->self, r) != pr)
417 if (r->end >= res->start && res->end >= r->start) {
423 list_for_each_entry(dev, &parent->devices, bus_list) {
424 for (i = 0; i < 6; ++i) {
425 r = &dev->resource[i];
426 if (!r->flags || (r->flags & IORESOURCE_UNSET))
428 if (pci_find_parent_resource(dev, r) != pr)
430 if (r->end >= res->start && res->end >= r->start) {
440 update_bridge_resource(struct pci_dev *dev, struct resource *res)
442 u8 io_base_lo, io_limit_lo;
443 u16 mem_base, mem_limit;
445 resource_size_t start, end, off;
446 struct pci_controller *hose = dev->sysdata;
449 printk("update_bridge_base: no hose?\n");
452 pci_read_config_word(dev, PCI_COMMAND, &cmd);
453 pci_write_config_word(dev, PCI_COMMAND,
454 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
455 if (res->flags & IORESOURCE_IO) {
456 off = (unsigned long) hose->io_base_virt - isa_io_base;
457 start = res->start - off;
458 end = res->end - off;
459 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
460 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
462 io_base_lo |= PCI_IO_RANGE_TYPE_32;
464 io_base_lo |= PCI_IO_RANGE_TYPE_16;
465 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
467 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
469 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
470 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
472 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
474 off = hose->pci_mem_offset;
475 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
476 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
477 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
478 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
480 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
481 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
482 off = hose->pci_mem_offset;
483 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
484 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
485 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
486 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
489 DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
490 pci_name(dev), res->flags);
492 pci_write_config_word(dev, PCI_COMMAND, cmd);
496 update_bridge_base(struct pci_bus *bus, int i)
498 struct resource *res = bus->resource[i];
499 struct pci_dev *dev = bus->self;
500 update_bridge_resource(dev, res);
503 static inline void alloc_resource(struct pci_dev *dev, int idx)
505 struct resource *pr, *r = &dev->resource[idx];
507 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
508 pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags);
509 pr = pci_find_parent_resource(dev, r);
510 if (!pr || request_resource(pr, r) < 0) {
511 printk(KERN_WARNING "PCI: Remapping resource region %d"
512 " of device %s\n", idx, pci_name(dev));
514 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
515 pr, (u64)pr->start, (u64)pr->end, pr->flags);
516 /* We'll assign a new address later */
517 r->flags |= IORESOURCE_UNSET;
524 pcibios_allocate_resources(int pass)
526 struct pci_dev *dev = NULL;
531 for_each_pci_dev(dev) {
532 pci_read_config_word(dev, PCI_COMMAND, &command);
533 for (idx = 0; idx < 6; idx++) {
534 r = &dev->resource[idx];
535 if (r->parent) /* Already allocated */
537 if (!r->flags || (r->flags & IORESOURCE_UNSET))
538 continue; /* Not assigned at all */
539 if (r->flags & IORESOURCE_IO)
540 disabled = !(command & PCI_COMMAND_IO);
542 disabled = !(command & PCI_COMMAND_MEMORY);
543 if (pass == disabled)
544 alloc_resource(dev, idx);
548 r = &dev->resource[PCI_ROM_RESOURCE];
549 if (r->flags & IORESOURCE_ROM_ENABLE) {
550 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
552 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
553 r->flags &= ~IORESOURCE_ROM_ENABLE;
554 pci_read_config_dword(dev, dev->rom_base_reg, ®);
555 pci_write_config_dword(dev, dev->rom_base_reg,
556 reg & ~PCI_ROM_ADDRESS_ENABLE);
562 pcibios_assign_resources(void)
564 struct pci_dev *dev = NULL;
568 for_each_pci_dev(dev) {
569 int class = dev->class >> 8;
571 /* Don't touch classless devices and host bridges */
572 if (!class || class == PCI_CLASS_BRIDGE_HOST)
575 for (idx = 0; idx < 6; idx++) {
576 r = &dev->resource[idx];
579 * We shall assign a new address to this resource,
580 * either because the BIOS (sic) forgot to do so
581 * or because we have decided the old address was
582 * unusable for some reason.
584 if ((r->flags & IORESOURCE_UNSET) && r->end &&
585 (!ppc_md.pcibios_enable_device_hook ||
586 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
589 r->flags &= ~IORESOURCE_UNSET;
590 rc = pci_assign_resource(dev, idx);
595 #if 0 /* don't assign ROMs */
596 r = &dev->resource[PCI_ROM_RESOURCE];
600 pci_assign_resource(dev, PCI_ROM_RESOURCE);
607 * Functions below are used on OpenFirmware machines.
610 make_one_node_map(struct device_node* node, u8 pci_bus)
612 const int *bus_range;
615 if (pci_bus >= pci_bus_count)
617 bus_range = of_get_property(node, "bus-range", &len);
618 if (bus_range == NULL || len < 2 * sizeof(int)) {
619 printk(KERN_WARNING "Can't get bus-range for %s, "
620 "assuming it starts at 0\n", node->full_name);
621 pci_to_OF_bus_map[pci_bus] = 0;
623 pci_to_OF_bus_map[pci_bus] = bus_range[0];
625 for (node=node->child; node != 0;node = node->sibling) {
627 const unsigned int *class_code, *reg;
629 class_code = of_get_property(node, "class-code", NULL);
630 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
631 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
633 reg = of_get_property(node, "reg", NULL);
636 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
637 if (!dev || !dev->subordinate) {
641 make_one_node_map(node, dev->subordinate->number);
647 pcibios_make_OF_bus_map(void)
650 struct pci_controller *hose, *tmp;
651 struct property *map_prop;
652 struct device_node *dn;
654 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
655 if (!pci_to_OF_bus_map) {
656 printk(KERN_ERR "Can't allocate OF bus map !\n");
660 /* We fill the bus map with invalid values, that helps
663 for (i=0; i<pci_bus_count; i++)
664 pci_to_OF_bus_map[i] = 0xff;
666 /* For each hose, we begin searching bridges */
667 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
668 struct device_node* node = hose->dn;
672 make_one_node_map(node, hose->first_busno);
674 dn = of_find_node_by_path("/");
675 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
677 BUG_ON(pci_bus_count > map_prop->length);
678 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
682 printk("PCI->OF bus map:\n");
683 for (i=0; i<pci_bus_count; i++) {
684 if (pci_to_OF_bus_map[i] == 0xff)
686 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
691 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
693 static struct device_node*
694 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
696 struct device_node* sub_node;
698 for (; node != 0;node = node->sibling) {
699 const unsigned int *class_code;
701 if (filter(node, data))
704 /* For PCI<->PCI bridges or CardBus bridges, we go down
705 * Note: some OFs create a parent node "multifunc-device" as
706 * a fake root for all functions of a multi-function device,
707 * we go down them as well.
709 class_code = of_get_property(node, "class-code", NULL);
710 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
711 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
712 strcmp(node->name, "multifunc-device"))
714 sub_node = scan_OF_pci_childs(node->child, filter, data);
721 static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
724 struct device_node *np = NULL;
728 while ((np = of_get_next_child(parent, np)) != NULL) {
729 reg = of_get_property(np, "reg", &psize);
730 if (reg == NULL || psize < 4)
732 if (((reg[0] >> 8) & 0xff) == devfn)
739 static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
741 struct device_node *parent, *np;
743 /* Are we a root bus ? */
744 if (bus->self == NULL || bus->parent == NULL) {
745 struct pci_controller *hose = pci_bus_to_host(bus);
748 return of_node_get(hose->dn);
751 /* not a root bus, we need to get our parent */
752 parent = scan_OF_for_pci_bus(bus->parent);
756 /* now iterate for children for a match */
757 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
764 * Scans the OF tree for a device node matching a PCI device
767 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
769 struct device_node *parent, *np;
774 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
775 parent = scan_OF_for_pci_bus(bus);
778 DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>");
779 np = scan_OF_for_pci_dev(parent, devfn);
781 DBG(" result is %s\n", np ? np->full_name : "<NULL>");
783 /* XXX most callers don't release the returned node
784 * mostly because ppc64 doesn't increase the refcount,
785 * we need to fix that.
789 EXPORT_SYMBOL(pci_busdev_to_OF_node);
792 pci_device_to_OF_node(struct pci_dev *dev)
794 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
796 EXPORT_SYMBOL(pci_device_to_OF_node);
799 find_OF_pci_device_filter(struct device_node* node, void* data)
801 return ((void *)node == data);
805 * Returns the PCI device matching a given OF node
808 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
810 const unsigned int *reg;
811 struct pci_controller* hose;
812 struct pci_dev* dev = NULL;
816 /* Make sure it's really a PCI device */
817 hose = pci_find_hose_for_OF_device(node);
818 if (!hose || !hose->dn)
820 if (!scan_OF_pci_childs(hose->dn->child,
821 find_OF_pci_device_filter, (void *)node))
823 reg = of_get_property(node, "reg", NULL);
826 *bus = (reg[0] >> 16) & 0xff;
827 *devfn = ((reg[0] >> 8) & 0xff);
829 /* Ok, here we need some tweak. If we have already renumbered
830 * all busses, we can't rely on the OF bus number any more.
831 * the pci_to_OF_bus_map is not enough as several PCI busses
832 * may match the same OF bus number.
834 if (!pci_to_OF_bus_map)
837 for_each_pci_dev(dev)
838 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
839 dev->devfn == *devfn) {
840 *bus = dev->bus->number;
847 EXPORT_SYMBOL(pci_device_from_OF_node);
849 /* We create the "pci-OF-bus-map" property now so it appears in the
853 pci_create_OF_bus_map(void)
855 struct property* of_prop;
856 struct device_node *dn;
858 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
861 dn = of_find_node_by_path("/");
863 memset(of_prop, -1, sizeof(struct property) + 256);
864 of_prop->name = "pci-OF-bus-map";
865 of_prop->length = 256;
866 of_prop->value = &of_prop[1];
867 prom_add_property(dn, of_prop);
872 #else /* CONFIG_PPC_OF */
873 void pcibios_make_OF_bus_map(void)
876 #endif /* CONFIG_PPC_OF */
878 #ifdef CONFIG_PPC_PMAC
880 * This set of routines checks for PCI<->PCI bridges that have closed
881 * IO resources and have child devices. It tries to re-open an IO
884 * This is a _temporary_ fix to workaround a problem with Apple's OF
885 * closing IO windows on P2P bridges when the OF drivers of cards
886 * below this bridge don't claim any IO range (typically ATI or
889 * A more complete fix would be to use drivers/pci/setup-bus.c, which
890 * involves a working pcibios_fixup_pbus_ranges(), some more care about
891 * ordering when creating the host bus resources, and maybe a few more
895 /* Initialize bridges with base/limit values we have collected */
897 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
899 struct pci_dev *bridge = bus->self;
900 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
905 if (bus->resource[0] == NULL)
907 res = *(bus->resource[0]);
909 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
910 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
911 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
912 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
914 /* Set up the top and bottom of the PCI I/O segment for this bus. */
915 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
917 l |= (res.start >> 8) & 0x00f0;
918 l |= res.end & 0xf000;
919 pci_write_config_dword(bridge, PCI_IO_BASE, l);
921 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
922 l = (res.start >> 16) | (res.end & 0xffff0000);
923 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
926 pci_read_config_word(bridge, PCI_COMMAND, &w);
928 pci_write_config_word(bridge, PCI_COMMAND, w);
930 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
932 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
933 w |= PCI_BRIDGE_CTL_VGA;
934 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
939 /* This function is pretty basic and actually quite broken for the
940 * general case, it's enough for us right now though. It's supposed
941 * to tell us if we need to open an IO range at all or not and what
945 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
951 #define push_end(res, mask) do { \
952 BUG_ON((mask+1) & mask); \
953 res->end = (res->end + mask) | mask; \
956 list_for_each_entry(dev, &bus->devices, bus_list) {
957 u16 class = dev->class >> 8;
959 if (class == PCI_CLASS_DISPLAY_VGA ||
960 class == PCI_CLASS_NOT_DEFINED_VGA)
962 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
963 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
964 if (class == PCI_CLASS_BRIDGE_CARDBUS)
965 push_end(res, 0xfff);
967 for (i=0; i<PCI_NUM_RESOURCES; i++) {
969 unsigned long r_size;
971 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
972 && i >= PCI_BRIDGE_RESOURCES)
974 r = &dev->resource[i];
975 r_size = r->end - r->start;
978 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
980 push_end(res, r_size);
988 /* Here we scan all P2P bridges of a given level that have a closed
989 * IO window. Note that the test for the presence of a VGA card should
990 * be improved to take into account already configured P2P bridges,
991 * currently, we don't see them and might end up configuring 2 bridges
992 * with VGA pass through enabled
995 do_fixup_p2p_level(struct pci_bus *bus)
1001 for (parent_io=0; parent_io<4; parent_io++)
1002 if (bus->resource[parent_io]
1003 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1008 list_for_each_entry(b, &bus->children, node) {
1009 struct pci_dev *d = b->self;
1010 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1011 struct resource *res = b->resource[0];
1012 struct resource tmp_res;
1016 memset(&tmp_res, 0, sizeof(tmp_res));
1017 tmp_res.start = bus->resource[parent_io]->start;
1019 /* We don't let low addresses go through that closed P2P bridge, well,
1020 * that may not be necessary but I feel safer that way
1022 if (tmp_res.start == 0)
1023 tmp_res.start = 0x1000;
1025 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1026 res != bus->resource[parent_io] &&
1027 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1028 check_for_io_childs(b, &tmp_res, &found_vga)) {
1031 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1035 printk(KERN_WARNING "Skipping VGA, already active"
1036 " on bus segment\n");
1041 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1043 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1044 max = ((unsigned long) hose->io_base_virt
1045 - isa_io_base) + 0xffffffff;
1047 max = ((unsigned long) hose->io_base_virt
1048 - isa_io_base) + 0xffff;
1051 res->flags = IORESOURCE_IO;
1052 res->name = b->name;
1054 /* Find a resource in the parent where we can allocate */
1055 for (i = 0 ; i < 4; i++) {
1056 struct resource *r = bus->resource[i];
1059 if ((r->flags & IORESOURCE_IO) == 0)
1061 DBG("Trying to allocate from %016llx, size %016llx from parent"
1062 " res %d: %016llx -> %016llx\n",
1063 res->start, res->end, i, r->start, r->end);
1065 if (allocate_resource(r, res, res->end + 1, res->start, max,
1066 res->end + 1, NULL, NULL) < 0) {
1070 do_update_p2p_io_resource(b, found_vga);
1074 do_fixup_p2p_level(b);
1079 pcibios_fixup_p2p_bridges(void)
1083 list_for_each_entry(b, &pci_root_buses, node)
1084 do_fixup_p2p_level(b);
1087 #endif /* CONFIG_PPC_PMAC */
1092 struct pci_controller *hose, *tmp;
1093 struct pci_bus *bus;
1096 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1098 /* Scan all of the recorded PCI controllers. */
1099 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1100 if (pci_assign_all_buses)
1101 hose->first_busno = next_busno;
1102 hose->last_busno = 0xff;
1103 bus = pci_scan_bus_parented(hose->parent, hose->first_busno,
1106 pci_bus_add_devices(bus);
1107 hose->last_busno = bus->subordinate;
1108 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1109 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1111 pci_bus_count = next_busno;
1113 /* OpenFirmware based machines need a map of OF bus
1114 * numbers vs. kernel bus numbers since we may have to
1117 if (pci_assign_all_buses && have_of)
1118 pcibios_make_OF_bus_map();
1120 /* Call machine dependent fixup */
1121 if (ppc_md.pcibios_fixup)
1122 ppc_md.pcibios_fixup();
1124 /* Allocate and assign resources */
1125 pcibios_allocate_bus_resources(&pci_root_buses);
1126 pcibios_allocate_resources(0);
1127 pcibios_allocate_resources(1);
1128 #ifdef CONFIG_PPC_PMAC
1129 pcibios_fixup_p2p_bridges();
1130 #endif /* CONFIG_PPC_PMAC */
1131 pcibios_assign_resources();
1133 /* Call machine dependent post-init code */
1134 if (ppc_md.pcibios_after_init)
1135 ppc_md.pcibios_after_init();
1140 subsys_initcall(pcibios_init);
1142 void pcibios_fixup_bus(struct pci_bus *bus)
1144 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1145 unsigned long io_offset;
1146 struct resource *res;
1147 struct pci_dev *dev;
1150 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1151 if (bus->parent == NULL) {
1152 /* This is a host bridge - fill in its resources */
1155 bus->resource[0] = res = &hose->io_resource;
1158 printk(KERN_ERR "I/O resource not set for host"
1159 " bridge %d\n", hose->global_number);
1161 res->end = IO_SPACE_LIMIT;
1162 res->flags = IORESOURCE_IO;
1164 res->start = (res->start + io_offset) & 0xffffffffu;
1165 res->end = (res->end + io_offset) & 0xffffffffu;
1167 for (i = 0; i < 3; ++i) {
1168 res = &hose->mem_resources[i];
1172 printk(KERN_ERR "Memory resource not set for "
1173 "host bridge %d\n", hose->global_number);
1174 res->start = hose->pci_mem_offset;
1176 res->flags = IORESOURCE_MEM;
1178 bus->resource[i+1] = res;
1181 /* This is a subordinate bridge */
1182 pci_read_bridge_bases(bus);
1184 for (i = 0; i < 4; ++i) {
1185 if ((res = bus->resource[i]) == NULL)
1187 if (!res->flags || bus->self->transparent)
1189 if (io_offset && (res->flags & IORESOURCE_IO)) {
1190 res->start = (res->start + io_offset) &
1192 res->end = (res->end + io_offset) &
1194 } else if (hose->pci_mem_offset
1195 && (res->flags & IORESOURCE_MEM)) {
1196 res->start += hose->pci_mem_offset;
1197 res->end += hose->pci_mem_offset;
1202 /* Platform specific bus fixups */
1203 if (ppc_md.pcibios_fixup_bus)
1204 ppc_md.pcibios_fixup_bus(bus);
1206 /* Read default IRQs and fixup if necessary */
1207 list_for_each_entry(dev, &bus->devices, bus_list) {
1208 pci_read_irq_line(dev);
1209 if (ppc_md.pci_irq_fixup)
1210 ppc_md.pci_irq_fixup(dev);
1214 /* the next one is stolen from the alpha port... */
1216 pcibios_update_irq(struct pci_dev *dev, int irq)
1218 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1219 /* XXX FIXME - update OF device tree node interrupt property */
1222 int pcibios_enable_device(struct pci_dev *dev, int mask)
1228 if (ppc_md.pcibios_enable_device_hook)
1229 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1232 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1234 for (idx=0; idx<6; idx++) {
1235 r = &dev->resource[idx];
1236 if (r->flags & IORESOURCE_UNSET) {
1237 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1240 if (r->flags & IORESOURCE_IO)
1241 cmd |= PCI_COMMAND_IO;
1242 if (r->flags & IORESOURCE_MEM)
1243 cmd |= PCI_COMMAND_MEMORY;
1245 if (cmd != old_cmd) {
1246 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1247 pci_name(dev), old_cmd, cmd);
1248 pci_write_config_word(dev, PCI_COMMAND, cmd);
1253 static struct pci_controller*
1254 pci_bus_to_hose(int bus)
1256 struct pci_controller *hose, *tmp;
1258 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1259 if (bus >= hose->first_busno && bus <= hose->last_busno)
1264 /* Provide information on locations of various I/O regions in physical
1265 * memory. Do this on a per-card basis so that we choose the right
1267 * Note that the returned IO or memory base is a physical address
1270 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1272 struct pci_controller* hose;
1273 long result = -EOPNOTSUPP;
1275 /* Argh ! Please forgive me for that hack, but that's the
1276 * simplest way to get existing XFree to not lockup on some
1277 * G5 machines... So when something asks for bus 0 io base
1278 * (bus 0 is HT root), we return the AGP one instead.
1280 #ifdef CONFIG_PPC_PMAC
1281 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1284 #endif /* CONFIG_PPC_PMAC */
1286 hose = pci_bus_to_hose(bus);
1291 case IOBASE_BRIDGE_NUMBER:
1292 return (long)hose->first_busno;
1294 return (long)hose->pci_mem_offset;
1296 return (long)hose->io_base_phys;
1298 return (long)isa_io_base;
1299 case IOBASE_ISA_MEM:
1300 return (long)isa_mem_base;
1306 unsigned long pci_address_to_pio(phys_addr_t address)
1308 struct pci_controller *hose, *tmp;
1310 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1311 unsigned int size = hose->io_resource.end -
1312 hose->io_resource.start + 1;
1313 if (address >= hose->io_base_phys &&
1314 address < (hose->io_base_phys + size)) {
1315 unsigned long base =
1316 (unsigned long)hose->io_base_virt - _IO_BASE;
1317 return base + (address - hose->io_base_phys);
1320 return (unsigned int)-1;
1322 EXPORT_SYMBOL(pci_address_to_pio);
1325 * Null PCI config access functions, for the case when we can't
1328 #define NULL_PCI_OP(rw, size, type) \
1330 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1332 return PCIBIOS_DEVICE_NOT_FOUND; \
1336 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1339 return PCIBIOS_DEVICE_NOT_FOUND;
1343 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1346 return PCIBIOS_DEVICE_NOT_FOUND;
1349 static struct pci_ops null_pci_ops =
1351 .read = null_read_config,
1352 .write = null_write_config,
1356 * These functions are used early on before PCI scanning is done
1357 * and all of the pci_dev and pci_bus structures have been created.
1359 static struct pci_bus *
1360 fake_pci_bus(struct pci_controller *hose, int busnr)
1362 static struct pci_bus bus;
1365 hose = pci_bus_to_hose(busnr);
1367 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1371 bus.ops = hose? hose->ops: &null_pci_ops;
1375 #define EARLY_PCI_OP(rw, size, type) \
1376 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1377 int devfn, int offset, type value) \
1379 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1380 devfn, offset, value); \
1383 EARLY_PCI_OP(read, byte, u8 *)
1384 EARLY_PCI_OP(read, word, u16 *)
1385 EARLY_PCI_OP(read, dword, u32 *)
1386 EARLY_PCI_OP(write, byte, u8)
1387 EARLY_PCI_OP(write, word, u16)
1388 EARLY_PCI_OP(write, dword, u32)
1390 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1391 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1394 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);