3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/threads.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
38 #define DO_SOFT_DISABLE
41 * We layout physical memory as follows:
42 * 0x0000 - 0x00ff : Secondary processor spin code
43 * 0x0100 - 0x2fff : pSeries Interrupt prologs
44 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
45 * 0x6000 - 0x6fff : Initial (CPU0) segment table
46 * 0x7000 - 0x7fff : FWNMI data area
47 * 0x8000 - : Early init and support code
55 * SPRG0 reserved for hypervisor
56 * SPRG1 temp - used to save gpr
57 * SPRG2 temp - used to save gpr
58 * SPRG3 virt addr of paca
62 * Entering into this code we make the following assumptions:
64 * 1. The MMU is off & open firmware is running in real mode.
65 * 2. The kernel is entered at __start
68 * 1. The MMU is on (as it always is for iSeries)
69 * 2. The kernel is entered at system_reset_iSeries
76 /* NOP this out unconditionally */
78 b .__start_initialization_multiplatform
81 /* Catch branch to 0 in real mode */
84 /* Secondary processors spin on this value until it goes to 1. */
85 .globl __secondary_hold_spinloop
86 __secondary_hold_spinloop:
89 /* Secondary processors write this value with their cpu # */
90 /* after they enter the spin loop immediately below. */
91 .globl __secondary_hold_acknowledge
92 __secondary_hold_acknowledge:
95 #ifdef CONFIG_PPC_ISERIES
97 * At offset 0x20, there is a pointer to iSeries LPAR data.
98 * This is required by the hypervisor
101 .llong hvReleaseData-KERNELBASE
102 #endif /* CONFIG_PPC_ISERIES */
106 * The following code is used on pSeries to hold secondary processors
107 * in a spin loop after they have been freed from OpenFirmware, but
108 * before the bulk of the kernel has been relocated. This code
109 * is relocated to physical address 0x60 before prom_init is run.
110 * All of it must fit below the first exception vector at 0x100.
112 _GLOBAL(__secondary_hold)
115 mtmsrd r24 /* RI on */
117 /* Grab our physical cpu number */
120 /* Tell the master cpu we're here */
121 /* Relocation is off & we are located at an address less */
122 /* than 0x100, so only need to grab low order offset. */
123 std r24,__secondary_hold_acknowledge@l(0)
126 /* All secondary cpus wait here until told to start. */
127 100: ld r4,__secondary_hold_spinloop@l(0)
131 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
132 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
140 /* This value is used to mark exception frames on the stack. */
143 .tc ID_72656773_68657265[TC],0x7265677368657265
147 * The following macros define the code that appears as
148 * the prologue to each of the exception handlers. They
149 * are split into two parts to allow a single kernel binary
150 * to be used for pSeries and iSeries.
151 * LOL. One day... - paulus
155 * We make as much of the exception code common between native
156 * exception handlers (including pSeries LPAR) and iSeries LPAR
157 * implementations as possible.
161 * This is the start of the interrupt handlers for pSeries
162 * This code runs with relocation off.
177 * We're short on space and time in the exception prolog, so we can't
178 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
179 * low halfword of the address, but for Kdump we need the whole low
182 #ifdef CONFIG_CRASH_DUMP
183 #define LOAD_HANDLER(reg, label) \
184 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
185 ori reg,reg,(label)@l; /* .. and the rest */
187 #define LOAD_HANDLER(reg, label) \
188 ori reg,reg,(label)@l; /* virt addr of handler ... */
192 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
193 * The firmware calls the registered system_reset_fwnmi and
194 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
195 * a 32bit application at the time of the event.
196 * This firmware bug is present on POWER4 and JS20.
198 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
199 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
200 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
201 std r10,area+EX_R10(r13); \
202 std r11,area+EX_R11(r13); \
203 std r12,area+EX_R12(r13); \
204 mfspr r9,SPRN_SPRG1; \
205 std r9,area+EX_R13(r13); \
207 clrrdi r12,r13,32; /* get high part of &label */ \
209 /* force 64bit mode */ \
210 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
211 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
212 /* done 64bit mode */ \
213 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
214 LOAD_HANDLER(r12,label) \
215 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
216 mtspr SPRN_SRR0,r12; \
217 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
218 mtspr SPRN_SRR1,r10; \
220 b . /* prevent speculative execution */
222 #define EXCEPTION_PROLOG_PSERIES(area, label) \
223 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
224 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
225 std r10,area+EX_R10(r13); \
226 std r11,area+EX_R11(r13); \
227 std r12,area+EX_R12(r13); \
228 mfspr r9,SPRN_SPRG1; \
229 std r9,area+EX_R13(r13); \
231 clrrdi r12,r13,32; /* get high part of &label */ \
233 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
234 LOAD_HANDLER(r12,label) \
235 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
236 mtspr SPRN_SRR0,r12; \
237 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
238 mtspr SPRN_SRR1,r10; \
240 b . /* prevent speculative execution */
243 * This is the start of the interrupt handlers for iSeries
244 * This code runs with relocation on.
246 #define EXCEPTION_PROLOG_ISERIES_1(area) \
247 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
248 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
249 std r10,area+EX_R10(r13); \
250 std r11,area+EX_R11(r13); \
251 std r12,area+EX_R12(r13); \
252 mfspr r9,SPRN_SPRG1; \
253 std r9,area+EX_R13(r13); \
256 #define EXCEPTION_PROLOG_ISERIES_2 \
258 ld r12,PACALPPACAPTR(r13); \
259 ld r11,LPPACASRR0(r12); \
260 ld r12,LPPACASRR1(r12); \
261 ori r10,r10,MSR_RI; \
265 * The common exception prolog is used for all except a few exceptions
266 * such as a segment miss on a kernel address. We have to be prepared
267 * to take another exception from the point where we first touch the
268 * kernel stack onwards.
270 * On entry r13 points to the paca, r9-r13 are saved in the paca,
271 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
272 * SRR1, and relocation is on.
274 #define EXCEPTION_PROLOG_COMMON(n, area) \
275 andi. r10,r12,MSR_PR; /* See if coming from user */ \
276 mr r10,r1; /* Save r1 */ \
277 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
279 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
280 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
281 bge- cr1,bad_stack; /* abort if it is */ \
282 std r9,_CCR(r1); /* save CR in stackframe */ \
283 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
284 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
285 std r10,0(r1); /* make stack chain pointer */ \
286 std r0,GPR0(r1); /* save r0 in stackframe */ \
287 std r10,GPR1(r1); /* save r1 in stackframe */ \
288 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
289 std r2,GPR2(r1); /* save r2 in stackframe */ \
290 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
291 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
292 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
293 ld r10,area+EX_R10(r13); \
296 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
297 ld r10,area+EX_R12(r13); \
298 ld r11,area+EX_R13(r13); \
302 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
303 mflr r9; /* save LR in stackframe */ \
305 mfctr r10; /* save CTR in stackframe */ \
307 lbz r10,PACASOFTIRQEN(r13); \
308 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
312 std r9,_TRAP(r1); /* set trap number */ \
314 ld r11,exception_marker@toc(r2); \
315 std r10,RESULT(r1); /* clear regs->result */ \
316 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
321 #define STD_EXCEPTION_PSERIES(n, label) \
323 .globl label##_pSeries; \
326 mtspr SPRN_SPRG1,r13; /* save r13 */ \
327 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
329 #define HSTD_EXCEPTION_PSERIES(n, label) \
331 .globl label##_pSeries; \
334 mtspr SPRN_SPRG1,r20; /* save r20 */ \
335 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
336 mtspr SPRN_SRR0,r20; \
337 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
338 mtspr SPRN_SRR1,r20; \
339 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
340 mtspr SPRN_SPRG1,r13; /* save r13 */ \
341 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
344 #define MASKABLE_EXCEPTION_PSERIES(n, label) \
346 .globl label##_pSeries; \
349 mtspr SPRN_SPRG1,r13; /* save r13 */ \
350 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
351 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
352 std r10,PACA_EXGEN+EX_R10(r13); \
353 lbz r10,PACASOFTIRQEN(r13); \
356 beq masked_interrupt; \
357 mfspr r10,SPRN_SPRG1; \
358 std r10,PACA_EXGEN+EX_R13(r13); \
359 std r11,PACA_EXGEN+EX_R11(r13); \
360 std r12,PACA_EXGEN+EX_R12(r13); \
361 clrrdi r12,r13,32; /* get high part of &label */ \
363 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
364 LOAD_HANDLER(r12,label##_common) \
365 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
366 mtspr SPRN_SRR0,r12; \
367 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
368 mtspr SPRN_SRR1,r10; \
370 b . /* prevent speculative execution */
372 #define STD_EXCEPTION_ISERIES(n, label, area) \
373 .globl label##_iSeries; \
376 mtspr SPRN_SPRG1,r13; /* save r13 */ \
377 EXCEPTION_PROLOG_ISERIES_1(area); \
378 EXCEPTION_PROLOG_ISERIES_2; \
381 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
382 .globl label##_iSeries; \
385 mtspr SPRN_SPRG1,r13; /* save r13 */ \
386 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
387 lbz r10,PACASOFTIRQEN(r13); \
389 beq- label##_iSeries_masked; \
390 EXCEPTION_PROLOG_ISERIES_2; \
393 #ifdef CONFIG_PPC_ISERIES
394 #define DISABLE_INTS \
396 stb r11,PACASOFTIRQEN(r13); \
397 BEGIN_FW_FTR_SECTION; \
398 stb r11,PACAHARDIRQEN(r13); \
399 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
400 BEGIN_FW_FTR_SECTION; \
402 ori r10,r10,MSR_EE; \
404 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
407 #define DISABLE_INTS \
409 stb r11,PACASOFTIRQEN(r13); \
410 stb r11,PACAHARDIRQEN(r13)
412 #endif /* CONFIG_PPC_ISERIES */
414 #define ENABLE_INTS \
417 rlwimi r11,r12,0,MSR_EE; \
420 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
422 .globl label##_common; \
424 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
427 addi r3,r1,STACK_FRAME_OVERHEAD; \
432 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
433 * in the idle task and therefore need the special idle handling.
435 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
437 .globl label##_common; \
439 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
443 addi r3,r1,STACK_FRAME_OVERHEAD; \
447 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
449 .globl label##_common; \
451 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
454 bl .ppc64_runlatch_on; \
455 addi r3,r1,STACK_FRAME_OVERHEAD; \
457 b .ret_from_except_lite
460 * When the idle code in power4_idle puts the CPU into NAP mode,
461 * it has to do so in a loop, and relies on the external interrupt
462 * and decrementer interrupt entry code to get it out of the loop.
463 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
464 * to signal that it is in the loop and needs help to get out.
466 #ifdef CONFIG_PPC_970_NAP
469 clrrdi r11,r1,THREAD_SHIFT; \
470 ld r9,TI_LOCAL_FLAGS(r11); \
471 andi. r10,r9,_TLF_NAPPING; \
472 bnel power4_fixup_nap; \
473 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
479 * Start of pSeries system interrupt routines
482 .globl __start_interrupts
485 STD_EXCEPTION_PSERIES(0x100, system_reset)
488 _machine_check_pSeries:
490 mtspr SPRN_SPRG1,r13 /* save r13 */
491 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
494 .globl data_access_pSeries
503 rlwimi r13,r12,16,0x20
506 beq do_stab_bolted_pSeries
509 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
510 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
513 .globl data_access_slb_pSeries
514 data_access_slb_pSeries:
517 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
518 std r3,PACA_EXSLB+EX_R3(r13)
520 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
523 /* Keep that around for when we re-implement dynamic VSIDs */
525 bge slb_miss_user_pseries
526 #endif /* __DISABLED__ */
527 std r10,PACA_EXSLB+EX_R10(r13)
528 std r11,PACA_EXSLB+EX_R11(r13)
529 std r12,PACA_EXSLB+EX_R12(r13)
531 std r10,PACA_EXSLB+EX_R13(r13)
532 mfspr r12,SPRN_SRR1 /* and SRR1 */
533 b .slb_miss_realmode /* Rel. branch works in real mode */
535 STD_EXCEPTION_PSERIES(0x400, instruction_access)
538 .globl instruction_access_slb_pSeries
539 instruction_access_slb_pSeries:
542 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
543 std r3,PACA_EXSLB+EX_R3(r13)
544 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
545 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
548 /* Keep that around for when we re-implement dynamic VSIDs */
550 bge slb_miss_user_pseries
551 #endif /* __DISABLED__ */
552 std r10,PACA_EXSLB+EX_R10(r13)
553 std r11,PACA_EXSLB+EX_R11(r13)
554 std r12,PACA_EXSLB+EX_R12(r13)
556 std r10,PACA_EXSLB+EX_R13(r13)
557 mfspr r12,SPRN_SRR1 /* and SRR1 */
558 b .slb_miss_realmode /* Rel. branch works in real mode */
560 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
561 STD_EXCEPTION_PSERIES(0x600, alignment)
562 STD_EXCEPTION_PSERIES(0x700, program_check)
563 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
564 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
565 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
566 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
569 .globl system_call_pSeries
577 oris r12,r12,system_call_common@h
578 ori r12,r12,system_call_common@l
580 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
584 b . /* prevent speculative execution */
586 STD_EXCEPTION_PSERIES(0xd00, single_step)
587 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
589 /* We need to deal with the Altivec unavailable exception
590 * here which is at 0xf20, thus in the middle of the
591 * prolog code of the PerformanceMonitor one. A little
592 * trickery is thus necessary
595 b performance_monitor_pSeries
597 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
599 #ifdef CONFIG_CBE_RAS
600 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
601 #endif /* CONFIG_CBE_RAS */
602 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
603 #ifdef CONFIG_CBE_RAS
604 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
605 #endif /* CONFIG_CBE_RAS */
606 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
607 #ifdef CONFIG_CBE_RAS
608 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
609 #endif /* CONFIG_CBE_RAS */
613 /*** pSeries interrupt support ***/
615 /* moved from 0xf00 */
616 MASKABLE_EXCEPTION_PSERIES(., performance_monitor)
619 * An interrupt came in while soft-disabled; clear EE in SRR1,
620 * clear paca->hard_enabled and return.
623 stb r10,PACAHARDIRQEN(r13)
625 ld r9,PACA_EXGEN+EX_R9(r13)
627 rldicl r10,r10,48,1 /* clear MSR_EE */
630 ld r10,PACA_EXGEN+EX_R10(r13)
636 do_stab_bolted_pSeries:
639 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
642 * We have some room here we use that to put
643 * the peries slb miss user trampoline code so it's reasonably
644 * away from slb_miss_user_common to avoid problems with rfid
646 * This is used for when the SLB miss handler has to go virtual,
647 * which doesn't happen for now anymore but will once we re-implement
648 * dynamic VSIDs for shared page tables
651 slb_miss_user_pseries:
652 std r10,PACA_EXGEN+EX_R10(r13)
653 std r11,PACA_EXGEN+EX_R11(r13)
654 std r12,PACA_EXGEN+EX_R12(r13)
656 ld r11,PACA_EXSLB+EX_R9(r13)
657 ld r12,PACA_EXSLB+EX_R3(r13)
658 std r10,PACA_EXGEN+EX_R13(r13)
659 std r11,PACA_EXGEN+EX_R9(r13)
660 std r12,PACA_EXGEN+EX_R3(r13)
663 mfspr r11,SRR0 /* save SRR0 */
664 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
665 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
667 mfspr r12,SRR1 /* and SRR1 */
670 b . /* prevent spec. execution */
671 #endif /* __DISABLED__ */
674 * Vectors for the FWNMI option. Share common code.
676 .globl system_reset_fwnmi
680 mtspr SPRN_SPRG1,r13 /* save r13 */
681 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
683 .globl machine_check_fwnmi
687 mtspr SPRN_SPRG1,r13 /* save r13 */
688 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
690 #ifdef CONFIG_PPC_ISERIES
691 /*** ISeries-LPAR interrupt handlers ***/
693 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
695 .globl data_access_iSeries
703 rlwimi r13,r12,16,0x20
706 beq .do_stab_bolted_iSeries
709 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
710 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
711 EXCEPTION_PROLOG_ISERIES_2
714 .do_stab_bolted_iSeries:
717 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
718 EXCEPTION_PROLOG_ISERIES_2
721 .globl data_access_slb_iSeries
722 data_access_slb_iSeries:
723 mtspr SPRN_SPRG1,r13 /* save r13 */
724 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
725 std r3,PACA_EXSLB+EX_R3(r13)
727 std r9,PACA_EXSLB+EX_R9(r13)
731 bge slb_miss_user_iseries
733 std r10,PACA_EXSLB+EX_R10(r13)
734 std r11,PACA_EXSLB+EX_R11(r13)
735 std r12,PACA_EXSLB+EX_R12(r13)
737 std r10,PACA_EXSLB+EX_R13(r13)
738 ld r12,PACALPPACAPTR(r13)
739 ld r12,LPPACASRR1(r12)
742 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
744 .globl instruction_access_slb_iSeries
745 instruction_access_slb_iSeries:
746 mtspr SPRN_SPRG1,r13 /* save r13 */
747 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
748 std r3,PACA_EXSLB+EX_R3(r13)
749 ld r3,PACALPPACAPTR(r13)
750 ld r3,LPPACASRR0(r3) /* get SRR0 value */
751 std r9,PACA_EXSLB+EX_R9(r13)
755 bge .slb_miss_user_iseries
757 std r10,PACA_EXSLB+EX_R10(r13)
758 std r11,PACA_EXSLB+EX_R11(r13)
759 std r12,PACA_EXSLB+EX_R12(r13)
761 std r10,PACA_EXSLB+EX_R13(r13)
762 ld r12,PACALPPACAPTR(r13)
763 ld r12,LPPACASRR1(r12)
767 slb_miss_user_iseries:
768 std r10,PACA_EXGEN+EX_R10(r13)
769 std r11,PACA_EXGEN+EX_R11(r13)
770 std r12,PACA_EXGEN+EX_R12(r13)
772 ld r11,PACA_EXSLB+EX_R9(r13)
773 ld r12,PACA_EXSLB+EX_R3(r13)
774 std r10,PACA_EXGEN+EX_R13(r13)
775 std r11,PACA_EXGEN+EX_R9(r13)
776 std r12,PACA_EXGEN+EX_R3(r13)
777 EXCEPTION_PROLOG_ISERIES_2
778 b slb_miss_user_common
781 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
782 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
783 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
784 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
785 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
786 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
787 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
789 .globl system_call_iSeries
793 EXCEPTION_PROLOG_ISERIES_2
796 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
797 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
798 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
800 .globl system_reset_iSeries
801 system_reset_iSeries:
802 mfspr r13,SPRN_SPRG3 /* Get paca address */
805 mtmsrd r24 /* RI on */
806 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
807 cmpwi 0,r24,0 /* Are we processor 0? */
808 beq .__start_initialization_iSeries /* Start up the first processor */
810 li r5,CTRL_RUNLATCH /* Turn off the run light */
817 lbz r23,PACAPROCSTART(r13) /* Test if this processor
820 LOAD_REG_IMMEDIATE(r3,current_set)
821 sldi r28,r24,3 /* get current_set[cpu#] */
823 addi r1,r3,THREAD_SIZE
824 subi r1,r1,STACK_FRAME_OVERHEAD
827 beq iSeries_secondary_smp_loop /* Loop until told to go */
828 bne __secondary_start /* Loop until told to go */
829 iSeries_secondary_smp_loop:
830 /* Let the Hypervisor know we are alive */
831 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
833 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
834 #else /* CONFIG_SMP */
835 /* Yield the processor. This is required for non-SMP kernels
836 which are running on multi-threaded machines. */
838 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
839 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
840 li r4,0 /* "yield timed" */
841 li r5,-1 /* "yield forever" */
842 #endif /* CONFIG_SMP */
843 li r0,-1 /* r0=-1 indicates a Hypervisor call */
844 sc /* Invoke the hypervisor via a system call */
845 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
846 b 1b /* If SMP not configured, secondaries
849 decrementer_iSeries_masked:
850 /* We may not have a valid TOC pointer in here. */
852 ld r12,PACALPPACAPTR(r13)
853 stb r11,LPPACADECRINT(r12)
854 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
859 hardware_interrupt_iSeries_masked:
860 mtcrf 0x80,r9 /* Restore regs */
861 ld r12,PACALPPACAPTR(r13)
862 ld r11,LPPACASRR0(r12)
863 ld r12,LPPACASRR1(r12)
866 ld r9,PACA_EXGEN+EX_R9(r13)
867 ld r10,PACA_EXGEN+EX_R10(r13)
868 ld r11,PACA_EXGEN+EX_R11(r13)
869 ld r12,PACA_EXGEN+EX_R12(r13)
870 ld r13,PACA_EXGEN+EX_R13(r13)
872 b . /* prevent speculative execution */
873 #endif /* CONFIG_PPC_ISERIES */
875 /*** Common interrupt handlers ***/
877 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
880 * Machine check is different because we use a different
881 * save area: PACA_EXMC instead of PACA_EXGEN.
884 .globl machine_check_common
885 machine_check_common:
886 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
890 addi r3,r1,STACK_FRAME_OVERHEAD
891 bl .machine_check_exception
894 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
895 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
896 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
897 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
898 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
899 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
900 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
901 #ifdef CONFIG_ALTIVEC
902 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
904 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
906 #ifdef CONFIG_CBE_RAS
907 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
908 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
909 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
910 #endif /* CONFIG_CBE_RAS */
913 * Here we have detected that the kernel stack pointer is bad.
914 * R9 contains the saved CR, r13 points to the paca,
915 * r10 contains the (bad) kernel stack pointer,
916 * r11 and r12 contain the saved SRR0 and SRR1.
917 * We switch to using an emergency stack, save the registers there,
918 * and call kernel_bad_stack(), which panics.
921 ld r1,PACAEMERGSP(r13)
922 subi r1,r1,64+INT_FRAME_SIZE
943 addi r11,r1,INT_FRAME_SIZE
948 1: addi r3,r1,STACK_FRAME_OVERHEAD
953 * Return from an exception with minimal checks.
954 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
955 * If interrupts have been enabled, or anything has been
956 * done that might have changed the scheduling status of
957 * any task or sent any task a signal, you should use
958 * ret_from_except or ret_from_except_lite instead of this.
960 fast_exc_return_irq: /* restores irq state too */
963 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
964 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
965 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
968 .globl fast_exception_return
969 fast_exception_return:
972 andi. r3,r12,MSR_RI /* check if RI is set */
975 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
978 ACCOUNT_CPU_USER_EXIT(r3, r4)
994 rldicl r10,r10,48,1 /* clear EE */
995 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
1003 b . /* prevent speculative execution */
1007 1: addi r3,r1,STACK_FRAME_OVERHEAD
1008 bl .unrecoverable_exception
1012 * Here r13 points to the paca, r9 contains the saved CR,
1013 * SRR0 and SRR1 are saved in r11 and r12,
1014 * r9 - r13 are saved in paca->exgen.
1017 .globl data_access_common
1020 std r10,PACA_EXGEN+EX_DAR(r13)
1021 mfspr r10,SPRN_DSISR
1022 stw r10,PACA_EXGEN+EX_DSISR(r13)
1023 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1024 ld r3,PACA_EXGEN+EX_DAR(r13)
1025 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1027 b .do_hash_page /* Try to handle as hpte fault */
1030 .globl instruction_access_common
1031 instruction_access_common:
1032 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1034 andis. r4,r12,0x5820
1036 b .do_hash_page /* Try to handle as hpte fault */
1039 * Here is the common SLB miss user that is used when going to virtual
1040 * mode for SLB misses, that is currently not used
1044 .globl slb_miss_user_common
1045 slb_miss_user_common:
1047 std r3,PACA_EXGEN+EX_DAR(r13)
1048 stw r9,PACA_EXGEN+EX_CCR(r13)
1049 std r10,PACA_EXGEN+EX_LR(r13)
1050 std r11,PACA_EXGEN+EX_SRR0(r13)
1051 bl .slb_allocate_user
1053 ld r10,PACA_EXGEN+EX_LR(r13)
1054 ld r3,PACA_EXGEN+EX_R3(r13)
1055 lwz r9,PACA_EXGEN+EX_CCR(r13)
1056 ld r11,PACA_EXGEN+EX_SRR0(r13)
1060 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1061 beq- unrecov_user_slb
1069 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
1075 ld r9,PACA_EXGEN+EX_R9(r13)
1076 ld r10,PACA_EXGEN+EX_R10(r13)
1077 ld r11,PACA_EXGEN+EX_R11(r13)
1078 ld r12,PACA_EXGEN+EX_R12(r13)
1079 ld r13,PACA_EXGEN+EX_R13(r13)
1084 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1085 ld r4,PACA_EXGEN+EX_DAR(r13)
1092 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1095 1: addi r3,r1,STACK_FRAME_OVERHEAD
1096 bl .unrecoverable_exception
1099 #endif /* __DISABLED__ */
1103 * r13 points to the PACA, r9 contains the saved CR,
1104 * r12 contain the saved SRR1, SRR0 is still ready for return
1105 * r3 has the faulting address
1106 * r9 - r13 are saved in paca->exslb.
1107 * r3 is saved in paca->slb_r3
1108 * We assume we aren't going to take any exceptions during this procedure.
1110 _GLOBAL(slb_miss_realmode)
1113 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1114 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1116 bl .slb_allocate_realmode
1118 /* All done -- return from exception. */
1120 ld r10,PACA_EXSLB+EX_LR(r13)
1121 ld r3,PACA_EXSLB+EX_R3(r13)
1122 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1123 #ifdef CONFIG_PPC_ISERIES
1124 BEGIN_FW_FTR_SECTION
1125 ld r11,PACALPPACAPTR(r13)
1126 ld r11,LPPACASRR0(r11) /* get SRR0 value */
1127 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1128 #endif /* CONFIG_PPC_ISERIES */
1132 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1138 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1141 #ifdef CONFIG_PPC_ISERIES
1142 BEGIN_FW_FTR_SECTION
1145 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1146 #endif /* CONFIG_PPC_ISERIES */
1147 ld r9,PACA_EXSLB+EX_R9(r13)
1148 ld r10,PACA_EXSLB+EX_R10(r13)
1149 ld r11,PACA_EXSLB+EX_R11(r13)
1150 ld r12,PACA_EXSLB+EX_R12(r13)
1151 ld r13,PACA_EXSLB+EX_R13(r13)
1153 b . /* prevent speculative execution */
1156 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1159 1: addi r3,r1,STACK_FRAME_OVERHEAD
1160 bl .unrecoverable_exception
1164 .globl hardware_interrupt_common
1165 .globl hardware_interrupt_entry
1166 hardware_interrupt_common:
1167 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1169 hardware_interrupt_entry:
1171 bl .ppc64_runlatch_on
1172 addi r3,r1,STACK_FRAME_OVERHEAD
1174 b .ret_from_except_lite
1176 #ifdef CONFIG_PPC_970_NAP
1179 std r9,TI_LOCAL_FLAGS(r11)
1180 ld r10,_LINK(r1) /* make idle task do the */
1181 std r10,_NIP(r1) /* equivalent of a blr */
1186 .globl alignment_common
1189 std r10,PACA_EXGEN+EX_DAR(r13)
1190 mfspr r10,SPRN_DSISR
1191 stw r10,PACA_EXGEN+EX_DSISR(r13)
1192 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1193 ld r3,PACA_EXGEN+EX_DAR(r13)
1194 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1198 addi r3,r1,STACK_FRAME_OVERHEAD
1200 bl .alignment_exception
1204 .globl program_check_common
1205 program_check_common:
1206 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1208 addi r3,r1,STACK_FRAME_OVERHEAD
1210 bl .program_check_exception
1214 .globl fp_unavailable_common
1215 fp_unavailable_common:
1216 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1217 bne 1f /* if from user, just load it up */
1219 addi r3,r1,STACK_FRAME_OVERHEAD
1221 bl .kernel_fp_unavailable_exception
1226 .globl altivec_unavailable_common
1227 altivec_unavailable_common:
1228 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1229 #ifdef CONFIG_ALTIVEC
1231 bne .load_up_altivec /* if from user, just load it up */
1232 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1235 addi r3,r1,STACK_FRAME_OVERHEAD
1237 bl .altivec_unavailable_exception
1240 #ifdef CONFIG_ALTIVEC
1242 * load_up_altivec(unused, unused, tsk)
1243 * Disable VMX for the task which had it previously,
1244 * and save its vector registers in its thread_struct.
1245 * Enables the VMX for use in the kernel on return.
1246 * On SMP we know the VMX is free, since we give it up every
1247 * switch (ie, no lazy save of the vector registers).
1248 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1250 _STATIC(load_up_altivec)
1251 mfmsr r5 /* grab the current MSR */
1252 oris r5,r5,MSR_VEC@h
1253 mtmsrd r5 /* enable use of VMX now */
1257 * For SMP, we don't do lazy VMX switching because it just gets too
1258 * horrendously complex, especially when a task switches from one CPU
1259 * to another. Instead we call giveup_altvec in switch_to.
1260 * VRSAVE isn't dealt with here, that is done in the normal context
1261 * switch code. Note that we could rely on vrsave value to eventually
1262 * avoid saving all of the VREGs here...
1265 ld r3,last_task_used_altivec@got(r2)
1269 /* Save VMX state to last_task_used_altivec's THREAD struct */
1275 /* Disable VMX for last_task_used_altivec */
1277 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1280 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1282 #endif /* CONFIG_SMP */
1283 /* Hack: if we get an altivec unavailable trap with VRSAVE
1284 * set to all zeros, we assume this is a broken application
1285 * that fails to set it properly, and thus we switch it to
1288 mfspr r4,SPRN_VRSAVE
1292 mtspr SPRN_VRSAVE,r4
1294 /* enable use of VMX after return */
1295 ld r4,PACACURRENT(r13)
1296 addi r5,r4,THREAD /* Get THREAD */
1297 oris r12,r12,MSR_VEC@h
1301 stw r4,THREAD_USED_VR(r5)
1306 /* Update last_task_used_math to 'current' */
1307 subi r4,r5,THREAD /* Back to 'current' */
1309 #endif /* CONFIG_SMP */
1310 /* restore registers and return */
1311 b fast_exception_return
1312 #endif /* CONFIG_ALTIVEC */
1318 _GLOBAL(do_hash_page)
1322 andis. r0,r4,0xa450 /* weird error? */
1323 bne- handle_page_fault /* if not, try to insert a HPTE */
1325 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1326 bne- do_ste_alloc /* If so handle it */
1327 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1330 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1331 * accessing a userspace segment (even from the kernel). We assume
1332 * kernel addresses always have the high bit set.
1334 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1335 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1336 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1337 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1338 ori r4,r4,1 /* add _PAGE_PRESENT */
1339 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1342 * On iSeries, we soft-disable interrupts here, then
1343 * hard-enable interrupts so that the hash_page code can spin on
1344 * the hash_table_lock without problems on a shared processor.
1349 * r3 contains the faulting address
1350 * r4 contains the required access permissions
1351 * r5 contains the trap number
1353 * at return r3 = 0 for success
1355 bl .hash_page /* build HPTE if possible */
1356 cmpdi r3,0 /* see if hash_page succeeded */
1358 #ifdef DO_SOFT_DISABLE
1359 BEGIN_FW_FTR_SECTION
1361 * If we had interrupts soft-enabled at the point where the
1362 * DSI/ISI occurred, and an interrupt came in during hash_page,
1364 * We jump to ret_from_except_lite rather than fast_exception_return
1365 * because ret_from_except_lite will check for and handle pending
1366 * interrupts if necessary.
1369 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1371 BEGIN_FW_FTR_SECTION
1373 * Here we have interrupts hard-disabled, so it is sufficient
1374 * to restore paca->{soft,hard}_enable and get out.
1376 beq fast_exc_return_irq /* Return from exception on success */
1377 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1379 /* For a hash failure, we don't bother re-enabling interrupts */
1383 * hash_page couldn't handle it, set soft interrupt enable back
1384 * to what it was before the trap. Note that .local_irq_restore
1385 * handles any interrupts pending at this point.
1388 bl .local_irq_restore
1391 /* Here we have a page fault that hash_page can't handle. */
1396 addi r3,r1,STACK_FRAME_OVERHEAD
1402 addi r3,r1,STACK_FRAME_OVERHEAD
1407 13: b .ret_from_except_lite
1409 /* We have a page fault that hash_page could handle but HV refused
1413 addi r3,r1,STACK_FRAME_OVERHEAD
1418 /* here we have a segment miss */
1420 bl .ste_allocate /* try to insert stab entry */
1422 bne- handle_page_fault
1423 b fast_exception_return
1426 * r13 points to the PACA, r9 contains the saved CR,
1427 * r11 and r12 contain the saved SRR0 and SRR1.
1428 * r9 - r13 are saved in paca->exslb.
1429 * We assume we aren't going to take any exceptions during this procedure.
1430 * We assume (DAR >> 60) == 0xc.
1433 _GLOBAL(do_stab_bolted)
1434 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1435 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1437 /* Hash to the primary group */
1438 ld r10,PACASTABVIRT(r13)
1441 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1443 /* Calculate VSID */
1444 /* This is a kernel address, so protovsid = ESID */
1445 ASM_VSID_SCRAMBLE(r11, r9)
1446 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1448 /* Search the primary group for a free entry */
1449 1: ld r11,0(r10) /* Test valid bit of the current ste */
1456 /* Stick for only searching the primary group for now. */
1457 /* At least for now, we use a very simple random castout scheme */
1458 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1460 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1463 /* r10 currently points to an ste one past the group of interest */
1464 /* make it point to the randomly selected entry */
1466 or r10,r10,r11 /* r10 is the entry to invalidate */
1468 isync /* mark the entry invalid */
1470 rldicl r11,r11,56,1 /* clear the valid bit */
1475 clrrdi r11,r11,28 /* Get the esid part of the ste */
1478 2: std r9,8(r10) /* Store the vsid part of the ste */
1481 mfspr r11,SPRN_DAR /* Get the new esid */
1482 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1483 ori r11,r11,0x90 /* Turn on valid and kp */
1484 std r11,0(r10) /* Put new entry back into the stab */
1488 /* All done -- return from exception. */
1489 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1490 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1492 andi. r10,r12,MSR_RI
1495 mtcrf 0x80,r9 /* restore CR */
1503 ld r9,PACA_EXSLB+EX_R9(r13)
1504 ld r10,PACA_EXSLB+EX_R10(r13)
1505 ld r11,PACA_EXSLB+EX_R11(r13)
1506 ld r12,PACA_EXSLB+EX_R12(r13)
1507 ld r13,PACA_EXSLB+EX_R13(r13)
1509 b . /* prevent speculative execution */
1512 * Space for CPU0's segment table.
1514 * On iSeries, the hypervisor must fill in at least one entry before
1515 * we get control (with relocate on). The address is give to the hv
1516 * as a page number (see xLparMap in lpardata.c), so this must be at a
1517 * fixed address (the linker can't compute (u64)&initial_stab >>
1520 . = STAB0_OFFSET /* 0x6000 */
1526 * Data area reserved for FWNMI option.
1527 * This address (0x7000) is fixed by the RPA.
1530 .globl fwnmi_data_area
1533 /* iSeries does not use the FWNMI stuff, so it is safe to put
1534 * this here, even if we later allow kernels that will boot on
1535 * both pSeries and iSeries */
1536 #ifdef CONFIG_PPC_ISERIES
1538 #include "lparmap.s"
1540 * This ".text" is here for old compilers that generate a trailing
1541 * .note section when compiling .c files to .s
1544 #endif /* CONFIG_PPC_ISERIES */
1549 * On pSeries and most other platforms, secondary processors spin
1550 * in the following code.
1551 * At entry, r3 = this processor's number (physical cpu id)
1553 _GLOBAL(generic_secondary_smp_init)
1556 /* turn on 64-bit mode */
1560 /* Set up a paca value for this processor. Since we have the
1561 * physical cpu id in r24, we need to search the pacas to find
1562 * which logical id maps to our physical one.
1564 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1565 li r5,0 /* logical cpu id */
1566 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1567 cmpw r6,r24 /* Compare to our id */
1569 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1574 mr r3,r24 /* not found, copy phys to r3 */
1575 b .kexec_wait /* next kernel might do better */
1577 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1578 /* From now on, r24 is expected to be logical cpuid */
1581 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1586 b 3b /* Never go on non-SMP */
1589 beq 3b /* Loop until told to go */
1591 /* See if we need to call a cpu state restore handler */
1592 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1594 ld r23,CPU_SPEC_RESTORE(r23)
1601 4: /* Create a temp kernel stack for use before relocation is on. */
1602 ld r1,PACAEMERGSP(r13)
1603 subi r1,r1,STACK_FRAME_OVERHEAD
1608 #ifdef CONFIG_PPC_ISERIES
1609 _STATIC(__start_initialization_iSeries)
1610 /* Clear out the BSS */
1611 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1612 LOAD_REG_IMMEDIATE(r8,__bss_start)
1613 sub r11,r11,r8 /* bss size */
1614 addi r11,r11,7 /* round up to an even double word */
1615 rldicl. r11,r11,61,3 /* shift right by 3 */
1619 mtctr r11 /* zero this many doublewords */
1623 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1624 addi r1,r1,THREAD_SIZE
1626 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1628 LOAD_REG_IMMEDIATE(r2,__toc_start)
1632 bl .iSeries_early_setup
1635 /* relocation is on at this point */
1637 b .start_here_common
1638 #endif /* CONFIG_PPC_ISERIES */
1643 andi. r0,r3,MSR_IR|MSR_DR
1650 b . /* prevent speculative execution */
1654 * Here is our main kernel entry point. We support currently 2 kind of entries
1655 * depending on the value of r5.
1657 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1660 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1661 * DT block, r4 is a physical pointer to the kernel itself
1664 _GLOBAL(__start_initialization_multiplatform)
1666 * Are we booted from a PROM Of-type client-interface ?
1669 bne .__boot_from_prom /* yes -> prom */
1671 /* Save parameters */
1675 /* Make sure we are running in 64 bits mode */
1678 /* Setup some critical 970 SPRs before switching MMU off */
1681 cmpwi r0,0x39 /* 970 */
1683 cmpwi r0,0x3c /* 970FX */
1685 cmpwi r0,0x44 /* 970MP */
1687 cmpwi r0,0x45 /* 970GX */
1689 1: bl .__cpu_preinit_ppc970
1692 /* Switch off MMU if not already */
1693 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1696 b .__after_prom_start
1698 _STATIC(__boot_from_prom)
1699 /* Save parameters */
1707 * Align the stack to 16-byte boundary
1708 * Depending on the size and layout of the ELF sections in the initial
1709 * boot binary, the stack pointer will be unalignet on PowerMac
1713 /* Make sure we are running in 64 bits mode */
1716 /* put a relocation offset into r3 */
1719 LOAD_REG_IMMEDIATE(r2,__toc_start)
1723 /* Relocate the TOC from a virt addr to a real addr */
1726 /* Restore parameters */
1733 /* Do all of the interaction with OF client interface */
1735 /* We never return */
1739 * At this point, r3 contains the physical address we are running at,
1740 * returned by prom_init()
1742 _STATIC(__after_prom_start)
1745 * We need to run with __start at physical address PHYSICAL_START.
1746 * This will leave some code in the first 256B of
1747 * real memory, which are reserved for software use.
1748 * The remainder of the first page is loaded with the fixed
1749 * interrupt vectors. The next two pages are filled with
1750 * unknown exception placeholders.
1752 * Note: This process overwrites the OF exception vectors.
1753 * r26 == relocation offset
1758 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1760 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1762 // XXX FIXME: Use phys returned by OF (r30)
1763 add r4,r27,r26 /* source addr */
1764 /* current address of _start */
1765 /* i.e. where we are running */
1766 /* the source addr */
1768 cmpdi r4,0 /* In some cases the loader may */
1769 beq .start_here_multiplatform /* have already put us at zero */
1770 /* so we can skip the copy. */
1771 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1774 li r6,0x100 /* Start offset, the first 0x100 */
1775 /* bytes were copied earlier. */
1777 bl .copy_and_flush /* copy the first n bytes */
1778 /* this includes the code being */
1779 /* executed here. */
1781 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1782 mtctr r0 /* that we just made/relocated */
1785 4: LOAD_REG_IMMEDIATE(r5,klimit)
1787 ld r5,0(r5) /* get the value of klimit */
1789 bl .copy_and_flush /* copy the rest */
1790 b .start_here_multiplatform
1793 * Copy routine used to copy the kernel to start at physical address 0
1794 * and flush and invalidate the caches as needed.
1795 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1796 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1798 * Note: this routine *only* clobbers r0, r6 and lr
1800 _GLOBAL(copy_and_flush)
1803 4: li r0,8 /* Use the smallest common */
1804 /* denominator cache line */
1805 /* size. This results in */
1806 /* extra cache line flushes */
1807 /* but operation is correct. */
1808 /* Can't get cache line size */
1809 /* from NACA as it is being */
1812 mtctr r0 /* put # words/line in ctr */
1813 3: addi r6,r6,8 /* copy a cache line */
1817 dcbst r6,r3 /* write it to memory */
1819 icbi r6,r3 /* flush the icache line */
1831 #ifdef CONFIG_PPC_PMAC
1833 * On PowerMac, secondary processors starts from the reset vector, which
1834 * is temporarily turned into a call to one of the functions below.
1839 .globl __secondary_start_pmac_0
1840 __secondary_start_pmac_0:
1841 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1851 _GLOBAL(pmac_secondary_start)
1852 /* turn on 64-bit mode */
1856 /* Copy some CPU settings from CPU 0 */
1857 bl .__restore_cpu_ppc970
1859 /* pSeries do that early though I don't think we really need it */
1862 mtmsrd r3 /* RI on */
1864 /* Set up a paca value for this processor. */
1865 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1866 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1867 add r13,r13,r4 /* for this processor. */
1868 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1870 /* Create a temp kernel stack for use before relocation is on. */
1871 ld r1,PACAEMERGSP(r13)
1872 subi r1,r1,STACK_FRAME_OVERHEAD
1876 #endif /* CONFIG_PPC_PMAC */
1879 * This function is called after the master CPU has released the
1880 * secondary processors. The execution environment is relocation off.
1881 * The paca for this processor has the following fields initialized at
1883 * 1. Processor number
1884 * 2. Segment table pointer (virtual address)
1885 * On entry the following are set:
1886 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1887 * r24 = cpu# (in Linux terms)
1888 * r13 = paca virtual address
1889 * SPRG3 = paca virtual address
1892 /* Set thread priority to MEDIUM */
1898 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1899 bl .early_setup_secondary
1901 /* Initialize the kernel stack. Just a repeat for iSeries. */
1902 LOAD_REG_ADDR(r3, current_set)
1903 sldi r28,r24,3 /* get current_set[cpu#] */
1905 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1906 std r1,PACAKSAVE(r13)
1908 /* Clear backchain so we get nice backtraces */
1912 /* enable MMU and jump to start_secondary */
1913 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1914 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1915 #ifdef CONFIG_PPC_ISERIES
1916 BEGIN_FW_FTR_SECTION
1918 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1920 BEGIN_FW_FTR_SECTION
1921 stb r7,PACASOFTIRQEN(r13)
1922 stb r7,PACAHARDIRQEN(r13)
1923 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1928 b . /* prevent speculative execution */
1931 * Running with relocation on at this point. All we want to do is
1932 * zero the stack back-chain pointer before going into C code.
1934 _GLOBAL(start_secondary_prolog)
1936 std r3,0(r1) /* Zero the stack frame pointer */
1942 * This subroutine clobbers r11 and r12
1944 _GLOBAL(enable_64b_mode)
1945 mfmsr r11 /* grab the current MSR */
1947 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1950 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1957 * This is where the main kernel code starts.
1959 _STATIC(start_here_multiplatform)
1960 /* get a new offset, now that the kernel has moved. */
1964 /* Clear out the BSS. It may have been done in prom_init,
1965 * already but that's irrelevant since prom_init will soon
1966 * be detached from the kernel completely. Besides, we need
1967 * to clear it now for kexec-style entry.
1969 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1970 LOAD_REG_IMMEDIATE(r8,__bss_start)
1971 sub r11,r11,r8 /* bss size */
1972 addi r11,r11,7 /* round up to an even double word */
1973 rldicl. r11,r11,61,3 /* shift right by 3 */
1977 mtctr r11 /* zero this many doublewords */
1984 mtmsrd r6 /* RI on */
1986 /* The following gets the stack and TOC set up with the regs */
1987 /* pointing to the real addr of the kernel stack. This is */
1988 /* all done to support the C function call below which sets */
1989 /* up the htab. This is done because we have relocated the */
1990 /* kernel but are still running in real mode. */
1992 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1995 /* set up a stack pointer (physical address) */
1996 addi r1,r3,THREAD_SIZE
1998 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2000 /* set up the TOC (physical address) */
2001 LOAD_REG_IMMEDIATE(r2,__toc_start)
2006 /* Do very early kernel initializations, including initial hash table,
2007 * stab and slb setup before we turn on relocation. */
2009 /* Restore parameters passed from prom_init/kexec */
2013 LOAD_REG_IMMEDIATE(r3, .start_here_common)
2014 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
2018 b . /* prevent speculative execution */
2020 /* This is where all platforms converge execution */
2021 _STATIC(start_here_common)
2022 /* relocation is on at this point */
2024 /* The following code sets up the SP and TOC now that we are */
2025 /* running with translation enabled. */
2027 LOAD_REG_IMMEDIATE(r3,init_thread_union)
2029 /* set up the stack */
2030 addi r1,r3,THREAD_SIZE
2032 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2034 /* ptr to current */
2035 LOAD_REG_IMMEDIATE(r4, init_task)
2036 std r4,PACACURRENT(r13)
2040 std r1,PACAKSAVE(r13)
2044 /* Load up the kernel context */
2047 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
2048 #ifdef CONFIG_PPC_ISERIES
2049 BEGIN_FW_FTR_SECTION
2051 ori r5,r5,MSR_EE /* Hard Enabled */
2053 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2055 BEGIN_FW_FTR_SECTION
2056 stb r5,PACAHARDIRQEN(r13)
2057 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
2065 * We put a few things here that have to be page-aligned.
2066 * This stuff goes at the beginning of the bss, which is page-aligned.
2072 .globl empty_zero_page
2076 .globl swapper_pg_dir
2081 * This space gets a copy of optional info passed to us by the bootstrap
2082 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2086 .space COMMAND_LINE_SIZE