2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #include <linux/config.h>
27 #include <linux/threads.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/iseries/lpar_map.h>
38 #include <asm/thread_info.h>
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
45 * We layout physical memory as follows:
46 * 0x0000 - 0x00ff : Secondary processor spin code
47 * 0x0100 - 0x2fff : pSeries Interrupt prologs
48 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
49 * 0x6000 - 0x6fff : Initial (CPU0) segment table
50 * 0x7000 - 0x7fff : FWNMI data area
51 * 0x8000 - : Early init and support code
59 * SPRG0 reserved for hypervisor
60 * SPRG1 temp - used to save gpr
61 * SPRG2 temp - used to save gpr
62 * SPRG3 virt addr of paca
66 * Entering into this code we make the following assumptions:
68 * 1. The MMU is off & open firmware is running in real mode.
69 * 2. The kernel is entered at __start
72 * 1. The MMU is on (as it always is for iSeries)
73 * 2. The kernel is entered at system_reset_iSeries
79 #ifdef CONFIG_PPC_MULTIPLATFORM
81 /* NOP this out unconditionally */
83 b .__start_initialization_multiplatform
85 #endif /* CONFIG_PPC_MULTIPLATFORM */
87 /* Catch branch to 0 in real mode */
90 #ifdef CONFIG_PPC_ISERIES
92 * At offset 0x20, there is a pointer to iSeries LPAR data.
93 * This is required by the hypervisor
96 .llong hvReleaseData-KERNELBASE
99 * At offset 0x28 and 0x30 are offsets to the mschunks_map
100 * array (used by the iSeries LPAR debugger to do translation
101 * between physical addresses and absolute addresses) and
102 * to the pidhash table (also used by the debugger)
104 .llong mschunks_map-KERNELBASE
105 .llong 0 /* pidhash-KERNELBASE SFRXXX */
107 /* Offset 0x38 - Pointer to start of embedded System.map */
108 .globl embedded_sysmap_start
109 embedded_sysmap_start:
111 /* Offset 0x40 - Pointer to end of embedded System.map */
112 .globl embedded_sysmap_end
116 #endif /* CONFIG_PPC_ISERIES */
118 /* Secondary processors spin on this value until it goes to 1. */
119 .globl __secondary_hold_spinloop
120 __secondary_hold_spinloop:
123 /* Secondary processors write this value with their cpu # */
124 /* after they enter the spin loop immediately below. */
125 .globl __secondary_hold_acknowledge
126 __secondary_hold_acknowledge:
131 * The following code is used on pSeries to hold secondary processors
132 * in a spin loop after they have been freed from OpenFirmware, but
133 * before the bulk of the kernel has been relocated. This code
134 * is relocated to physical address 0x60 before prom_init is run.
135 * All of it must fit below the first exception vector at 0x100.
137 _GLOBAL(__secondary_hold)
140 mtmsrd r24 /* RI on */
142 /* Grab our linux cpu number */
145 /* Tell the master cpu we're here */
146 /* Relocation is off & we are located at an address less */
147 /* than 0x100, so only need to grab low order offset. */
148 std r24,__secondary_hold_acknowledge@l(0)
151 /* All secondary cpus wait here until told to start. */
152 100: ld r4,__secondary_hold_spinloop@l(0)
157 SET_REG_IMMEDIATE(r4, .hmt_init)
162 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
171 /* This value is used to mark exception frames on the stack. */
174 .tc ID_72656773_68657265[TC],0x7265677368657265
178 * The following macros define the code that appears as
179 * the prologue to each of the exception handlers. They
180 * are split into two parts to allow a single kernel binary
181 * to be used for pSeries and iSeries.
182 * LOL. One day... - paulus
186 * We make as much of the exception code common between native
187 * exception handlers (including pSeries LPAR) and iSeries LPAR
188 * implementations as possible.
192 * This is the start of the interrupt handlers for pSeries
193 * This code runs with relocation off.
208 * We're short on space and time in the exception prolog, so we can't
209 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
210 * low halfword of the address, but for Kdump we need the whole low
213 #ifdef CONFIG_CRASH_DUMP
214 #define LOAD_HANDLER(reg, label) \
215 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
216 ori reg,reg,(label)@l; /* .. and the rest */
218 #define LOAD_HANDLER(reg, label) \
219 ori reg,reg,(label)@l; /* virt addr of handler ... */
222 #define EXCEPTION_PROLOG_PSERIES(area, label) \
223 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
224 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
225 std r10,area+EX_R10(r13); \
226 std r11,area+EX_R11(r13); \
227 std r12,area+EX_R12(r13); \
228 mfspr r9,SPRN_SPRG1; \
229 std r9,area+EX_R13(r13); \
231 clrrdi r12,r13,32; /* get high part of &label */ \
233 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
234 LOAD_HANDLER(r12,label) \
235 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
236 mtspr SPRN_SRR0,r12; \
237 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
238 mtspr SPRN_SRR1,r10; \
240 b . /* prevent speculative execution */
243 * This is the start of the interrupt handlers for iSeries
244 * This code runs with relocation on.
246 #define EXCEPTION_PROLOG_ISERIES_1(area) \
247 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
248 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
249 std r10,area+EX_R10(r13); \
250 std r11,area+EX_R11(r13); \
251 std r12,area+EX_R12(r13); \
252 mfspr r9,SPRN_SPRG1; \
253 std r9,area+EX_R13(r13); \
256 #define EXCEPTION_PROLOG_ISERIES_2 \
258 ld r11,PACALPPACA+LPPACASRR0(r13); \
259 ld r12,PACALPPACA+LPPACASRR1(r13); \
260 ori r10,r10,MSR_RI; \
264 * The common exception prolog is used for all except a few exceptions
265 * such as a segment miss on a kernel address. We have to be prepared
266 * to take another exception from the point where we first touch the
267 * kernel stack onwards.
269 * On entry r13 points to the paca, r9-r13 are saved in the paca,
270 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
271 * SRR1, and relocation is on.
273 #define EXCEPTION_PROLOG_COMMON(n, area) \
274 andi. r10,r12,MSR_PR; /* See if coming from user */ \
275 mr r10,r1; /* Save r1 */ \
276 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
278 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
279 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
280 bge- cr1,bad_stack; /* abort if it is */ \
281 std r9,_CCR(r1); /* save CR in stackframe */ \
282 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
283 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
284 std r10,0(r1); /* make stack chain pointer */ \
285 std r0,GPR0(r1); /* save r0 in stackframe */ \
286 std r10,GPR1(r1); /* save r1 in stackframe */ \
287 std r2,GPR2(r1); /* save r2 in stackframe */ \
288 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
289 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
290 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
291 ld r10,area+EX_R10(r13); \
294 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
295 ld r10,area+EX_R12(r13); \
296 ld r11,area+EX_R13(r13); \
300 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
301 mflr r9; /* save LR in stackframe */ \
303 mfctr r10; /* save CTR in stackframe */ \
305 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
308 std r9,_TRAP(r1); /* set trap number */ \
310 ld r11,exception_marker@toc(r2); \
311 std r10,RESULT(r1); /* clear regs->result */ \
312 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
317 #define STD_EXCEPTION_PSERIES(n, label) \
319 .globl label##_pSeries; \
322 mtspr SPRN_SPRG1,r13; /* save r13 */ \
324 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
326 #define STD_EXCEPTION_ISERIES(n, label, area) \
327 .globl label##_iSeries; \
330 mtspr SPRN_SPRG1,r13; /* save r13 */ \
332 EXCEPTION_PROLOG_ISERIES_1(area); \
333 EXCEPTION_PROLOG_ISERIES_2; \
336 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
337 .globl label##_iSeries; \
340 mtspr SPRN_SPRG1,r13; /* save r13 */ \
342 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
343 lbz r10,PACAPROCENABLED(r13); \
345 beq- label##_iSeries_masked; \
346 EXCEPTION_PROLOG_ISERIES_2; \
349 #ifdef DO_SOFT_DISABLE
350 #define DISABLE_INTS \
351 lbz r10,PACAPROCENABLED(r13); \
355 stb r11,PACAPROCENABLED(r13); \
356 ori r10,r10,MSR_EE; \
359 #define ENABLE_INTS \
360 lbz r10,PACAPROCENABLED(r13); \
363 ori r11,r11,MSR_EE; \
366 #else /* hard enable/disable interrupts */
369 #define ENABLE_INTS \
372 rlwimi r11,r12,0,MSR_EE; \
377 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
379 .globl label##_common; \
381 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
384 addi r3,r1,STACK_FRAME_OVERHEAD; \
388 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
390 .globl label##_common; \
392 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
394 addi r3,r1,STACK_FRAME_OVERHEAD; \
396 b .ret_from_except_lite
399 * Start of pSeries system interrupt routines
402 .globl __start_interrupts
405 STD_EXCEPTION_PSERIES(0x100, system_reset)
408 _machine_check_pSeries:
410 mtspr SPRN_SPRG1,r13 /* save r13 */
412 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
415 .globl data_access_pSeries
424 rlwimi r13,r12,16,0x20
427 beq .do_stab_bolted_pSeries
430 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
431 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
434 .globl data_access_slb_pSeries
435 data_access_slb_pSeries:
439 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
440 std r3,PACA_EXSLB+EX_R3(r13)
442 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
445 /* Keep that around for when we re-implement dynamic VSIDs */
447 bge slb_miss_user_pseries
448 #endif /* __DISABLED__ */
449 std r10,PACA_EXSLB+EX_R10(r13)
450 std r11,PACA_EXSLB+EX_R11(r13)
451 std r12,PACA_EXSLB+EX_R12(r13)
453 std r10,PACA_EXSLB+EX_R13(r13)
454 mfspr r12,SPRN_SRR1 /* and SRR1 */
455 b .slb_miss_realmode /* Rel. branch works in real mode */
457 STD_EXCEPTION_PSERIES(0x400, instruction_access)
460 .globl instruction_access_slb_pSeries
461 instruction_access_slb_pSeries:
465 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
466 std r3,PACA_EXSLB+EX_R3(r13)
467 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
468 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
471 /* Keep that around for when we re-implement dynamic VSIDs */
473 bge slb_miss_user_pseries
474 #endif /* __DISABLED__ */
475 std r10,PACA_EXSLB+EX_R10(r13)
476 std r11,PACA_EXSLB+EX_R11(r13)
477 std r12,PACA_EXSLB+EX_R12(r13)
479 std r10,PACA_EXSLB+EX_R13(r13)
480 mfspr r12,SPRN_SRR1 /* and SRR1 */
481 b .slb_miss_realmode /* Rel. branch works in real mode */
483 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
484 STD_EXCEPTION_PSERIES(0x600, alignment)
485 STD_EXCEPTION_PSERIES(0x700, program_check)
486 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
487 STD_EXCEPTION_PSERIES(0x900, decrementer)
488 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
489 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
492 .globl system_call_pSeries
501 oris r12,r12,system_call_common@h
502 ori r12,r12,system_call_common@l
504 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
508 b . /* prevent speculative execution */
510 STD_EXCEPTION_PSERIES(0xd00, single_step)
511 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
513 /* We need to deal with the Altivec unavailable exception
514 * here which is at 0xf20, thus in the middle of the
515 * prolog code of the PerformanceMonitor one. A little
516 * trickery is thus necessary
519 b performance_monitor_pSeries
521 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
523 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
524 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
528 /*** pSeries interrupt support ***/
530 /* moved from 0xf00 */
531 STD_EXCEPTION_PSERIES(., performance_monitor)
534 _GLOBAL(do_stab_bolted_pSeries)
537 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
540 * We have some room here we use that to put
541 * the peries slb miss user trampoline code so it's reasonably
542 * away from slb_miss_user_common to avoid problems with rfid
544 * This is used for when the SLB miss handler has to go virtual,
545 * which doesn't happen for now anymore but will once we re-implement
546 * dynamic VSIDs for shared page tables
549 slb_miss_user_pseries:
550 std r10,PACA_EXGEN+EX_R10(r13)
551 std r11,PACA_EXGEN+EX_R11(r13)
552 std r12,PACA_EXGEN+EX_R12(r13)
554 ld r11,PACA_EXSLB+EX_R9(r13)
555 ld r12,PACA_EXSLB+EX_R3(r13)
556 std r10,PACA_EXGEN+EX_R13(r13)
557 std r11,PACA_EXGEN+EX_R9(r13)
558 std r12,PACA_EXGEN+EX_R3(r13)
561 mfspr r11,SRR0 /* save SRR0 */
562 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
563 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
565 mfspr r12,SRR1 /* and SRR1 */
568 b . /* prevent spec. execution */
569 #endif /* __DISABLED__ */
572 * Vectors for the FWNMI option. Share common code.
574 .globl system_reset_fwnmi
578 mtspr SPRN_SPRG1,r13 /* save r13 */
580 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
582 .globl machine_check_fwnmi
586 mtspr SPRN_SPRG1,r13 /* save r13 */
588 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
590 #ifdef CONFIG_PPC_ISERIES
591 /*** ISeries-LPAR interrupt handlers ***/
593 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
595 .globl data_access_iSeries
603 rlwimi r13,r12,16,0x20
606 beq .do_stab_bolted_iSeries
609 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
610 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
611 EXCEPTION_PROLOG_ISERIES_2
614 .do_stab_bolted_iSeries:
617 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
618 EXCEPTION_PROLOG_ISERIES_2
621 .globl data_access_slb_iSeries
622 data_access_slb_iSeries:
623 mtspr SPRN_SPRG1,r13 /* save r13 */
624 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
625 std r3,PACA_EXSLB+EX_R3(r13)
627 std r9,PACA_EXSLB+EX_R9(r13)
631 bge slb_miss_user_iseries
633 std r10,PACA_EXSLB+EX_R10(r13)
634 std r11,PACA_EXSLB+EX_R11(r13)
635 std r12,PACA_EXSLB+EX_R12(r13)
637 std r10,PACA_EXSLB+EX_R13(r13)
638 ld r12,PACALPPACA+LPPACASRR1(r13);
641 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
643 .globl instruction_access_slb_iSeries
644 instruction_access_slb_iSeries:
645 mtspr SPRN_SPRG1,r13 /* save r13 */
646 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
647 std r3,PACA_EXSLB+EX_R3(r13)
648 ld r3,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
649 std r9,PACA_EXSLB+EX_R9(r13)
653 bge .slb_miss_user_iseries
655 std r10,PACA_EXSLB+EX_R10(r13)
656 std r11,PACA_EXSLB+EX_R11(r13)
657 std r12,PACA_EXSLB+EX_R12(r13)
659 std r10,PACA_EXSLB+EX_R13(r13)
660 ld r12,PACALPPACA+LPPACASRR1(r13);
664 slb_miss_user_iseries:
665 std r10,PACA_EXGEN+EX_R10(r13)
666 std r11,PACA_EXGEN+EX_R11(r13)
667 std r12,PACA_EXGEN+EX_R12(r13)
669 ld r11,PACA_EXSLB+EX_R9(r13)
670 ld r12,PACA_EXSLB+EX_R3(r13)
671 std r10,PACA_EXGEN+EX_R13(r13)
672 std r11,PACA_EXGEN+EX_R9(r13)
673 std r12,PACA_EXGEN+EX_R3(r13)
674 EXCEPTION_PROLOG_ISERIES_2
675 b slb_miss_user_common
678 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
679 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
680 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
681 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
682 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
683 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
684 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
686 .globl system_call_iSeries
690 EXCEPTION_PROLOG_ISERIES_2
693 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
694 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
695 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
697 .globl system_reset_iSeries
698 system_reset_iSeries:
699 mfspr r13,SPRN_SPRG3 /* Get paca address */
702 mtmsrd r24 /* RI on */
703 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
704 cmpwi 0,r24,0 /* Are we processor 0? */
705 beq .__start_initialization_iSeries /* Start up the first processor */
707 li r5,CTRL_RUNLATCH /* Turn off the run light */
714 lbz r23,PACAPROCSTART(r13) /* Test if this processor
717 LOAD_REG_IMMEDIATE(r3,current_set)
718 sldi r28,r24,3 /* get current_set[cpu#] */
720 addi r1,r3,THREAD_SIZE
721 subi r1,r1,STACK_FRAME_OVERHEAD
724 beq iSeries_secondary_smp_loop /* Loop until told to go */
725 bne .__secondary_start /* Loop until told to go */
726 iSeries_secondary_smp_loop:
727 /* Let the Hypervisor know we are alive */
728 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
730 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
731 #else /* CONFIG_SMP */
732 /* Yield the processor. This is required for non-SMP kernels
733 which are running on multi-threaded machines. */
735 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
736 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
737 li r4,0 /* "yield timed" */
738 li r5,-1 /* "yield forever" */
739 #endif /* CONFIG_SMP */
740 li r0,-1 /* r0=-1 indicates a Hypervisor call */
741 sc /* Invoke the hypervisor via a system call */
742 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
743 b 1b /* If SMP not configured, secondaries
746 .globl decrementer_iSeries_masked
747 decrementer_iSeries_masked:
749 stb r11,PACALPPACA+LPPACADECRINT(r13)
750 LOAD_REG_ADDRBASE(r12,tb_ticks_per_jiffy)
751 lwz r12,ADDROFF(tb_ticks_per_jiffy)(r12)
755 .globl hardware_interrupt_iSeries_masked
756 hardware_interrupt_iSeries_masked:
757 mtcrf 0x80,r9 /* Restore regs */
758 ld r11,PACALPPACA+LPPACASRR0(r13)
759 ld r12,PACALPPACA+LPPACASRR1(r13)
762 ld r9,PACA_EXGEN+EX_R9(r13)
763 ld r10,PACA_EXGEN+EX_R10(r13)
764 ld r11,PACA_EXGEN+EX_R11(r13)
765 ld r12,PACA_EXGEN+EX_R12(r13)
766 ld r13,PACA_EXGEN+EX_R13(r13)
768 b . /* prevent speculative execution */
769 #endif /* CONFIG_PPC_ISERIES */
771 /*** Common interrupt handlers ***/
773 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
776 * Machine check is different because we use a different
777 * save area: PACA_EXMC instead of PACA_EXGEN.
780 .globl machine_check_common
781 machine_check_common:
782 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
785 addi r3,r1,STACK_FRAME_OVERHEAD
786 bl .machine_check_exception
789 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
790 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
791 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
792 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
793 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
794 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
795 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
796 #ifdef CONFIG_ALTIVEC
797 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
799 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
803 * Here we have detected that the kernel stack pointer is bad.
804 * R9 contains the saved CR, r13 points to the paca,
805 * r10 contains the (bad) kernel stack pointer,
806 * r11 and r12 contain the saved SRR0 and SRR1.
807 * We switch to using an emergency stack, save the registers there,
808 * and call kernel_bad_stack(), which panics.
811 ld r1,PACAEMERGSP(r13)
812 subi r1,r1,64+INT_FRAME_SIZE
833 addi r11,r1,INT_FRAME_SIZE
838 1: addi r3,r1,STACK_FRAME_OVERHEAD
843 * Return from an exception with minimal checks.
844 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
845 * If interrupts have been enabled, or anything has been
846 * done that might have changed the scheduling status of
847 * any task or sent any task a signal, you should use
848 * ret_from_except or ret_from_except_lite instead of this.
850 .globl fast_exception_return
851 fast_exception_return:
854 andi. r3,r12,MSR_RI /* check if RI is set */
868 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
876 b . /* prevent speculative execution */
880 1: addi r3,r1,STACK_FRAME_OVERHEAD
881 bl .unrecoverable_exception
885 * Here r13 points to the paca, r9 contains the saved CR,
886 * SRR0 and SRR1 are saved in r11 and r12,
887 * r9 - r13 are saved in paca->exgen.
890 .globl data_access_common
892 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
894 std r10,PACA_EXGEN+EX_DAR(r13)
896 stw r10,PACA_EXGEN+EX_DSISR(r13)
897 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
898 ld r3,PACA_EXGEN+EX_DAR(r13)
899 lwz r4,PACA_EXGEN+EX_DSISR(r13)
901 b .do_hash_page /* Try to handle as hpte fault */
904 .globl instruction_access_common
905 instruction_access_common:
906 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
910 b .do_hash_page /* Try to handle as hpte fault */
913 * Here is the common SLB miss user that is used when going to virtual
914 * mode for SLB misses, that is currently not used
918 .globl slb_miss_user_common
919 slb_miss_user_common:
921 std r3,PACA_EXGEN+EX_DAR(r13)
922 stw r9,PACA_EXGEN+EX_CCR(r13)
923 std r10,PACA_EXGEN+EX_LR(r13)
924 std r11,PACA_EXGEN+EX_SRR0(r13)
925 bl .slb_allocate_user
927 ld r10,PACA_EXGEN+EX_LR(r13)
928 ld r3,PACA_EXGEN+EX_R3(r13)
929 lwz r9,PACA_EXGEN+EX_CCR(r13)
930 ld r11,PACA_EXGEN+EX_SRR0(r13)
934 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
935 beq- unrecov_user_slb
943 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
949 ld r9,PACA_EXGEN+EX_R9(r13)
950 ld r10,PACA_EXGEN+EX_R10(r13)
951 ld r11,PACA_EXGEN+EX_R11(r13)
952 ld r12,PACA_EXGEN+EX_R12(r13)
953 ld r13,PACA_EXGEN+EX_R13(r13)
958 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
959 ld r4,PACA_EXGEN+EX_DAR(r13)
966 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
969 1: addi r3,r1,STACK_FRAME_OVERHEAD
970 bl .unrecoverable_exception
973 #endif /* __DISABLED__ */
977 * r13 points to the PACA, r9 contains the saved CR,
978 * r12 contain the saved SRR1, SRR0 is still ready for return
979 * r3 has the faulting address
980 * r9 - r13 are saved in paca->exslb.
981 * r3 is saved in paca->slb_r3
982 * We assume we aren't going to take any exceptions during this procedure.
984 _GLOBAL(slb_miss_realmode)
987 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
988 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
990 bl .slb_allocate_realmode
992 /* All done -- return from exception. */
994 ld r10,PACA_EXSLB+EX_LR(r13)
995 ld r3,PACA_EXSLB+EX_R3(r13)
996 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
997 #ifdef CONFIG_PPC_ISERIES
998 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
999 #endif /* CONFIG_PPC_ISERIES */
1003 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1009 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1012 #ifdef CONFIG_PPC_ISERIES
1015 #endif /* CONFIG_PPC_ISERIES */
1016 ld r9,PACA_EXSLB+EX_R9(r13)
1017 ld r10,PACA_EXSLB+EX_R10(r13)
1018 ld r11,PACA_EXSLB+EX_R11(r13)
1019 ld r12,PACA_EXSLB+EX_R12(r13)
1020 ld r13,PACA_EXSLB+EX_R13(r13)
1022 b . /* prevent speculative execution */
1025 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1028 1: addi r3,r1,STACK_FRAME_OVERHEAD
1029 bl .unrecoverable_exception
1033 .globl hardware_interrupt_common
1034 .globl hardware_interrupt_entry
1035 hardware_interrupt_common:
1036 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1037 hardware_interrupt_entry:
1039 addi r3,r1,STACK_FRAME_OVERHEAD
1041 b .ret_from_except_lite
1044 .globl alignment_common
1047 std r10,PACA_EXGEN+EX_DAR(r13)
1048 mfspr r10,SPRN_DSISR
1049 stw r10,PACA_EXGEN+EX_DSISR(r13)
1050 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1051 ld r3,PACA_EXGEN+EX_DAR(r13)
1052 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1056 addi r3,r1,STACK_FRAME_OVERHEAD
1058 bl .alignment_exception
1062 .globl program_check_common
1063 program_check_common:
1064 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1066 addi r3,r1,STACK_FRAME_OVERHEAD
1068 bl .program_check_exception
1072 .globl fp_unavailable_common
1073 fp_unavailable_common:
1074 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1075 bne .load_up_fpu /* if from user, just load it up */
1077 addi r3,r1,STACK_FRAME_OVERHEAD
1079 bl .kernel_fp_unavailable_exception
1083 .globl altivec_unavailable_common
1084 altivec_unavailable_common:
1085 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1086 #ifdef CONFIG_ALTIVEC
1088 bne .load_up_altivec /* if from user, just load it up */
1089 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1092 addi r3,r1,STACK_FRAME_OVERHEAD
1094 bl .altivec_unavailable_exception
1097 #ifdef CONFIG_ALTIVEC
1099 * load_up_altivec(unused, unused, tsk)
1100 * Disable VMX for the task which had it previously,
1101 * and save its vector registers in its thread_struct.
1102 * Enables the VMX for use in the kernel on return.
1103 * On SMP we know the VMX is free, since we give it up every
1104 * switch (ie, no lazy save of the vector registers).
1105 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1107 _STATIC(load_up_altivec)
1108 mfmsr r5 /* grab the current MSR */
1109 oris r5,r5,MSR_VEC@h
1110 mtmsrd r5 /* enable use of VMX now */
1114 * For SMP, we don't do lazy VMX switching because it just gets too
1115 * horrendously complex, especially when a task switches from one CPU
1116 * to another. Instead we call giveup_altvec in switch_to.
1117 * VRSAVE isn't dealt with here, that is done in the normal context
1118 * switch code. Note that we could rely on vrsave value to eventually
1119 * avoid saving all of the VREGs here...
1122 ld r3,last_task_used_altivec@got(r2)
1126 /* Save VMX state to last_task_used_altivec's THREAD struct */
1132 /* Disable VMX for last_task_used_altivec */
1134 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1137 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1139 #endif /* CONFIG_SMP */
1140 /* Hack: if we get an altivec unavailable trap with VRSAVE
1141 * set to all zeros, we assume this is a broken application
1142 * that fails to set it properly, and thus we switch it to
1145 mfspr r4,SPRN_VRSAVE
1149 mtspr SPRN_VRSAVE,r4
1151 /* enable use of VMX after return */
1152 ld r4,PACACURRENT(r13)
1153 addi r5,r4,THREAD /* Get THREAD */
1154 oris r12,r12,MSR_VEC@h
1158 stw r4,THREAD_USED_VR(r5)
1163 /* Update last_task_used_math to 'current' */
1164 subi r4,r5,THREAD /* Back to 'current' */
1166 #endif /* CONFIG_SMP */
1167 /* restore registers and return */
1168 b fast_exception_return
1169 #endif /* CONFIG_ALTIVEC */
1175 _GLOBAL(do_hash_page)
1179 andis. r0,r4,0xa450 /* weird error? */
1180 bne- .handle_page_fault /* if not, try to insert a HPTE */
1182 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1183 bne- .do_ste_alloc /* If so handle it */
1184 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1187 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1188 * accessing a userspace segment (even from the kernel). We assume
1189 * kernel addresses always have the high bit set.
1191 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1192 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1193 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1194 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1195 ori r4,r4,1 /* add _PAGE_PRESENT */
1196 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1199 * On iSeries, we soft-disable interrupts here, then
1200 * hard-enable interrupts so that the hash_page code can spin on
1201 * the hash_table_lock without problems on a shared processor.
1206 * r3 contains the faulting address
1207 * r4 contains the required access permissions
1208 * r5 contains the trap number
1210 * at return r3 = 0 for success
1212 bl .hash_page /* build HPTE if possible */
1213 cmpdi r3,0 /* see if hash_page succeeded */
1215 #ifdef DO_SOFT_DISABLE
1217 * If we had interrupts soft-enabled at the point where the
1218 * DSI/ISI occurred, and an interrupt came in during hash_page,
1220 * We jump to ret_from_except_lite rather than fast_exception_return
1221 * because ret_from_except_lite will check for and handle pending
1222 * interrupts if necessary.
1224 beq .ret_from_except_lite
1225 /* For a hash failure, we don't bother re-enabling interrupts */
1229 * hash_page couldn't handle it, set soft interrupt enable back
1230 * to what it was before the trap. Note that .local_irq_restore
1231 * handles any interrupts pending at this point.
1234 bl .local_irq_restore
1237 beq fast_exception_return /* Return from exception on success */
1238 ble- 12f /* Failure return from hash_page */
1243 /* Here we have a page fault that hash_page can't handle. */
1244 _GLOBAL(handle_page_fault)
1248 addi r3,r1,STACK_FRAME_OVERHEAD
1251 beq+ .ret_from_except_lite
1254 addi r3,r1,STACK_FRAME_OVERHEAD
1259 /* We have a page fault that hash_page could handle but HV refused
1263 addi r3,r1,STACK_FRAME_OVERHEAD
1268 /* here we have a segment miss */
1269 _GLOBAL(do_ste_alloc)
1270 bl .ste_allocate /* try to insert stab entry */
1272 beq+ fast_exception_return
1273 b .handle_page_fault
1276 * r13 points to the PACA, r9 contains the saved CR,
1277 * r11 and r12 contain the saved SRR0 and SRR1.
1278 * r9 - r13 are saved in paca->exslb.
1279 * We assume we aren't going to take any exceptions during this procedure.
1280 * We assume (DAR >> 60) == 0xc.
1283 _GLOBAL(do_stab_bolted)
1284 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1285 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1287 /* Hash to the primary group */
1288 ld r10,PACASTABVIRT(r13)
1291 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1293 /* Calculate VSID */
1294 /* This is a kernel address, so protovsid = ESID */
1295 ASM_VSID_SCRAMBLE(r11, r9)
1296 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1298 /* Search the primary group for a free entry */
1299 1: ld r11,0(r10) /* Test valid bit of the current ste */
1306 /* Stick for only searching the primary group for now. */
1307 /* At least for now, we use a very simple random castout scheme */
1308 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1310 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1313 /* r10 currently points to an ste one past the group of interest */
1314 /* make it point to the randomly selected entry */
1316 or r10,r10,r11 /* r10 is the entry to invalidate */
1318 isync /* mark the entry invalid */
1320 rldicl r11,r11,56,1 /* clear the valid bit */
1325 clrrdi r11,r11,28 /* Get the esid part of the ste */
1328 2: std r9,8(r10) /* Store the vsid part of the ste */
1331 mfspr r11,SPRN_DAR /* Get the new esid */
1332 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1333 ori r11,r11,0x90 /* Turn on valid and kp */
1334 std r11,0(r10) /* Put new entry back into the stab */
1338 /* All done -- return from exception. */
1339 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1340 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1342 andi. r10,r12,MSR_RI
1345 mtcrf 0x80,r9 /* restore CR */
1353 ld r9,PACA_EXSLB+EX_R9(r13)
1354 ld r10,PACA_EXSLB+EX_R10(r13)
1355 ld r11,PACA_EXSLB+EX_R11(r13)
1356 ld r12,PACA_EXSLB+EX_R12(r13)
1357 ld r13,PACA_EXSLB+EX_R13(r13)
1359 b . /* prevent speculative execution */
1362 * Space for CPU0's segment table.
1364 * On iSeries, the hypervisor must fill in at least one entry before
1365 * we get control (with relocate on). The address is give to the hv
1366 * as a page number (see xLparMap in lpardata.c), so this must be at a
1367 * fixed address (the linker can't compute (u64)&initial_stab >>
1370 . = STAB0_OFFSET /* 0x6000 */
1376 * Data area reserved for FWNMI option.
1377 * This address (0x7000) is fixed by the RPA.
1380 .globl fwnmi_data_area
1383 /* iSeries does not use the FWNMI stuff, so it is safe to put
1384 * this here, even if we later allow kernels that will boot on
1385 * both pSeries and iSeries */
1386 #ifdef CONFIG_PPC_ISERIES
1388 #include "lparmap.s"
1390 * This ".text" is here for old compilers that generate a trailing
1391 * .note section when compiling .c files to .s
1394 #endif /* CONFIG_PPC_ISERIES */
1399 * On pSeries, secondary processors spin in the following code.
1400 * At entry, r3 = this processor's number (physical cpu id)
1402 _GLOBAL(pSeries_secondary_smp_init)
1405 /* turn on 64-bit mode */
1409 /* Copy some CPU settings from CPU 0 */
1410 bl .__restore_cpu_setup
1412 /* Set up a paca value for this processor. Since we have the
1413 * physical cpu id in r24, we need to search the pacas to find
1414 * which logical id maps to our physical one.
1416 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1417 li r5,0 /* logical cpu id */
1418 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1419 cmpw r6,r24 /* Compare to our id */
1421 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1426 mr r3,r24 /* not found, copy phys to r3 */
1427 b .kexec_wait /* next kernel might do better */
1429 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1430 /* From now on, r24 is expected to be logical cpuid */
1433 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1437 /* Create a temp kernel stack for use before relocation is on. */
1438 ld r1,PACAEMERGSP(r13)
1439 subi r1,r1,STACK_FRAME_OVERHEAD
1443 bne .__secondary_start
1445 b 3b /* Loop until told to go */
1447 #ifdef CONFIG_PPC_ISERIES
1448 _STATIC(__start_initialization_iSeries)
1449 /* Clear out the BSS */
1450 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1451 LOAD_REG_IMMEDIATE(r8,__bss_start)
1452 sub r11,r11,r8 /* bss size */
1453 addi r11,r11,7 /* round up to an even double word */
1454 rldicl. r11,r11,61,3 /* shift right by 3 */
1458 mtctr r11 /* zero this many doublewords */
1462 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1463 addi r1,r1,THREAD_SIZE
1465 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1467 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1468 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1472 LOAD_REG_IMMEDIATE(r2,__toc_start)
1476 bl .iSeries_early_setup
1479 /* relocation is on at this point */
1481 b .start_here_common
1482 #endif /* CONFIG_PPC_ISERIES */
1484 #ifdef CONFIG_PPC_MULTIPLATFORM
1488 andi. r0,r3,MSR_IR|MSR_DR
1495 b . /* prevent speculative execution */
1499 * Here is our main kernel entry point. We support currently 2 kind of entries
1500 * depending on the value of r5.
1502 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1505 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1506 * DT block, r4 is a physical pointer to the kernel itself
1509 _GLOBAL(__start_initialization_multiplatform)
1510 #ifdef CONFIG_PPC_MULTIPLATFORM
1512 * Are we booted from a PROM Of-type client-interface ?
1515 bne .__boot_from_prom /* yes -> prom */
1518 /* Save parameters */
1522 /* Make sure we are running in 64 bits mode */
1525 /* Setup some critical 970 SPRs before switching MMU off */
1526 bl .__970_cpu_preinit
1531 /* Switch off MMU if not already */
1532 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1535 b .__after_prom_start
1537 #ifdef CONFIG_PPC_MULTIPLATFORM
1538 _STATIC(__boot_from_prom)
1539 /* Save parameters */
1546 /* Make sure we are running in 64 bits mode */
1549 /* put a relocation offset into r3 */
1552 LOAD_REG_IMMEDIATE(r2,__toc_start)
1556 /* Relocate the TOC from a virt addr to a real addr */
1559 /* Restore parameters */
1566 /* Do all of the interaction with OF client interface */
1568 /* We never return */
1573 * At this point, r3 contains the physical address we are running at,
1574 * returned by prom_init()
1576 _STATIC(__after_prom_start)
1579 * We need to run with __start at physical address PHYSICAL_START.
1580 * This will leave some code in the first 256B of
1581 * real memory, which are reserved for software use.
1582 * The remainder of the first page is loaded with the fixed
1583 * interrupt vectors. The next two pages are filled with
1584 * unknown exception placeholders.
1586 * Note: This process overwrites the OF exception vectors.
1587 * r26 == relocation offset
1592 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1594 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1596 // XXX FIXME: Use phys returned by OF (r30)
1597 add r4,r27,r26 /* source addr */
1598 /* current address of _start */
1599 /* i.e. where we are running */
1600 /* the source addr */
1602 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1605 li r6,0x100 /* Start offset, the first 0x100 */
1606 /* bytes were copied earlier. */
1608 bl .copy_and_flush /* copy the first n bytes */
1609 /* this includes the code being */
1610 /* executed here. */
1612 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1613 mtctr r0 /* that we just made/relocated */
1616 4: LOAD_REG_IMMEDIATE(r5,klimit)
1618 ld r5,0(r5) /* get the value of klimit */
1620 bl .copy_and_flush /* copy the rest */
1621 b .start_here_multiplatform
1623 #endif /* CONFIG_PPC_MULTIPLATFORM */
1626 * Copy routine used to copy the kernel to start at physical address 0
1627 * and flush and invalidate the caches as needed.
1628 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1629 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1631 * Note: this routine *only* clobbers r0, r6 and lr
1633 _GLOBAL(copy_and_flush)
1636 4: li r0,16 /* Use the least common */
1637 /* denominator cache line */
1638 /* size. This results in */
1639 /* extra cache line flushes */
1640 /* but operation is correct. */
1641 /* Can't get cache line size */
1642 /* from NACA as it is being */
1645 mtctr r0 /* put # words/line in ctr */
1646 3: addi r6,r6,8 /* copy a cache line */
1650 dcbst r6,r3 /* write it to memory */
1652 icbi r6,r3 /* flush the icache line */
1664 #ifdef CONFIG_PPC_PMAC
1666 * On PowerMac, secondary processors starts from the reset vector, which
1667 * is temporarily turned into a call to one of the functions below.
1672 .globl __secondary_start_pmac_0
1673 __secondary_start_pmac_0:
1674 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1684 _GLOBAL(pmac_secondary_start)
1685 /* turn on 64-bit mode */
1689 /* Copy some CPU settings from CPU 0 */
1690 bl .__restore_cpu_setup
1692 /* pSeries do that early though I don't think we really need it */
1695 mtmsrd r3 /* RI on */
1697 /* Set up a paca value for this processor. */
1698 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1699 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1700 add r13,r13,r4 /* for this processor. */
1701 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1703 /* Create a temp kernel stack for use before relocation is on. */
1704 ld r1,PACAEMERGSP(r13)
1705 subi r1,r1,STACK_FRAME_OVERHEAD
1707 b .__secondary_start
1709 #endif /* CONFIG_PPC_PMAC */
1712 * This function is called after the master CPU has released the
1713 * secondary processors. The execution environment is relocation off.
1714 * The paca for this processor has the following fields initialized at
1716 * 1. Processor number
1717 * 2. Segment table pointer (virtual address)
1718 * On entry the following are set:
1719 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1720 * r24 = cpu# (in Linux terms)
1721 * r13 = paca virtual address
1722 * SPRG3 = paca virtual address
1724 _GLOBAL(__secondary_start)
1725 /* Set thread priority to MEDIUM */
1731 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1732 bl .early_setup_secondary
1734 /* Initialize the kernel stack. Just a repeat for iSeries. */
1735 LOAD_REG_ADDR(r3, current_set)
1736 sldi r28,r24,3 /* get current_set[cpu#] */
1738 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1739 std r1,PACAKSAVE(r13)
1741 /* Clear backchain so we get nice backtraces */
1745 /* enable MMU and jump to start_secondary */
1746 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1747 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1748 #ifdef DO_SOFT_DISABLE
1754 b . /* prevent speculative execution */
1757 * Running with relocation on at this point. All we want to do is
1758 * zero the stack back-chain pointer before going into C code.
1760 _GLOBAL(start_secondary_prolog)
1762 std r3,0(r1) /* Zero the stack frame pointer */
1768 * This subroutine clobbers r11 and r12
1770 _GLOBAL(enable_64b_mode)
1771 mfmsr r11 /* grab the current MSR */
1773 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1776 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1782 #ifdef CONFIG_PPC_MULTIPLATFORM
1784 * This is where the main kernel code starts.
1786 _STATIC(start_here_multiplatform)
1787 /* get a new offset, now that the kernel has moved. */
1791 /* Clear out the BSS. It may have been done in prom_init,
1792 * already but that's irrelevant since prom_init will soon
1793 * be detached from the kernel completely. Besides, we need
1794 * to clear it now for kexec-style entry.
1796 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1797 LOAD_REG_IMMEDIATE(r8,__bss_start)
1798 sub r11,r11,r8 /* bss size */
1799 addi r11,r11,7 /* round up to an even double word */
1800 rldicl. r11,r11,61,3 /* shift right by 3 */
1804 mtctr r11 /* zero this many doublewords */
1811 mtmsrd r6 /* RI on */
1814 /* Start up the second thread on cpu 0 */
1817 cmpwi r3,0x34 /* Pulsar */
1819 cmpwi r3,0x36 /* Icestar */
1821 cmpwi r3,0x37 /* SStar */
1823 b 91f /* HMT not supported */
1825 bl .hmt_start_secondary
1829 /* The following gets the stack and TOC set up with the regs */
1830 /* pointing to the real addr of the kernel stack. This is */
1831 /* all done to support the C function call below which sets */
1832 /* up the htab. This is done because we have relocated the */
1833 /* kernel but are still running in real mode. */
1835 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1838 /* set up a stack pointer (physical address) */
1839 addi r1,r3,THREAD_SIZE
1841 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1843 /* set up the TOC (physical address) */
1844 LOAD_REG_IMMEDIATE(r2,__toc_start)
1849 LOAD_REG_IMMEDIATE(r3, cpu_specs)
1851 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1856 /* Save some low level config HIDs of CPU0 to be copied to
1857 * other CPUs later on, or used for suspend/resume
1859 bl .__save_cpu_setup
1862 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1863 * note that boot_cpuid can always be 0 nowadays since there is
1864 * nowhere it can be initialized differently before we reach this
1867 LOAD_REG_IMMEDIATE(r27, boot_cpuid)
1871 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
1872 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1873 add r13,r13,r24 /* for this processor. */
1874 add r13,r13,r26 /* convert to physical addr */
1875 mtspr SPRN_SPRG3,r13
1877 /* Do very early kernel initializations, including initial hash table,
1878 * stab and slb setup before we turn on relocation. */
1880 /* Restore parameters passed from prom_init/kexec */
1884 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1885 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1889 b . /* prevent speculative execution */
1890 #endif /* CONFIG_PPC_MULTIPLATFORM */
1892 /* This is where all platforms converge execution */
1893 _STATIC(start_here_common)
1894 /* relocation is on at this point */
1896 /* The following code sets up the SP and TOC now that we are */
1897 /* running with translation enabled. */
1899 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1901 /* set up the stack */
1902 addi r1,r3,THREAD_SIZE
1904 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1906 /* Apply the CPUs-specific fixups (nop out sections not relevant
1910 bl .do_cpu_ftr_fixups
1912 LOAD_REG_IMMEDIATE(r26, boot_cpuid)
1915 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
1916 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1917 add r13,r13,r24 /* for this processor. */
1918 mtspr SPRN_SPRG3,r13
1920 /* ptr to current */
1921 LOAD_REG_IMMEDIATE(r4, init_task)
1922 std r4,PACACURRENT(r13)
1926 std r1,PACAKSAVE(r13)
1930 /* Load up the kernel context */
1932 #ifdef DO_SOFT_DISABLE
1934 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1936 ori r5,r5,MSR_EE /* Hard Enabled */
1944 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
1947 cmpwi r7,0x34 /* Pulsar */
1949 cmpwi r7,0x36 /* Icestar */
1951 cmpwi r7,0x37 /* SStar */
1954 90: mfspr r6,SPRN_PIR
1957 91: mfspr r6,SPRN_PIR
1961 bl .hmt_start_secondary
1964 __hmt_secondary_hold:
1965 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
1975 93: andi. r6,r6,0x3f
1989 b .pSeries_secondary_smp_init
1992 _GLOBAL(hmt_start_secondary)
1993 LOAD_REG_IMMEDIATE(r4,__hmt_secondary_hold)
1995 mtspr SPRN_NIADORM, r4
1996 mfspr r4, SPRN_MSRDORM
1999 mtspr SPRN_MSRDORM, r4
2008 mfspr r4, SPRN_CTRLF
2010 mtspr SPRN_CTRLT, r4
2015 * We put a few things here that have to be page-aligned.
2016 * This stuff goes at the beginning of the bss, which is page-aligned.
2022 .globl empty_zero_page
2026 .globl swapper_pg_dir
2031 * This space gets a copy of optional info passed to us by the bootstrap
2032 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2036 .space COMMAND_LINE_SIZE