3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/config.h>
23 #include <linux/errno.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
36 #undef SHOW_SYSCALLS_TASK
39 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
41 #if MSR_KERNEL >= 0x10000
42 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
44 #define LOAD_MSR_KERNEL(r, x) li r,(x)
48 #include "head_booke.h"
49 #define TRANSFER_TO_HANDLER_EXC_LEVEL(exc_level) \
50 mtspr exc_level##_SPRG,r8; \
51 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level); \
52 lwz r0,GPR10-INT_FRAME_SIZE(r8); \
54 lwz r0,GPR11-INT_FRAME_SIZE(r8); \
56 mfspr r8,exc_level##_SPRG
58 .globl mcheck_transfer_to_handler
59 mcheck_transfer_to_handler:
60 TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK)
61 b transfer_to_handler_full
63 .globl debug_transfer_to_handler
64 debug_transfer_to_handler:
65 TRANSFER_TO_HANDLER_EXC_LEVEL(DEBUG)
66 b transfer_to_handler_full
68 .globl crit_transfer_to_handler
69 crit_transfer_to_handler:
70 TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT)
75 .globl crit_transfer_to_handler
76 crit_transfer_to_handler:
85 * This code finishes saving the registers to the exception frame
86 * and jumps to the appropriate handler for the exception, turning
87 * on address translation.
88 * Note that we rely on the caller having set cr0.eq iff the exception
89 * occurred in kernel mode (i.e. MSR:PR = 0).
91 .globl transfer_to_handler_full
92 transfer_to_handler_full:
96 .globl transfer_to_handler
108 tovirt(r2,r2) /* set r2 to current */
109 beq 2f /* if from user, fix up THREAD.regs */
110 addi r11,r1,STACK_FRAME_OVERHEAD
112 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
113 /* Check to see if the dbcr0 register is set up to debug. Use the
114 single-step bit to do this. */
115 lwz r12,THREAD_DBCR0(r12)
116 andis. r12,r12,DBCR0_IC@h
118 /* From user and task is ptraced - load up global dbcr0 */
119 li r12,-1 /* clear all pending debug events */
121 lis r11,global_dbcr0@ha
123 addi r11,r11,global_dbcr0@l
131 2: /* if from kernel, check interrupted DOZE/NAP mode and
132 * check for stack overflow
138 bt- 8,4f /* Check DOZE */
139 END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
141 bt- 9,4f /* Check NAP */
142 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
143 #endif /* CONFIG_6xx */
144 .globl transfer_to_handler_cont
145 transfer_to_handler_cont:
146 lwz r11,THREAD_INFO-THREAD(r12)
147 cmplw r1,r11 /* if r1 <= current->thread_info */
148 ble- stack_ovf /* then the kernel stack overflowed */
151 lwz r11,0(r9) /* virtual address of handler */
152 lwz r9,4(r9) /* where to go when done */
158 RFI /* jump to handler, enable MMU */
161 4: b power_save_6xx_restore
165 * On kernel stack overflow, load up an initial stack pointer
166 * and call StackOverflow(regs), which should not return.
169 /* sometimes we use a statically-allocated stack, which is OK. */
173 ble 3b /* r1 <= &_end is OK */
175 addi r3,r1,STACK_FRAME_OVERHEAD
176 lis r1,init_thread_union@ha
177 addi r1,r1,init_thread_union@l
178 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
179 lis r9,StackOverflow@ha
180 addi r9,r9,StackOverflow@l
181 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
189 * Handle a system call.
191 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
192 .stabs "entry_32.S",N_SO,0,0,0f
196 stw r0,THREAD+LAST_SYSCALL(r2)
200 lwz r11,_CCR(r1) /* Clear SO bit in CR */
205 #endif /* SHOW_SYSCALLS */
206 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
207 lwz r11,TI_FLAGS(r10)
208 andi. r11,r11,_TIF_SYSCALL_T_OR_A
210 syscall_dotrace_cont:
211 cmplwi 0,r0,NR_syscalls
212 lis r10,sys_call_table@h
213 ori r10,r10,sys_call_table@l
216 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
218 addi r9,r1,STACK_FRAME_OVERHEAD
220 blrl /* Call handler */
221 .globl ret_from_syscall
224 bl do_show_syscall_exit
227 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
228 /* disable interrupts so current_thread_info()->flags can't change */
229 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
234 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
235 bne- syscall_exit_work
237 blt+ syscall_exit_cont
238 lwz r11,_CCR(r1) /* Load CR */
240 oris r11,r11,0x1000 /* Set SO bit in CR */
243 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
244 /* If the process has its own DBCR0 value, load it up. The single
245 step bit tells us that dbcr0 should be loaded. */
246 lwz r0,THREAD+THREAD_DBCR0(r2)
247 andis. r10,r0,DBCR0_IC@h
250 stwcx. r0,0,r1 /* to clear the reservation */
275 /* Traced system call support */
280 addi r3,r1,STACK_FRAME_OVERHEAD
281 bl do_syscall_trace_enter
282 lwz r0,GPR0(r1) /* Restore original registers */
290 b syscall_dotrace_cont
293 andi. r0,r9,_TIF_RESTOREALL
299 andi. r0,r9,_TIF_NOERROR
301 lwz r11,_CCR(r1) /* Load CR */
303 oris r11,r11,0x1000 /* Set SO bit in CR */
306 1: stw r6,RESULT(r1) /* Save result */
307 stw r3,GPR3(r1) /* Update return value */
308 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
311 /* Clear per-syscall TIF flags if any are set. */
313 li r11,_TIF_PERSYSCALL_MASK
314 addi r12,r12,TI_FLAGS
317 #ifdef CONFIG_IBM405_ERR77
322 subi r12,r12,TI_FLAGS
324 4: /* Anything which requires enabling interrupts? */
325 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
328 /* Re-enable interrupts */
333 /* Save NVGPRS if they're not saved already */
341 addi r3,r1,STACK_FRAME_OVERHEAD
342 bl do_syscall_trace_leave
343 b ret_from_except_full
347 #ifdef SHOW_SYSCALLS_TASK
348 lis r11,show_syscalls_task@ha
349 lwz r11,show_syscalls_task@l(r11)
380 do_show_syscall_exit:
381 #ifdef SHOW_SYSCALLS_TASK
382 lis r11,show_syscalls_task@ha
383 lwz r11,show_syscalls_task@l(r11)
389 stw r3,RESULT(r1) /* Save result */
399 7: .string "syscall %d(%x, %x, %x, %x, %x, "
400 77: .string "%x), current=%p\n"
401 79: .string " -> %x\n"
404 #ifdef SHOW_SYSCALLS_TASK
406 .globl show_syscalls_task
411 #endif /* SHOW_SYSCALLS */
414 * The fork/clone functions need to copy the full register set into
415 * the child process. Therefore we need to save all the nonvolatile
416 * registers (r13 - r31) before calling the C code.
422 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
423 stw r0,_TRAP(r1) /* register set saved */
430 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
431 stw r0,_TRAP(r1) /* register set saved */
438 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
439 stw r0,_TRAP(r1) /* register set saved */
442 .globl ppc_swapcontext
446 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
447 stw r0,_TRAP(r1) /* register set saved */
451 * Top-level page fault handling.
452 * This is in assembler because if do_page_fault tells us that
453 * it is a bad kernel page fault, we want to save the non-volatile
454 * registers before calling bad_page_fault.
456 .globl handle_page_fault
459 addi r3,r1,STACK_FRAME_OVERHEAD
468 addi r3,r1,STACK_FRAME_OVERHEAD
471 b ret_from_except_full
474 * This routine switches between two different tasks. The process
475 * state of one is saved on its kernel stack. Then the state
476 * of the other is restored from its kernel stack. The memory
477 * management hardware is updated to the second process's state.
478 * Finally, we can return to the second process.
479 * On entry, r3 points to the THREAD for the current task, r4
480 * points to the THREAD for the new task.
482 * This routine is always called with interrupts disabled.
484 * Note: there are two ways to get to the "going out" portion
485 * of this code; either by coming in via the entry (_switch)
486 * or via "fork" which must set up an environment equivalent
487 * to the "_switch" path. If you change this , you'll have to
488 * change the fork code also.
490 * The code which creates the new task context is in 'copy_thread'
491 * in arch/ppc/kernel/process.c
494 stwu r1,-INT_FRAME_SIZE(r1)
496 stw r0,INT_FRAME_SIZE+4(r1)
497 /* r3-r12 are caller saved -- Cort */
499 stw r0,_NIP(r1) /* Return to switch caller */
501 li r0,MSR_FP /* Disable floating-point */
502 #ifdef CONFIG_ALTIVEC
504 oris r0,r0,MSR_VEC@h /* Disable altivec */
505 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
506 stw r12,THREAD+THREAD_VRSAVE(r2)
507 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
508 #endif /* CONFIG_ALTIVEC */
510 oris r0,r0,MSR_SPE@h /* Disable SPE */
511 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
512 stw r12,THREAD+THREAD_SPEFSCR(r2)
513 #endif /* CONFIG_SPE */
514 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
522 stw r1,KSP(r3) /* Set old stack pointer */
525 /* We need a sync somewhere here to make sure that if the
526 * previous task gets rescheduled on another CPU, it sees all
527 * stores it has performed on this one.
530 #endif /* CONFIG_SMP */
534 mtspr SPRN_SPRG3,r0 /* Update current THREAD phys addr */
535 lwz r1,KSP(r4) /* Load new stack pointer */
537 /* save the old current 'last' for return value */
539 addi r2,r4,-THREAD /* Update current */
541 #ifdef CONFIG_ALTIVEC
543 lwz r0,THREAD+THREAD_VRSAVE(r2)
544 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
545 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
546 #endif /* CONFIG_ALTIVEC */
548 lwz r0,THREAD+THREAD_SPEFSCR(r2)
549 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
550 #endif /* CONFIG_SPE */
554 /* r3-r12 are destroyed -- Cort */
557 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
559 addi r1,r1,INT_FRAME_SIZE
562 .globl fast_exception_return
563 fast_exception_return:
564 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
565 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
566 beq 1f /* if not, we've got problems */
569 2: REST_4GPRS(3, r11)
584 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
585 /* check if the exception happened in a restartable section */
586 1: lis r3,exc_exit_restart_end@ha
587 addi r3,r3,exc_exit_restart_end@l
590 lis r4,exc_exit_restart@ha
591 addi r4,r4,exc_exit_restart@l
594 lis r3,fee_restarts@ha
596 lwz r5,fee_restarts@l(r3)
598 stw r5,fee_restarts@l(r3)
599 mr r12,r4 /* restart at exc_exit_restart */
604 /* aargh, a nonrecoverable interrupt, panic */
605 /* aargh, we don't know which trap this is */
606 /* but the 601 doesn't implement the RI bit, so assume it's OK */
610 END_FTR_SECTION_IFSET(CPU_FTR_601)
613 addi r3,r1,STACK_FRAME_OVERHEAD
615 ori r10,r10,MSR_KERNEL@l
616 bl transfer_to_handler_full
617 .long nonrecoverable_exception
618 .long ret_from_except
621 .globl ret_from_except_full
622 ret_from_except_full:
626 .globl ret_from_except
628 /* Hard-disable interrupts so that current_thread_info()->flags
629 * can't change between when we test it and when we return
630 * from the interrupt. */
631 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
632 SYNC /* Some chip revs have problems here... */
633 MTMSRD(r10) /* disable interrupts */
635 lwz r3,_MSR(r1) /* Returning to user mode? */
639 user_exc_return: /* r10 contains MSR_KERNEL here */
640 /* Check current_thread_info()->flags */
641 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
643 andi. r0,r9,(_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK|_TIF_NEED_RESCHED)
647 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
648 /* Check whether this process has its own DBCR0 value. The single
649 step bit tells us that dbcr0 should be loaded. */
650 lwz r0,THREAD+THREAD_DBCR0(r2)
651 andis. r10,r0,DBCR0_IC@h
655 #ifdef CONFIG_PREEMPT
658 /* N.B. the only way to get here is from the beq following ret_from_except. */
660 /* check current_thread_info->preempt_count */
661 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
662 lwz r0,TI_PREEMPT(r9)
663 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
666 andi. r0,r0,_TIF_NEED_RESCHED
668 andi. r0,r3,MSR_EE /* interrupts off? */
669 beq restore /* don't schedule if so */
670 1: bl preempt_schedule_irq
671 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
673 andi. r0,r3,_TIF_NEED_RESCHED
677 #endif /* CONFIG_PREEMPT */
679 /* interrupts are hard-disabled at this point */
692 stwcx. r0,0,r1 /* to clear the reservation */
694 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
696 andi. r10,r9,MSR_RI /* check if this exception occurred */
697 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
705 * Once we put values in SRR0 and SRR1, we are in a state
706 * where exceptions are not recoverable, since taking an
707 * exception will trash SRR0 and SRR1. Therefore we clear the
708 * MSR:RI bit to indicate this. If we do take an exception,
709 * we can't return to the point of the exception but we
710 * can restart the exception exit path at the label
711 * exc_exit_restart below. -- paulus
713 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
715 MTMSRD(r10) /* clear the RI bit */
716 .globl exc_exit_restart
725 .globl exc_exit_restart_end
726 exc_exit_restart_end:
730 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
732 * This is a bit different on 4xx/Book-E because it doesn't have
733 * the RI bit in the MSR.
734 * The TLB miss handler checks if we have interrupted
735 * the exception exit path and restarts it if so
736 * (well maybe one day it will... :).
743 .globl exc_exit_restart
752 .globl exc_exit_restart_end
753 exc_exit_restart_end:
756 b . /* prevent prefetch past rfi */
759 * Returning from a critical interrupt in user mode doesn't need
760 * to be any different from a normal exception. For a critical
761 * interrupt in the kernel, we just return (without checking for
762 * preemption) since the interrupt may have happened at some crucial
763 * place (e.g. inside the TLB miss handler), and because we will be
764 * running with r1 pointing into critical_stack, not the current
765 * process's kernel stack (and therefore current_thread_info() will
766 * give the wrong answer).
767 * We have to restore various SPRs that may have been in use at the
768 * time of the critical interrupt.
772 #define PPC_40x_TURN_OFF_MSR_DR \
773 /* avoid any possible TLB misses here by turning off MSR.DR, we \
774 * assume the instructions here are mapped by a pinned TLB entry */ \
780 #define PPC_40x_TURN_OFF_MSR_DR
783 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
786 andi. r3,r3,MSR_PR; \
787 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
788 bne user_exc_return; \
795 mtspr SPRN_XER,r10; \
797 PPC405_ERR77(0,r1); \
798 stwcx. r0,0,r1; /* to clear the reservation */ \
803 PPC_40x_TURN_OFF_MSR_DR; \
806 mtspr SPRN_DEAR,r9; \
807 mtspr SPRN_ESR,r10; \
810 mtspr exc_lvl_srr0,r11; \
811 mtspr exc_lvl_srr1,r12; \
819 b .; /* prevent prefetch past exc_lvl_rfi */
821 .globl ret_from_crit_exc
823 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI)
826 .globl ret_from_debug_exc
828 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI)
830 .globl ret_from_mcheck_exc
832 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI)
833 #endif /* CONFIG_BOOKE */
836 * Load the DBCR0 value for a task that is being ptraced,
837 * having first saved away the global DBCR0. Note that r0
838 * has the dbcr0 value to set upon entry to this.
841 mfmsr r10 /* first disable debug exceptions */
842 rlwinm r10,r10,0,~MSR_DE
846 lis r11,global_dbcr0@ha
847 addi r11,r11,global_dbcr0@l
854 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
858 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
860 do_work: /* r10 contains MSR_KERNEL here */
861 andi. r0,r9,_TIF_NEED_RESCHED
864 do_resched: /* r10 contains MSR_KERNEL here */
867 MTMSRD(r10) /* hard-enable interrupts */
870 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
872 MTMSRD(r10) /* disable interrupts */
873 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
875 andi. r0,r9,_TIF_NEED_RESCHED
877 andi. r0,r9,_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK
879 do_user_signal: /* r10 contains MSR_KERNEL here */
882 MTMSRD(r10) /* hard-enable interrupts */
883 /* save r13-r31 in the exception frame, if not already done */
891 addi r4,r1,STACK_FRAME_OVERHEAD
897 * We come here when we are at the end of handling an exception
898 * that occurred at a place where taking an exception will lose
899 * state information, such as the contents of SRR0 and SRR1.
902 lis r10,exc_exit_restart_end@ha
903 addi r10,r10,exc_exit_restart_end@l
906 lis r11,exc_exit_restart@ha
907 addi r11,r11,exc_exit_restart@l
910 lis r10,ee_restarts@ha
911 lwz r12,ee_restarts@l(r10)
913 stw r12,ee_restarts@l(r10)
914 mr r12,r11 /* restart at exc_exit_restart */
916 3: /* OK, we can't recover, kill this process */
917 /* but the 601 doesn't implement the RI bit, so assume it's OK */
920 END_FTR_SECTION_IFSET(CPU_FTR_601)
927 4: addi r3,r1,STACK_FRAME_OVERHEAD
928 bl nonrecoverable_exception
929 /* shouldn't return */
935 * PROM code for specific machines follows. Put it
936 * here so it's easy to add arch-specific sections later.
939 #ifdef CONFIG_PPC_RTAS
941 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
942 * called with the MMU off.
945 stwu r1,-INT_FRAME_SIZE(r1)
947 stw r0,INT_FRAME_SIZE+4(r1)
948 LOAD_REG_ADDR(r4, rtas)
949 lis r6,1f@ha /* physical return address for rtas */
957 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
958 SYNC /* disable interrupts so SRR0/1 */
959 MTMSRD(r0) /* don't get trashed */
960 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
967 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
968 lwz r9,8(r9) /* original msr value */
970 addi r1,r1,INT_FRAME_SIZE
975 RFI /* return to caller */
977 .globl machine_check_in_rtas
978 machine_check_in_rtas:
980 /* XXX load up BATs and panic */
982 #endif /* CONFIG_PPC_RTAS */