3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/sys.h>
24 #include <linux/threads.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/unistd.h>
35 #undef SHOW_SYSCALLS_TASK
38 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
40 #if MSR_KERNEL >= 0x10000
41 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
43 #define LOAD_MSR_KERNEL(r, x) li r,(x)
47 #include "head_booke.h"
48 #define TRANSFER_TO_HANDLER_EXC_LEVEL(exc_level) \
49 mtspr exc_level##_SPRG,r8; \
50 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level); \
51 lwz r0,GPR10-INT_FRAME_SIZE(r8); \
53 lwz r0,GPR11-INT_FRAME_SIZE(r8); \
55 mfspr r8,exc_level##_SPRG
57 .globl mcheck_transfer_to_handler
58 mcheck_transfer_to_handler:
59 TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK)
60 b transfer_to_handler_full
62 .globl debug_transfer_to_handler
63 debug_transfer_to_handler:
64 TRANSFER_TO_HANDLER_EXC_LEVEL(DEBUG)
65 b transfer_to_handler_full
67 .globl crit_transfer_to_handler
68 crit_transfer_to_handler:
69 TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT)
74 .globl crit_transfer_to_handler
75 crit_transfer_to_handler:
84 * This code finishes saving the registers to the exception frame
85 * and jumps to the appropriate handler for the exception, turning
86 * on address translation.
87 * Note that we rely on the caller having set cr0.eq iff the exception
88 * occurred in kernel mode (i.e. MSR:PR = 0).
90 .globl transfer_to_handler_full
91 transfer_to_handler_full:
95 .globl transfer_to_handler
107 tovirt(r2,r2) /* set r2 to current */
108 beq 2f /* if from user, fix up THREAD.regs */
109 addi r11,r1,STACK_FRAME_OVERHEAD
111 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
112 /* Check to see if the dbcr0 register is set up to debug. Use the
113 internal debug mode bit to do this. */
114 lwz r12,THREAD_DBCR0(r12)
115 andis. r12,r12,DBCR0_IDM@h
117 /* From user and task is ptraced - load up global dbcr0 */
118 li r12,-1 /* clear all pending debug events */
120 lis r11,global_dbcr0@ha
122 addi r11,r11,global_dbcr0@l
124 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
137 2: /* if from kernel, check interrupted DOZE/NAP mode and
138 * check for stack overflow
140 lwz r9,KSP_LIMIT(r12)
141 cmplw r1,r9 /* if r1 <= ksp_limit */
142 ble- stack_ovf /* then the kernel stack overflowed */
145 rlwinm r9,r1,0,0,31-THREAD_SHIFT
146 tophys(r9,r9) /* check local flags */
147 lwz r12,TI_LOCAL_FLAGS(r9)
149 bt- 31-TLF_NAPPING,4f
150 bt- 31-TLF_SLEEPING,7f
151 #endif /* CONFIG_6xx */
152 .globl transfer_to_handler_cont
153 transfer_to_handler_cont:
156 lwz r11,0(r9) /* virtual address of handler */
157 lwz r9,4(r9) /* where to go when done */
162 RFI /* jump to handler, enable MMU */
165 4: rlwinm r12,r12,0,~_TLF_NAPPING
166 stw r12,TI_LOCAL_FLAGS(r9)
167 b power_save_6xx_restore
169 7: rlwinm r12,r12,0,~_TLF_SLEEPING
170 stw r12,TI_LOCAL_FLAGS(r9)
171 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
172 rlwinm r9,r9,0,~MSR_EE
173 lwz r12,_LINK(r11) /* and return to address in LR */
174 b fast_exception_return
178 * On kernel stack overflow, load up an initial stack pointer
179 * and call StackOverflow(regs), which should not return.
182 /* sometimes we use a statically-allocated stack, which is OK. */
186 ble 5b /* r1 <= &_end is OK */
188 addi r3,r1,STACK_FRAME_OVERHEAD
189 lis r1,init_thread_union@ha
190 addi r1,r1,init_thread_union@l
191 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
192 lis r9,StackOverflow@ha
193 addi r9,r9,StackOverflow@l
194 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
202 * Handle a system call.
204 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
205 .stabs "entry_32.S",N_SO,0,0,0f
212 lwz r11,_CCR(r1) /* Clear SO bit in CR */
217 #endif /* SHOW_SYSCALLS */
218 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
219 lwz r11,TI_FLAGS(r10)
220 andi. r11,r11,_TIF_SYSCALL_T_OR_A
222 syscall_dotrace_cont:
223 cmplwi 0,r0,NR_syscalls
224 lis r10,sys_call_table@h
225 ori r10,r10,sys_call_table@l
228 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
230 addi r9,r1,STACK_FRAME_OVERHEAD
232 blrl /* Call handler */
233 .globl ret_from_syscall
236 bl do_show_syscall_exit
239 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
240 /* disable interrupts so current_thread_info()->flags can't change */
241 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
246 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
247 bne- syscall_exit_work
249 blt+ syscall_exit_cont
250 lwz r11,_CCR(r1) /* Load CR */
252 oris r11,r11,0x1000 /* Set SO bit in CR */
255 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
256 /* If the process has its own DBCR0 value, load it up. The internal
257 debug mode bit tells us that dbcr0 should be loaded. */
258 lwz r0,THREAD+THREAD_DBCR0(r2)
259 andis. r10,r0,DBCR0_IDM@h
263 lis r4,icache_44x_need_flush@ha
264 lwz r5,icache_44x_need_flush@l(r4)
268 #endif /* CONFIG_44x */
271 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
272 stwcx. r0,0,r1 /* to clear the reservation */
289 stw r7,icache_44x_need_flush@l(r4)
291 #endif /* CONFIG_44x */
303 /* Traced system call support */
308 addi r3,r1,STACK_FRAME_OVERHEAD
309 bl do_syscall_trace_enter
310 lwz r0,GPR0(r1) /* Restore original registers */
318 b syscall_dotrace_cont
321 andi. r0,r9,_TIF_RESTOREALL
327 andi. r0,r9,_TIF_NOERROR
329 lwz r11,_CCR(r1) /* Load CR */
331 oris r11,r11,0x1000 /* Set SO bit in CR */
334 1: stw r6,RESULT(r1) /* Save result */
335 stw r3,GPR3(r1) /* Update return value */
336 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
339 /* Clear per-syscall TIF flags if any are set. */
341 li r11,_TIF_PERSYSCALL_MASK
342 addi r12,r12,TI_FLAGS
345 #ifdef CONFIG_IBM405_ERR77
350 subi r12,r12,TI_FLAGS
352 4: /* Anything which requires enabling interrupts? */
353 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
356 /* Re-enable interrupts */
361 /* Save NVGPRS if they're not saved already */
369 addi r3,r1,STACK_FRAME_OVERHEAD
370 bl do_syscall_trace_leave
371 b ret_from_except_full
375 #ifdef SHOW_SYSCALLS_TASK
376 lis r11,show_syscalls_task@ha
377 lwz r11,show_syscalls_task@l(r11)
408 do_show_syscall_exit:
409 #ifdef SHOW_SYSCALLS_TASK
410 lis r11,show_syscalls_task@ha
411 lwz r11,show_syscalls_task@l(r11)
417 stw r3,RESULT(r1) /* Save result */
427 7: .string "syscall %d(%x, %x, %x, %x, %x, "
428 77: .string "%x), current=%p\n"
429 79: .string " -> %x\n"
432 #ifdef SHOW_SYSCALLS_TASK
434 .globl show_syscalls_task
439 #endif /* SHOW_SYSCALLS */
442 * The fork/clone functions need to copy the full register set into
443 * the child process. Therefore we need to save all the nonvolatile
444 * registers (r13 - r31) before calling the C code.
450 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
451 stw r0,_TRAP(r1) /* register set saved */
458 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
459 stw r0,_TRAP(r1) /* register set saved */
466 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
467 stw r0,_TRAP(r1) /* register set saved */
470 .globl ppc_swapcontext
474 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
475 stw r0,_TRAP(r1) /* register set saved */
479 * Top-level page fault handling.
480 * This is in assembler because if do_page_fault tells us that
481 * it is a bad kernel page fault, we want to save the non-volatile
482 * registers before calling bad_page_fault.
484 .globl handle_page_fault
487 addi r3,r1,STACK_FRAME_OVERHEAD
496 addi r3,r1,STACK_FRAME_OVERHEAD
499 b ret_from_except_full
502 * This routine switches between two different tasks. The process
503 * state of one is saved on its kernel stack. Then the state
504 * of the other is restored from its kernel stack. The memory
505 * management hardware is updated to the second process's state.
506 * Finally, we can return to the second process.
507 * On entry, r3 points to the THREAD for the current task, r4
508 * points to the THREAD for the new task.
510 * This routine is always called with interrupts disabled.
512 * Note: there are two ways to get to the "going out" portion
513 * of this code; either by coming in via the entry (_switch)
514 * or via "fork" which must set up an environment equivalent
515 * to the "_switch" path. If you change this , you'll have to
516 * change the fork code also.
518 * The code which creates the new task context is in 'copy_thread'
519 * in arch/ppc/kernel/process.c
522 stwu r1,-INT_FRAME_SIZE(r1)
524 stw r0,INT_FRAME_SIZE+4(r1)
525 /* r3-r12 are caller saved -- Cort */
527 stw r0,_NIP(r1) /* Return to switch caller */
529 li r0,MSR_FP /* Disable floating-point */
530 #ifdef CONFIG_ALTIVEC
532 oris r0,r0,MSR_VEC@h /* Disable altivec */
533 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
534 stw r12,THREAD+THREAD_VRSAVE(r2)
535 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
536 #endif /* CONFIG_ALTIVEC */
539 oris r0,r0,MSR_SPE@h /* Disable SPE */
540 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
541 stw r12,THREAD+THREAD_SPEFSCR(r2)
542 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
543 #endif /* CONFIG_SPE */
544 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
552 stw r1,KSP(r3) /* Set old stack pointer */
555 /* We need a sync somewhere here to make sure that if the
556 * previous task gets rescheduled on another CPU, it sees all
557 * stores it has performed on this one.
560 #endif /* CONFIG_SMP */
564 mtspr SPRN_SPRG3,r0 /* Update current THREAD phys addr */
565 lwz r1,KSP(r4) /* Load new stack pointer */
567 /* save the old current 'last' for return value */
569 addi r2,r4,-THREAD /* Update current */
571 #ifdef CONFIG_ALTIVEC
573 lwz r0,THREAD+THREAD_VRSAVE(r2)
574 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
575 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
576 #endif /* CONFIG_ALTIVEC */
579 lwz r0,THREAD+THREAD_SPEFSCR(r2)
580 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
581 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
582 #endif /* CONFIG_SPE */
586 /* r3-r12 are destroyed -- Cort */
589 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
591 addi r1,r1,INT_FRAME_SIZE
594 .globl fast_exception_return
595 fast_exception_return:
596 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
597 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
598 beq 1f /* if not, we've got problems */
601 2: REST_4GPRS(3, r11)
616 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
617 /* check if the exception happened in a restartable section */
618 1: lis r3,exc_exit_restart_end@ha
619 addi r3,r3,exc_exit_restart_end@l
622 lis r4,exc_exit_restart@ha
623 addi r4,r4,exc_exit_restart@l
626 lis r3,fee_restarts@ha
628 lwz r5,fee_restarts@l(r3)
630 stw r5,fee_restarts@l(r3)
631 mr r12,r4 /* restart at exc_exit_restart */
640 /* aargh, a nonrecoverable interrupt, panic */
641 /* aargh, we don't know which trap this is */
642 /* but the 601 doesn't implement the RI bit, so assume it's OK */
646 END_FTR_SECTION_IFSET(CPU_FTR_601)
649 addi r3,r1,STACK_FRAME_OVERHEAD
651 ori r10,r10,MSR_KERNEL@l
652 bl transfer_to_handler_full
653 .long nonrecoverable_exception
654 .long ret_from_except
657 .globl ret_from_except_full
658 ret_from_except_full:
662 .globl ret_from_except
664 /* Hard-disable interrupts so that current_thread_info()->flags
665 * can't change between when we test it and when we return
666 * from the interrupt. */
667 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
668 SYNC /* Some chip revs have problems here... */
669 MTMSRD(r10) /* disable interrupts */
671 lwz r3,_MSR(r1) /* Returning to user mode? */
675 user_exc_return: /* r10 contains MSR_KERNEL here */
676 /* Check current_thread_info()->flags */
677 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
679 andi. r0,r9,_TIF_USER_WORK_MASK
683 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
684 /* Check whether this process has its own DBCR0 value. The internal
685 debug mode bit tells us that dbcr0 should be loaded. */
686 lwz r0,THREAD+THREAD_DBCR0(r2)
687 andis. r10,r0,DBCR0_IDM@h
691 #ifdef CONFIG_PREEMPT
694 /* N.B. the only way to get here is from the beq following ret_from_except. */
696 /* check current_thread_info->preempt_count */
697 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
698 lwz r0,TI_PREEMPT(r9)
699 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
702 andi. r0,r0,_TIF_NEED_RESCHED
704 andi. r0,r3,MSR_EE /* interrupts off? */
705 beq restore /* don't schedule if so */
706 1: bl preempt_schedule_irq
707 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
709 andi. r0,r3,_TIF_NEED_RESCHED
713 #endif /* CONFIG_PREEMPT */
715 /* interrupts are hard-disabled at this point */
718 lis r4,icache_44x_need_flush@ha
719 lwz r5,icache_44x_need_flush@l(r4)
724 stw r6,icache_44x_need_flush@l(r4)
726 #endif /* CONFIG_44x */
740 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
741 stwcx. r0,0,r1 /* to clear the reservation */
743 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
745 andi. r10,r9,MSR_RI /* check if this exception occurred */
746 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
754 * Once we put values in SRR0 and SRR1, we are in a state
755 * where exceptions are not recoverable, since taking an
756 * exception will trash SRR0 and SRR1. Therefore we clear the
757 * MSR:RI bit to indicate this. If we do take an exception,
758 * we can't return to the point of the exception but we
759 * can restart the exception exit path at the label
760 * exc_exit_restart below. -- paulus
762 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
764 MTMSRD(r10) /* clear the RI bit */
765 .globl exc_exit_restart
774 .globl exc_exit_restart_end
775 exc_exit_restart_end:
779 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
781 * This is a bit different on 4xx/Book-E because it doesn't have
782 * the RI bit in the MSR.
783 * The TLB miss handler checks if we have interrupted
784 * the exception exit path and restarts it if so
785 * (well maybe one day it will... :).
792 .globl exc_exit_restart
801 .globl exc_exit_restart_end
802 exc_exit_restart_end:
805 b . /* prevent prefetch past rfi */
808 * Returning from a critical interrupt in user mode doesn't need
809 * to be any different from a normal exception. For a critical
810 * interrupt in the kernel, we just return (without checking for
811 * preemption) since the interrupt may have happened at some crucial
812 * place (e.g. inside the TLB miss handler), and because we will be
813 * running with r1 pointing into critical_stack, not the current
814 * process's kernel stack (and therefore current_thread_info() will
815 * give the wrong answer).
816 * We have to restore various SPRs that may have been in use at the
817 * time of the critical interrupt.
821 #define PPC_40x_TURN_OFF_MSR_DR \
822 /* avoid any possible TLB misses here by turning off MSR.DR, we \
823 * assume the instructions here are mapped by a pinned TLB entry */ \
829 #define PPC_40x_TURN_OFF_MSR_DR
832 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
835 andi. r3,r3,MSR_PR; \
836 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
837 bne user_exc_return; \
844 mtspr SPRN_XER,r10; \
846 PPC405_ERR77(0,r1); \
847 stwcx. r0,0,r1; /* to clear the reservation */ \
852 PPC_40x_TURN_OFF_MSR_DR; \
855 mtspr SPRN_DEAR,r9; \
856 mtspr SPRN_ESR,r10; \
859 mtspr exc_lvl_srr0,r11; \
860 mtspr exc_lvl_srr1,r12; \
868 b .; /* prevent prefetch past exc_lvl_rfi */
870 .globl ret_from_crit_exc
872 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI)
875 .globl ret_from_debug_exc
877 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI)
879 .globl ret_from_mcheck_exc
881 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI)
882 #endif /* CONFIG_BOOKE */
885 * Load the DBCR0 value for a task that is being ptraced,
886 * having first saved away the global DBCR0. Note that r0
887 * has the dbcr0 value to set upon entry to this.
890 mfmsr r10 /* first disable debug exceptions */
891 rlwinm r10,r10,0,~MSR_DE
895 lis r11,global_dbcr0@ha
896 addi r11,r11,global_dbcr0@l
898 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
909 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
917 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
919 do_work: /* r10 contains MSR_KERNEL here */
920 andi. r0,r9,_TIF_NEED_RESCHED
923 do_resched: /* r10 contains MSR_KERNEL here */
926 MTMSRD(r10) /* hard-enable interrupts */
929 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
931 MTMSRD(r10) /* disable interrupts */
932 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
934 andi. r0,r9,_TIF_NEED_RESCHED
936 andi. r0,r9,_TIF_USER_WORK_MASK
938 do_user_signal: /* r10 contains MSR_KERNEL here */
941 MTMSRD(r10) /* hard-enable interrupts */
942 /* save r13-r31 in the exception frame, if not already done */
950 addi r4,r1,STACK_FRAME_OVERHEAD
956 * We come here when we are at the end of handling an exception
957 * that occurred at a place where taking an exception will lose
958 * state information, such as the contents of SRR0 and SRR1.
961 lis r10,exc_exit_restart_end@ha
962 addi r10,r10,exc_exit_restart_end@l
965 lis r11,exc_exit_restart@ha
966 addi r11,r11,exc_exit_restart@l
969 lis r10,ee_restarts@ha
970 lwz r12,ee_restarts@l(r10)
972 stw r12,ee_restarts@l(r10)
973 mr r12,r11 /* restart at exc_exit_restart */
975 3: /* OK, we can't recover, kill this process */
976 /* but the 601 doesn't implement the RI bit, so assume it's OK */
979 END_FTR_SECTION_IFSET(CPU_FTR_601)
986 4: addi r3,r1,STACK_FRAME_OVERHEAD
987 bl nonrecoverable_exception
988 /* shouldn't return */
998 * PROM code for specific machines follows. Put it
999 * here so it's easy to add arch-specific sections later.
1002 #ifdef CONFIG_PPC_RTAS
1004 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1005 * called with the MMU off.
1008 stwu r1,-INT_FRAME_SIZE(r1)
1010 stw r0,INT_FRAME_SIZE+4(r1)
1011 LOAD_REG_ADDR(r4, rtas)
1012 lis r6,1f@ha /* physical return address for rtas */
1016 lwz r8,RTASENTRY(r4)
1020 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1021 SYNC /* disable interrupts so SRR0/1 */
1022 MTMSRD(r0) /* don't get trashed */
1023 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1030 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1031 lwz r9,8(r9) /* original msr value */
1033 addi r1,r1,INT_FRAME_SIZE
1038 RFI /* return to caller */
1040 .globl machine_check_in_rtas
1041 machine_check_in_rtas:
1043 /* XXX load up BATs and panic */
1045 #endif /* CONFIG_PPC_RTAS */