2 * TQM8548 Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR
60 compatible = "fsl,mpc8548-immr", "simple-bus";
62 memory-controller@2000 {
63 compatible = "fsl,mpc8548-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,mpc8548-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; // 32 bytes
73 cache-size = <0x80000>; // L2, 512K
74 interrupt-parent = <&mpic>;
82 compatible = "fsl-i2c";
85 interrupt-parent = <&mpic>;
89 compatible = "dallas,ds1337";
98 compatible = "fsl-i2c";
101 interrupt-parent = <&mpic>;
106 #address-cells = <1>;
108 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
110 ranges = <0x0 0x21100 0x200>;
113 compatible = "fsl,mpc8548-dma-channel",
114 "fsl,eloplus-dma-channel";
117 interrupt-parent = <&mpic>;
121 compatible = "fsl,mpc8548-dma-channel",
122 "fsl,eloplus-dma-channel";
125 interrupt-parent = <&mpic>;
129 compatible = "fsl,mpc8548-dma-channel",
130 "fsl,eloplus-dma-channel";
133 interrupt-parent = <&mpic>;
137 compatible = "fsl,mpc8548-dma-channel",
138 "fsl,eloplus-dma-channel";
141 interrupt-parent = <&mpic>;
147 #address-cells = <1>;
149 compatible = "fsl,gianfar-mdio";
150 reg = <0x24520 0x20>;
152 phy1: ethernet-phy@0 {
153 interrupt-parent = <&mpic>;
156 device_type = "ethernet-phy";
158 phy2: ethernet-phy@1 {
159 interrupt-parent = <&mpic>;
162 device_type = "ethernet-phy";
164 phy3: ethernet-phy@3 {
165 interrupt-parent = <&mpic>;
168 device_type = "ethernet-phy";
170 phy4: ethernet-phy@4 {
171 interrupt-parent = <&mpic>;
174 device_type = "ethernet-phy";
176 phy5: ethernet-phy@5 {
177 interrupt-parent = <&mpic>;
180 device_type = "ethernet-phy";
184 enet0: ethernet@24000 {
186 device_type = "network";
188 compatible = "gianfar";
189 reg = <0x24000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <29 2 30 2 34 2>;
192 interrupt-parent = <&mpic>;
193 phy-handle = <&phy2>;
196 enet1: ethernet@25000 {
198 device_type = "network";
200 compatible = "gianfar";
201 reg = <0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&mpic>;
205 phy-handle = <&phy1>;
208 enet2: ethernet@26000 {
210 device_type = "network";
212 compatible = "gianfar";
213 reg = <0x26000 0x1000>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <31 2 32 2 33 2>;
216 interrupt-parent = <&mpic>;
217 phy-handle = <&phy3>;
220 enet3: ethernet@27000 {
222 device_type = "network";
224 compatible = "gianfar";
225 reg = <0x27000 0x1000>;
226 local-mac-address = [ 00 00 00 00 00 00 ];
227 interrupts = <37 2 38 2 39 2>;
228 interrupt-parent = <&mpic>;
229 phy-handle = <&phy4>;
232 serial0: serial@4500 {
234 device_type = "serial";
235 compatible = "ns16550";
236 reg = <0x4500 0x100>; // reg base, size
237 clock-frequency = <0>; // should we fill in in uboot?
238 current-speed = <115200>;
240 interrupt-parent = <&mpic>;
243 serial1: serial@4600 {
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0x4600 0x100>; // reg base, size
248 clock-frequency = <0>; // should we fill in in uboot?
249 current-speed = <115200>;
251 interrupt-parent = <&mpic>;
254 global-utilities@e0000 { // global utilities reg
255 compatible = "fsl,mpc8548-guts";
256 reg = <0xe0000 0x1000>;
261 interrupt-controller;
262 #address-cells = <0>;
263 #interrupt-cells = <2>;
264 reg = <0x40000 0x40000>;
265 compatible = "chrp,open-pic";
266 device_type = "open-pic";
271 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
273 #address-cells = <2>;
275 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
278 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
279 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
280 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
281 3 0x0 0xe3010000 0x00008000 // NAND FLASH
286 #address-cells = <1>;
288 compatible = "cfi-flash";
289 reg = <1 0x0 0x8000000>;
295 reg = <0x00000000 0x00200000>;
299 reg = <0x00200000 0x00300000>;
303 reg = <0x00500000 0x07a00000>;
307 reg = <0x07f00000 0x00040000>;
311 reg = <0x07f40000 0x00040000>;
315 reg = <0x07f80000 0x00080000>;
320 /* Note: CAN support needs be enabled in U-Boot */
322 compatible = "intel,82527"; // Bosch CC770
325 interrupt-parent = <&mpic>;
329 compatible = "intel,82527"; // Bosch CC770
330 reg = <2 0x100 0x100>;
332 interrupt-parent = <&mpic>;
335 /* Note: NAND support needs to be enabled in U-Boot */
337 #address-cells = <0>;
339 compatible = "fsl,upm-nand";
341 fsl,upm-addr-offset = <0x10>;
342 fsl,upm-cmd-offset = <0x08>;
343 chip-delay = <25>; // in micro-seconds
346 #address-cells = <1>;
351 reg = <0x00000000 0x01000000>;
359 #interrupt-cells = <1>;
361 #address-cells = <3>;
362 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
364 reg = <0xe0008000 0x1000>;
365 clock-frequency = <33333333>;
366 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
369 0xe000 0 0 1 &mpic 2 1
370 0xe000 0 0 2 &mpic 3 1>;
372 interrupt-parent = <&mpic>;
375 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
376 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
379 pci1: pcie@e000a000 {
381 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
383 /* IDSEL 0x0 (PEX) */
384 0x00000 0 0 1 &mpic 0 1
385 0x00000 0 0 2 &mpic 1 1
386 0x00000 0 0 3 &mpic 2 1
387 0x00000 0 0 4 &mpic 3 1>;
389 interrupt-parent = <&mpic>;
391 bus-range = <0 0xff>;
392 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
393 0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
394 clock-frequency = <33333333>;
395 #interrupt-cells = <1>;
397 #address-cells = <3>;
398 reg = <0xe000a000 0x1000>;
399 compatible = "fsl,mpc8548-pcie";
404 #address-cells = <3>;
406 ranges = <0x02000000 0 0xc0000000 0x02000000 0
407 0xc0000000 0 0x20000000
408 0x01000000 0 0x00000000 0x01000000 0
409 0x00000000 0 0x08000000>;