err.no Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11
  12 / {
  13         model = "MPC8610HPCD";
  14         compatible = "fsl,MPC8610HPCD";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 serial0 = &serial0;
  20                 serial1 = &serial1;
  21                 pci0 = &pci0;
  22                 pci1 = &pci1;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 PowerPC,8610@0 {
  30                         device_type = "cpu";
  31                         reg = <0>;
  32                         d-cache-line-size = <d# 32>;    // bytes
  33                         i-cache-line-size = <d# 32>;    // bytes
  34                         d-cache-size = <8000>;          // L1, 32K
  35                         i-cache-size = <8000>;          // L1, 32K
  36                         timebase-frequency = <0>;       // 33 MHz, from uboot
  37                         bus-frequency = <0>;            // From uboot
  38                         clock-frequency = <0>;          // From uboot
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <00000000 20000000>;      // 512M at 0x0
  45         };
  46
  47         soc@e0000000 {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 #interrupt-cells = <2>;
  51                 device_type = "soc";
  52                 compatible = "fsl,mpc8610-immr", "simple-bus";
  53                 ranges = <0 e0000000 00100000>;
  54                 reg = <e0000000 1000>;
  55                 bus-frequency = <0>;
  56
  57                 i2c@3000 {
  58                         #address-cells = <1>;
  59                         #size-cells = <0>;
  60                         cell-index = <0>;
  61                         compatible = "fsl-i2c";
  62                         reg = <3000 100>;
  63                         interrupts = <2b 2>;
  64                         interrupt-parent = <&mpic>;
  65                         dfsrr;
  66
  67                         cs4270:codec@4f {
  68                                 compatible = "cirrus,cs4270";
  69                                 reg = <4f>;
  70                                 /* MCLK source is a stand-alone oscillator */
  71                                 clock-frequency = <bb8000>;
  72                         };
  73                 };
  74
  75                 i2c@3100 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         cell-index = <1>;
  79                         compatible = "fsl-i2c";
  80                         reg = <3100 100>;
  81                         interrupts = <2b 2>;
  82                         interrupt-parent = <&mpic>;
  83                         dfsrr;
  84                 };
  85
  86                 serial0: serial@4500 {
  87                         cell-index = <0>;
  88                         device_type = "serial";
  89                         compatible = "ns16550";
  90                         reg = <4500 100>;
  91                         clock-frequency = <0>;
  92                         interrupts = <2a 2>;
  93                         interrupt-parent = <&mpic>;
  94                 };
  95
  96                 serial1: serial@4600 {
  97                         cell-index = <1>;
  98                         device_type = "serial";
  99                         compatible = "ns16550";
 100                         reg = <4600 100>;
 101                         clock-frequency = <0>;
 102                         interrupts = <1c 2>;
 103                         interrupt-parent = <&mpic>;
 104                 };
 105
 106                 mpic: interrupt-controller@40000 {
 107                         clock-frequency = <0>;
 108                         interrupt-controller;
 109                         #address-cells = <0>;
 110                         #interrupt-cells = <2>;
 111                         reg = <40000 40000>;
 112                         compatible = "chrp,open-pic";
 113                         device_type = "open-pic";
 114                         big-endian;
 115                 };
 116
 117                 global-utilities@e0000 {
 118                         compatible = "fsl,mpc8610-guts";
 119                         reg = <e0000 1000>;
 120                         fsl,has-rstcr;
 121                 };
 122
 123                 i2s@16000 {
 124                         compatible = "fsl,mpc8610-ssi";
 125                         cell-index = <0>;
 126                         reg = <16000 100>;
 127                         interrupt-parent = <&mpic>;
 128                         interrupts = <3e 2>;
 129                         fsl,mode = "i2s-slave";
 130                         codec-handle = <&cs4270>;
 131                 };
 132
 133                 ssi@16100 {
 134                         compatible = "fsl,mpc8610-ssi";
 135                         cell-index = <1>;
 136                         reg = <16100 100>;
 137                         interrupt-parent = <&mpic>;
 138                         interrupts = <3f 2>;
 139                 };
 140
 141                 dma@21300 {
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 145                         cell-index = <0>;
 146                         reg = <21300 4>; /* DMA general status register */
 147                         ranges = <0 21100 200>;
 148
 149                         dma-channel@0 {
 150                                 compatible = "fsl,mpc8610-dma-channel",
 151                                         "fsl,eloplus-dma-channel";
 152                                 cell-index = <0>;
 153                                 reg = <0 80>;
 154                                 interrupt-parent = <&mpic>;
 155                                 interrupts = <14 2>;
 156                         };
 157                         dma-channel@1 {
 158                                 compatible = "fsl,mpc8610-dma-channel",
 159                                         "fsl,eloplus-dma-channel";
 160                                 cell-index = <1>;
 161                                 reg = <80 80>;
 162                                 interrupt-parent = <&mpic>;
 163                                 interrupts = <15 2>;
 164                         };
 165                         dma-channel@2 {
 166                                 compatible = "fsl,mpc8610-dma-channel",
 167                                         "fsl,eloplus-dma-channel";
 168                                 cell-index = <2>;
 169                                 reg = <100 80>;
 170                                 interrupt-parent = <&mpic>;
 171                                 interrupts = <16 2>;
 172                         };
 173                         dma-channel@3 {
 174                                 compatible = "fsl,mpc8610-dma-channel",
 175                                         "fsl,eloplus-dma-channel";
 176                                 cell-index = <3>;
 177                                 reg = <180 80>;
 178                                 interrupt-parent = <&mpic>;
 179                                 interrupts = <17 2>;
 180                         };
 181                 };
 182
 183                 dma@c300 {
 184                         #address-cells = <1>;
 185                         #size-cells = <1>;
 186                         compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
 187                         cell-index = <1>;
 188                         reg = <c300 4>; /* DMA general status register */
 189                         ranges = <0 c100 200>;
 190
 191                         dma-channel@0 {
 192                                 compatible = "fsl,mpc8610-dma-channel",
 193                                         "fsl,mpc8540-dma-channel";
 194                                 cell-index = <0>;
 195                                 reg = <0 80>;
 196                                 interrupt-parent = <&mpic>;
 197                                 interrupts = <3c 2>;
 198                         };
 199                         dma-channel@1 {
 200                                 compatible = "fsl,mpc8610-dma-channel",
 201                                         "fsl,mpc8540-dma-channel";
 202                                 cell-index = <1>;
 203                                 reg = <80 80>;
 204                                 interrupt-parent = <&mpic>;
 205                                 interrupts = <3d 2>;
 206                         };
 207                         dma-channel@2 {
 208                                 compatible = "fsl,mpc8610-dma-channel",
 209                                         "fsl,mpc8540-dma-channel";
 210                                 cell-index = <2>;
 211                                 reg = <100 80>;
 212                                 interrupt-parent = <&mpic>;
 213                                 interrupts = <3e 2>;
 214                         };
 215                         dma-channel@3 {
 216                                 compatible = "fsl,mpc8610-dma-channel",
 217                                         "fsl,mpc8540-dma-channel";
 218                                 cell-index = <3>;
 219                                 reg = <180 80>;
 220                                 interrupt-parent = <&mpic>;
 221                                 interrupts = <3f 2>;
 222                         };
 223                 };
 224
 225         };
 226
 227         pci0: pci@e0008000 {
 228                 cell-index = <0>;
 229                 compatible = "fsl,mpc8610-pci";
 230                 device_type = "pci";
 231                 #interrupt-cells = <1>;
 232                 #size-cells = <2>;
 233                 #address-cells = <3>;
 234                 reg = <e0008000 1000>;
 235                 bus-range = <0 0>;
 236                 ranges = <02000000 0 80000000 80000000 0 10000000
 237                           01000000 0 00000000 e1000000 0 00100000>;
 238                 clock-frequency = <1fca055>;
 239                 interrupt-parent = <&mpic>;
 240                 interrupts = <18 2>;
 241                 interrupt-map-mask = <f800 0 0 7>;
 242                 interrupt-map = <
 243                         /* IDSEL 0x11 */
 244                         8800 0 0 1 &mpic 4 1
 245                         8800 0 0 2 &mpic 5 1
 246                         8800 0 0 3 &mpic 6 1
 247                         8800 0 0 4 &mpic 7 1
 248
 249                         /* IDSEL 0x12 */
 250                         9000 0 0 1 &mpic 5 1
 251                         9000 0 0 2 &mpic 6 1
 252                         9000 0 0 3 &mpic 7 1
 253                         9000 0 0 4 &mpic 4 1
 254                         >;
 255         };
 256
 257         pci1: pcie@e000a000 {
 258                 cell-index = <1>;
 259                 compatible = "fsl,mpc8641-pcie";
 260                 device_type = "pci";
 261                 #interrupt-cells = <1>;
 262                 #size-cells = <2>;
 263                 #address-cells = <3>;
 264                 reg = <e000a000 1000>;
 265                 bus-range = <1 3>;
 266                 ranges = <02000000 0 a0000000 a0000000 0 10000000
 267                           01000000 0 00000000 e3000000 0 00100000>;
 268                 clock-frequency = <1fca055>;
 269                 interrupt-parent = <&mpic>;
 270                 interrupts = <1a 2>;
 271                 interrupt-map-mask = <f800 0 0 7>;
 272
 273                 interrupt-map = <
 274                         /* IDSEL 0x1b */
 275                         d800 0 0 1 &mpic 2 1
 276
 277                         /* IDSEL 0x1c*/
 278                         e000 0 0 1 &mpic 1 1
 279                         e000 0 0 2 &mpic 1 1
 280                         e000 0 0 3 &mpic 1 1
 281                         e000 0 0 4 &mpic 1 1
 282
 283                         /* IDSEL 0x1f */
 284                         f800 0 0 1 &mpic 3 0
 285                         f800 0 0 2 &mpic 0 1
 286                 >;
 287
 288                 pcie@0 {
 289                         reg = <0 0 0 0 0>;
 290                         #size-cells = <2>;
 291                         #address-cells = <3>;
 292                         device_type = "pci";
 293                         ranges = <02000000 0 a0000000
 294                                   02000000 0 a0000000
 295                                   0 10000000
 296                                   01000000 0 00000000
 297                                   01000000 0 00000000
 298                                   0 00100000>;
 299                         uli1575@0 {
 300                                 reg = <0 0 0 0 0>;
 301                                 #size-cells = <2>;
 302                                 #address-cells = <3>;
 303                                 ranges = <02000000 0 a0000000
 304                                           02000000 0 a0000000
 305                                           0 10000000
 306                                           01000000 0 00000000
 307                                           01000000 0 00000000
 308                                           0 00100000>;
 309                         };
 310                 };
 311         };
 312 };