err.no Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 /dts-v1/;
  12
  13 / {
  14         model = "MPC8610HPCD";
  15         compatible = "fsl,MPC8610HPCD";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 serial0 = &serial0;
  21                 serial1 = &serial1;
  22                 pci0 = &pci0;
  23                 pci1 = &pci1;
  24                 pci2 = &pci2;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 PowerPC,8610@0 {
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         d-cache-line-size = <32>;
  35                         i-cache-line-size = <32>;
  36                         d-cache-size = <32768>;         // L1
  37                         i-cache-size = <32768>;         // L1
  38                         timebase-frequency = <0>;       // From uboot
  39                         bus-frequency = <0>;            // From uboot
  40                         clock-frequency = <0>;          // From uboot
  41                 };
  42         };
  43
  44         memory {
  45                 device_type = "memory";
  46                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  47         };
  48
  49         board-control@e8000000 {
  50                 compatible = "fsl,fpga-pixis";
  51                 reg = <0xe8000000 32>;          // pixis at 0xe8000000
  52         };
  53
  54         soc@e0000000 {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 #interrupt-cells = <2>;
  58                 device_type = "soc";
  59                 compatible = "fsl,mpc8610-immr", "simple-bus";
  60                 ranges = <0x0 0xe0000000 0x00100000>;
  61                 reg = <0xe0000000 0x1000>;
  62                 bus-frequency = <0>;
  63
  64                 i2c@3000 {
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67                         cell-index = <0>;
  68                         compatible = "fsl-i2c";
  69                         reg = <0x3000 0x100>;
  70                         interrupts = <43 2>;
  71                         interrupt-parent = <&mpic>;
  72                         dfsrr;
  73
  74                         cs4270:codec@4f {
  75                                 compatible = "cirrus,cs4270";
  76                                 reg = <0x4f>;
  77                                 /* MCLK source is a stand-alone oscillator */
  78                                 clock-frequency = <12288000>;
  79                         };
  80                 };
  81
  82                 i2c@3100 {
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         cell-index = <1>;
  86                         compatible = "fsl-i2c";
  87                         reg = <0x3100 0x100>;
  88                         interrupts = <43 2>;
  89                         interrupt-parent = <&mpic>;
  90                         dfsrr;
  91                 };
  92
  93                 serial0: serial@4500 {
  94                         cell-index = <0>;
  95                         device_type = "serial";
  96                         compatible = "ns16550";
  97                         reg = <0x4500 0x100>;
  98                         clock-frequency = <0>;
  99                         interrupts = <42 2>;
 100                         interrupt-parent = <&mpic>;
 101                 };
 102
 103                 serial1: serial@4600 {
 104                         cell-index = <1>;
 105                         device_type = "serial";
 106                         compatible = "ns16550";
 107                         reg = <0x4600 0x100>;
 108                         clock-frequency = <0>;
 109                         interrupts = <42 2>;
 110                         interrupt-parent = <&mpic>;
 111                 };
 112
 113                 display@2c000 {
 114                         compatible = "fsl,diu";
 115                         reg = <0x2c000 100>;
 116                         interrupts = <72 2>;
 117                         interrupt-parent = <&mpic>;
 118                 };
 119
 120                 mpic: interrupt-controller@40000 {
 121                         clock-frequency = <0>;
 122                         interrupt-controller;
 123                         #address-cells = <0>;
 124                         #interrupt-cells = <2>;
 125                         reg = <0x40000 0x40000>;
 126                         compatible = "chrp,open-pic";
 127                         device_type = "open-pic";
 128                         big-endian;
 129                 };
 130
 131                 global-utilities@e0000 {
 132                         compatible = "fsl,mpc8610-guts";
 133                         reg = <0xe0000 0x1000>;
 134                         fsl,has-rstcr;
 135                 };
 136
 137                 i2s@16000 {
 138                         compatible = "fsl,mpc8610-ssi";
 139                         cell-index = <0>;
 140                         reg = <0x16000 0x100>;
 141                         interrupt-parent = <&mpic>;
 142                         interrupts = <62 2>;
 143                         fsl,mode = "i2s-slave";
 144                         codec-handle = <&cs4270>;
 145                 };
 146
 147                 ssi@16100 {
 148                         compatible = "fsl,mpc8610-ssi";
 149                         cell-index = <1>;
 150                         reg = <0x16100 0x100>;
 151                         interrupt-parent = <&mpic>;
 152                         interrupts = <63 2>;
 153                 };
 154
 155                 dma@21300 {
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 159                         cell-index = <0>;
 160                         reg = <0x21300 0x4>; /* DMA general status register */
 161                         ranges = <0x0 0x21100 0x200>;
 162
 163                         dma-channel@0 {
 164                                 compatible = "fsl,mpc8610-dma-channel",
 165                                         "fsl,eloplus-dma-channel";
 166                                 cell-index = <0>;
 167                                 reg = <0x0 0x80>;
 168                                 interrupt-parent = <&mpic>;
 169                                 interrupts = <20 2>;
 170                         };
 171                         dma-channel@1 {
 172                                 compatible = "fsl,mpc8610-dma-channel",
 173                                         "fsl,eloplus-dma-channel";
 174                                 cell-index = <1>;
 175                                 reg = <0x80 0x80>;
 176                                 interrupt-parent = <&mpic>;
 177                                 interrupts = <21 2>;
 178                         };
 179                         dma-channel@2 {
 180                                 compatible = "fsl,mpc8610-dma-channel",
 181                                         "fsl,eloplus-dma-channel";
 182                                 cell-index = <2>;
 183                                 reg = <0x100 0x80>;
 184                                 interrupt-parent = <&mpic>;
 185                                 interrupts = <22 2>;
 186                         };
 187                         dma-channel@3 {
 188                                 compatible = "fsl,mpc8610-dma-channel",
 189                                         "fsl,eloplus-dma-channel";
 190                                 cell-index = <3>;
 191                                 reg = <0x180 0x80>;
 192                                 interrupt-parent = <&mpic>;
 193                                 interrupts = <23 2>;
 194                         };
 195                 };
 196
 197                 dma@c300 {
 198                         #address-cells = <1>;
 199                         #size-cells = <1>;
 200                         compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
 201                         cell-index = <1>;
 202                         reg = <0xc300 0x4>; /* DMA general status register */
 203                         ranges = <0x0 0xc100 0x200>;
 204
 205                         dma-channel@0 {
 206                                 compatible = "fsl,mpc8610-dma-channel",
 207                                         "fsl,mpc8540-dma-channel";
 208                                 cell-index = <0>;
 209                                 reg = <0x0 0x80>;
 210                                 interrupt-parent = <&mpic>;
 211                                 interrupts = <60 2>;
 212                         };
 213                         dma-channel@1 {
 214                                 compatible = "fsl,mpc8610-dma-channel",
 215                                         "fsl,mpc8540-dma-channel";
 216                                 cell-index = <1>;
 217                                 reg = <0x80 0x80>;
 218                                 interrupt-parent = <&mpic>;
 219                                 interrupts = <61 2>;
 220                         };
 221                         dma-channel@2 {
 222                                 compatible = "fsl,mpc8610-dma-channel",
 223                                         "fsl,mpc8540-dma-channel";
 224                                 cell-index = <2>;
 225                                 reg = <0x100 0x80>;
 226                                 interrupt-parent = <&mpic>;
 227                                 interrupts = <62 2>;
 228                         };
 229                         dma-channel@3 {
 230                                 compatible = "fsl,mpc8610-dma-channel",
 231                                         "fsl,mpc8540-dma-channel";
 232                                 cell-index = <3>;
 233                                 reg = <0x180 0x80>;
 234                                 interrupt-parent = <&mpic>;
 235                                 interrupts = <63 2>;
 236                         };
 237                 };
 238
 239         };
 240
 241         pci0: pci@e0008000 {
 242                 cell-index = <0>;
 243                 compatible = "fsl,mpc8610-pci";
 244                 device_type = "pci";
 245                 #interrupt-cells = <1>;
 246                 #size-cells = <2>;
 247                 #address-cells = <3>;
 248                 reg = <0xe0008000 0x1000>;
 249                 bus-range = <0 0>;
 250                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 251                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
 252                 clock-frequency = <33333333>;
 253                 interrupt-parent = <&mpic>;
 254                 interrupts = <24 2>;
 255                 interrupt-map-mask = <0xf800 0 0 7>;
 256                 interrupt-map = <
 257                         /* IDSEL 0x11 */
 258                         0x8800 0 0 1 &mpic 4 1
 259                         0x8800 0 0 2 &mpic 5 1
 260                         0x8800 0 0 3 &mpic 6 1
 261                         0x8800 0 0 4 &mpic 7 1
 262
 263                         /* IDSEL 0x12 */
 264                         0x9000 0 0 1 &mpic 5 1
 265                         0x9000 0 0 2 &mpic 6 1
 266                         0x9000 0 0 3 &mpic 7 1
 267                         0x9000 0 0 4 &mpic 4 1
 268                         >;
 269         };
 270
 271         pci1: pcie@e000a000 {
 272                 cell-index = <1>;
 273                 compatible = "fsl,mpc8641-pcie";
 274                 device_type = "pci";
 275                 #interrupt-cells = <1>;
 276                 #size-cells = <2>;
 277                 #address-cells = <3>;
 278                 reg = <0xe000a000 0x1000>;
 279                 bus-range = <1 3>;
 280                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 281                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 282                 clock-frequency = <33333333>;
 283                 interrupt-parent = <&mpic>;
 284                 interrupts = <26 2>;
 285                 interrupt-map-mask = <0xf800 0 0 7>;
 286
 287                 interrupt-map = <
 288                         /* IDSEL 0x1b */
 289                         0xd800 0 0 1 &mpic 2 1
 290
 291                         /* IDSEL 0x1c*/
 292                         0xe000 0 0 1 &mpic 1 1
 293                         0xe000 0 0 2 &mpic 1 1
 294                         0xe000 0 0 3 &mpic 1 1
 295                         0xe000 0 0 4 &mpic 1 1
 296
 297                         /* IDSEL 0x1f */
 298                         0xf800 0 0 1 &mpic 3 0
 299                         0xf800 0 0 2 &mpic 0 1
 300                 >;
 301
 302                 pcie@0 {
 303                         reg = <0 0 0 0 0>;
 304                         #size-cells = <2>;
 305                         #address-cells = <3>;
 306                         device_type = "pci";
 307                         ranges = <0x02000000 0x0 0xa0000000
 308                                   0x02000000 0x0 0xa0000000
 309                                   0x0 0x10000000
 310                                   0x01000000 0x0 0x00000000
 311                                   0x01000000 0x0 0x00000000
 312                                   0x0 0x00100000>;
 313                         uli1575@0 {
 314                                 reg = <0 0 0 0 0>;
 315                                 #size-cells = <2>;
 316                                 #address-cells = <3>;
 317                                 ranges = <0x02000000 0x0 0xa0000000
 318                                           0x02000000 0x0 0xa0000000
 319                                           0x0 0x10000000
 320                                           0x01000000 0x0 0x00000000
 321                                           0x01000000 0x0 0x00000000
 322                                           0x0 0x00100000>;
 323                         };
 324                 };
 325         };
 326
 327         pci2: pcie@e0009000 {
 328                 #address-cells = <3>;
 329                 #size-cells = <2>;
 330                 #interrupt-cells = <1>;
 331                 device_type = "pci";
 332                 compatible = "fsl,mpc8641-pcie";
 333                 reg = <0xe0009000 0x00001000>;
 334                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
 335                           0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
 336                 bus-range = <0 255>;
 337                 interrupt-map-mask = <0xf800 0 0 7>;
 338                 interrupt-map = <0x0000 0 0 1 &mpic 4 1
 339                                  0x0000 0 0 2 &mpic 5 1
 340                                  0x0000 0 0 3 &mpic 6 1
 341                                  0x0000 0 0 4 &mpic 7 1>;
 342                 interrupt-parent = <&mpic>;
 343                 interrupts = <25 2>;
 344                 clock-frequency = <33333333>;
 345         };
 346 };