err.no Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 /dts-v1/;
  12
  13 / {
  14         model = "MPC8610HPCD";
  15         compatible = "fsl,MPC8610HPCD";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 serial0 = &serial0;
  21                 serial1 = &serial1;
  22                 pci0 = &pci0;
  23                 pci1 = &pci1;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,8610@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <32>;
  34                         i-cache-line-size = <32>;
  35                         d-cache-size = <32768>;         // L1
  36                         i-cache-size = <32768>;         // L1
  37                         timebase-frequency = <0>;       // From uboot
  38                         bus-frequency = <0>;            // From uboot
  39                         clock-frequency = <0>;          // From uboot
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  46         };
  47
  48         board-control@e8000000 {
  49                 compatible = "fsl,fpga-pixis";
  50                 reg = <0xe8000000 32>;          // pixis at 0xe8000000
  51         };
  52
  53         soc@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 #interrupt-cells = <2>;
  57                 device_type = "soc";
  58                 compatible = "fsl,mpc8610-immr", "simple-bus";
  59                 ranges = <0x0 0xe0000000 0x00100000>;
  60                 reg = <0xe0000000 0x1000>;
  61                 bus-frequency = <0>;
  62
  63                 i2c@3000 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66                         cell-index = <0>;
  67                         compatible = "fsl-i2c";
  68                         reg = <0x3000 0x100>;
  69                         interrupts = <43 2>;
  70                         interrupt-parent = <&mpic>;
  71                         dfsrr;
  72
  73                         cs4270:codec@4f {
  74                                 compatible = "cirrus,cs4270";
  75                                 reg = <0x4f>;
  76                                 /* MCLK source is a stand-alone oscillator */
  77                                 clock-frequency = <12288000>;
  78                         };
  79                 };
  80
  81                 i2c@3100 {
  82                         #address-cells = <1>;
  83                         #size-cells = <0>;
  84                         cell-index = <1>;
  85                         compatible = "fsl-i2c";
  86                         reg = <0x3100 0x100>;
  87                         interrupts = <43 2>;
  88                         interrupt-parent = <&mpic>;
  89                         dfsrr;
  90                 };
  91
  92                 serial0: serial@4500 {
  93                         cell-index = <0>;
  94                         device_type = "serial";
  95                         compatible = "ns16550";
  96                         reg = <0x4500 0x100>;
  97                         clock-frequency = <0>;
  98                         interrupts = <42 2>;
  99                         interrupt-parent = <&mpic>;
 100                 };
 101
 102                 serial1: serial@4600 {
 103                         cell-index = <1>;
 104                         device_type = "serial";
 105                         compatible = "ns16550";
 106                         reg = <0x4600 0x100>;
 107                         clock-frequency = <0>;
 108                         interrupts = <28 2>;
 109                         interrupt-parent = <&mpic>;
 110                 };
 111
 112                 display@2c000 {
 113                         compatible = "fsl,diu";
 114                         reg = <0x2c000 100>;
 115                         interrupts = <72 2>;
 116                         interrupt-parent = <&mpic>;
 117                 };
 118
 119                 mpic: interrupt-controller@40000 {
 120                         clock-frequency = <0>;
 121                         interrupt-controller;
 122                         #address-cells = <0>;
 123                         #interrupt-cells = <2>;
 124                         reg = <0x40000 0x40000>;
 125                         compatible = "chrp,open-pic";
 126                         device_type = "open-pic";
 127                         big-endian;
 128                 };
 129
 130                 global-utilities@e0000 {
 131                         compatible = "fsl,mpc8610-guts";
 132                         reg = <0xe0000 0x1000>;
 133                         fsl,has-rstcr;
 134                 };
 135
 136                 i2s@16000 {
 137                         compatible = "fsl,mpc8610-ssi";
 138                         cell-index = <0>;
 139                         reg = <0x16000 0x100>;
 140                         interrupt-parent = <&mpic>;
 141                         interrupts = <62 2>;
 142                         fsl,mode = "i2s-slave";
 143                         codec-handle = <&cs4270>;
 144                 };
 145
 146                 ssi@16100 {
 147                         compatible = "fsl,mpc8610-ssi";
 148                         cell-index = <1>;
 149                         reg = <0x16100 0x100>;
 150                         interrupt-parent = <&mpic>;
 151                         interrupts = <63 2>;
 152                 };
 153
 154                 dma@21300 {
 155                         #address-cells = <1>;
 156                         #size-cells = <1>;
 157                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 158                         cell-index = <0>;
 159                         reg = <0x21300 0x4>; /* DMA general status register */
 160                         ranges = <0x0 0x21100 0x200>;
 161
 162                         dma-channel@0 {
 163                                 compatible = "fsl,mpc8610-dma-channel",
 164                                         "fsl,eloplus-dma-channel";
 165                                 cell-index = <0>;
 166                                 reg = <0x0 0x80>;
 167                                 interrupt-parent = <&mpic>;
 168                                 interrupts = <20 2>;
 169                         };
 170                         dma-channel@1 {
 171                                 compatible = "fsl,mpc8610-dma-channel",
 172                                         "fsl,eloplus-dma-channel";
 173                                 cell-index = <1>;
 174                                 reg = <0x80 0x80>;
 175                                 interrupt-parent = <&mpic>;
 176                                 interrupts = <21 2>;
 177                         };
 178                         dma-channel@2 {
 179                                 compatible = "fsl,mpc8610-dma-channel",
 180                                         "fsl,eloplus-dma-channel";
 181                                 cell-index = <2>;
 182                                 reg = <0x100 0x80>;
 183                                 interrupt-parent = <&mpic>;
 184                                 interrupts = <22 2>;
 185                         };
 186                         dma-channel@3 {
 187                                 compatible = "fsl,mpc8610-dma-channel",
 188                                         "fsl,eloplus-dma-channel";
 189                                 cell-index = <3>;
 190                                 reg = <0x180 0x80>;
 191                                 interrupt-parent = <&mpic>;
 192                                 interrupts = <23 2>;
 193                         };
 194                 };
 195
 196                 dma@c300 {
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
 200                         cell-index = <1>;
 201                         reg = <0xc300 0x4>; /* DMA general status register */
 202                         ranges = <0x0 0xc100 0x200>;
 203
 204                         dma-channel@0 {
 205                                 compatible = "fsl,mpc8610-dma-channel",
 206                                         "fsl,mpc8540-dma-channel";
 207                                 cell-index = <0>;
 208                                 reg = <0x0 0x80>;
 209                                 interrupt-parent = <&mpic>;
 210                                 interrupts = <60 2>;
 211                         };
 212                         dma-channel@1 {
 213                                 compatible = "fsl,mpc8610-dma-channel",
 214                                         "fsl,mpc8540-dma-channel";
 215                                 cell-index = <1>;
 216                                 reg = <0x80 0x80>;
 217                                 interrupt-parent = <&mpic>;
 218                                 interrupts = <61 2>;
 219                         };
 220                         dma-channel@2 {
 221                                 compatible = "fsl,mpc8610-dma-channel",
 222                                         "fsl,mpc8540-dma-channel";
 223                                 cell-index = <2>;
 224                                 reg = <0x100 0x80>;
 225                                 interrupt-parent = <&mpic>;
 226                                 interrupts = <62 2>;
 227                         };
 228                         dma-channel@3 {
 229                                 compatible = "fsl,mpc8610-dma-channel",
 230                                         "fsl,mpc8540-dma-channel";
 231                                 cell-index = <3>;
 232                                 reg = <0x180 0x80>;
 233                                 interrupt-parent = <&mpic>;
 234                                 interrupts = <63 2>;
 235                         };
 236                 };
 237
 238         };
 239
 240         pci0: pci@e0008000 {
 241                 cell-index = <0>;
 242                 compatible = "fsl,mpc8610-pci";
 243                 device_type = "pci";
 244                 #interrupt-cells = <1>;
 245                 #size-cells = <2>;
 246                 #address-cells = <3>;
 247                 reg = <0xe0008000 0x1000>;
 248                 bus-range = <0 0>;
 249                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 250                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
 251                 clock-frequency = <33333333>;
 252                 interrupt-parent = <&mpic>;
 253                 interrupts = <24 2>;
 254                 interrupt-map-mask = <0xf800 0 0 7>;
 255                 interrupt-map = <
 256                         /* IDSEL 0x11 */
 257                         0x8800 0 0 1 &mpic 4 1
 258                         0x8800 0 0 2 &mpic 5 1
 259                         0x8800 0 0 3 &mpic 6 1
 260                         0x8800 0 0 4 &mpic 7 1
 261
 262                         /* IDSEL 0x12 */
 263                         0x9000 0 0 1 &mpic 5 1
 264                         0x9000 0 0 2 &mpic 6 1
 265                         0x9000 0 0 3 &mpic 7 1
 266                         0x9000 0 0 4 &mpic 4 1
 267                         >;
 268         };
 269
 270         pci1: pcie@e000a000 {
 271                 cell-index = <1>;
 272                 compatible = "fsl,mpc8641-pcie";
 273                 device_type = "pci";
 274                 #interrupt-cells = <1>;
 275                 #size-cells = <2>;
 276                 #address-cells = <3>;
 277                 reg = <0xe000a000 0x1000>;
 278                 bus-range = <1 3>;
 279                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 280                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 281                 clock-frequency = <33333333>;
 282                 interrupt-parent = <&mpic>;
 283                 interrupts = <26 2>;
 284                 interrupt-map-mask = <0xf800 0 0 7>;
 285
 286                 interrupt-map = <
 287                         /* IDSEL 0x1b */
 288                         0xd800 0 0 1 &mpic 2 1
 289
 290                         /* IDSEL 0x1c*/
 291                         0xe000 0 0 1 &mpic 1 1
 292                         0xe000 0 0 2 &mpic 1 1
 293                         0xe000 0 0 3 &mpic 1 1
 294                         0xe000 0 0 4 &mpic 1 1
 295
 296                         /* IDSEL 0x1f */
 297                         0xf800 0 0 1 &mpic 3 0
 298                         0xf800 0 0 2 &mpic 0 1
 299                 >;
 300
 301                 pcie@0 {
 302                         reg = <0 0 0 0 0>;
 303                         #size-cells = <2>;
 304                         #address-cells = <3>;
 305                         device_type = "pci";
 306                         ranges = <0x02000000 0x0 0xa0000000
 307                                   0x02000000 0x0 0xa0000000
 308                                   0x0 0x10000000
 309                                   0x01000000 0x0 0x00000000
 310                                   0x01000000 0x0 0x00000000
 311                                   0x0 0x00100000>;
 312                         uli1575@0 {
 313                                 reg = <0 0 0 0 0>;
 314                                 #size-cells = <2>;
 315                                 #address-cells = <3>;
 316                                 ranges = <0x02000000 0x0 0xa0000000
 317                                           0x02000000 0x0 0xa0000000
 318                                           0x0 0x10000000
 319                                           0x01000000 0x0 0x00000000
 320                                           0x01000000 0x0 0x00000000
 321                                           0x0 0x00100000>;
 322                         };
 323                 };
 324         };
 325 };