2 * MPC8572 DS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS";
37 d-cache-line-size = <20>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
48 device_type = "memory";
49 reg = <00000000 00000000>; // Filled by U-Boot
56 ranges = <00000000 ffe00000 00100000>;
57 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
58 bus-frequency = <0>; // Filled out by uboot.
60 memory-controller@2000 {
61 compatible = "fsl,mpc8572-memory-controller";
63 interrupt-parent = <&mpic>;
67 memory-controller@6000 {
68 compatible = "fsl,mpc8572-memory-controller";
70 interrupt-parent = <&mpic>;
74 l2-cache-controller@20000 {
75 compatible = "fsl,mpc8572-l2-cache-controller";
77 cache-line-size = <20>; // 32 bytes
78 cache-size = <80000>; // L2, 512K
79 interrupt-parent = <&mpic>;
87 compatible = "fsl-i2c";
90 interrupt-parent = <&mpic>;
98 compatible = "fsl-i2c";
101 interrupt-parent = <&mpic>;
106 #address-cells = <1>;
108 compatible = "fsl,gianfar-mdio";
111 phy0: ethernet-phy@0 {
112 interrupt-parent = <&mpic>;
116 phy1: ethernet-phy@1 {
117 interrupt-parent = <&mpic>;
121 phy2: ethernet-phy@2 {
122 interrupt-parent = <&mpic>;
126 phy3: ethernet-phy@3 {
127 interrupt-parent = <&mpic>;
133 enet0: ethernet@24000 {
135 device_type = "network";
137 compatible = "gianfar";
139 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <1d 2 1e 2 22 2>;
141 interrupt-parent = <&mpic>;
142 phy-handle = <&phy0>;
143 phy-connection-type = "rgmii-id";
146 enet1: ethernet@25000 {
148 device_type = "network";
150 compatible = "gianfar";
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <23 2 24 2 28 2>;
154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy1>;
156 phy-connection-type = "rgmii-id";
159 enet2: ethernet@26000 {
161 device_type = "network";
163 compatible = "gianfar";
165 local-mac-address = [ 00 00 00 00 00 00 ];
166 interrupts = <1f 2 20 2 21 2>;
167 interrupt-parent = <&mpic>;
168 phy-handle = <&phy2>;
169 phy-connection-type = "rgmii-id";
172 enet3: ethernet@27000 {
174 device_type = "network";
176 compatible = "gianfar";
178 local-mac-address = [ 00 00 00 00 00 00 ];
179 interrupts = <25 2 26 2 27 2>;
180 interrupt-parent = <&mpic>;
181 phy-handle = <&phy3>;
182 phy-connection-type = "rgmii-id";
185 serial0: serial@4500 {
187 device_type = "serial";
188 compatible = "ns16550";
190 clock-frequency = <0>;
192 interrupt-parent = <&mpic>;
195 serial1: serial@4600 {
197 device_type = "serial";
198 compatible = "ns16550";
200 clock-frequency = <0>;
202 interrupt-parent = <&mpic>;
205 global-utilities@e0000 { //global utilities block
206 compatible = "fsl,mpc8572-guts";
212 clock-frequency = <0>;
213 interrupt-controller;
214 #address-cells = <0>;
215 #interrupt-cells = <2>;
217 compatible = "chrp,open-pic";
218 device_type = "open-pic";
223 pci0: pcie@ffe08000 {
225 compatible = "fsl,mpc8548-pcie";
227 #interrupt-cells = <1>;
229 #address-cells = <3>;
230 reg = <ffe08000 1000>;
232 ranges = <02000000 0 80000000 80000000 0 20000000
233 01000000 0 00000000 ffc00000 0 00010000>;
234 clock-frequency = <1fca055>;
235 interrupt-parent = <&mpic>;
237 interrupt-map-mask = <ff00 0 0 7>;
239 /* IDSEL 0x11 func 0 - PCI slot 1 */
245 /* IDSEL 0x11 func 1 - PCI slot 1 */
251 /* IDSEL 0x11 func 2 - PCI slot 1 */
257 /* IDSEL 0x11 func 3 - PCI slot 1 */
263 /* IDSEL 0x11 func 4 - PCI slot 1 */
269 /* IDSEL 0x11 func 5 - PCI slot 1 */
275 /* IDSEL 0x11 func 6 - PCI slot 1 */
281 /* IDSEL 0x11 func 7 - PCI slot 1 */
287 /* IDSEL 0x12 func 0 - PCI slot 2 */
293 /* IDSEL 0x12 func 1 - PCI slot 2 */
299 /* IDSEL 0x12 func 2 - PCI slot 2 */
305 /* IDSEL 0x12 func 3 - PCI slot 2 */
311 /* IDSEL 0x12 func 4 - PCI slot 2 */
317 /* IDSEL 0x12 func 5 - PCI slot 2 */
323 /* IDSEL 0x12 func 6 - PCI slot 2 */
329 /* IDSEL 0x12 func 7 - PCI slot 2 */
336 e000 0 0 1 &i8259 c 2
337 e100 0 0 2 &i8259 9 2
338 e200 0 0 3 &i8259 a 2
339 e300 0 0 4 &i8259 b 2
342 e800 0 0 1 &i8259 6 2
345 f000 0 0 1 &i8259 7 2
346 f100 0 0 1 &i8259 7 2
348 // IDSEL 0x1f IDE/SATA
349 f800 0 0 1 &i8259 e 2
350 f900 0 0 1 &i8259 5 2
357 #address-cells = <3>;
359 ranges = <02000000 0 80000000
369 #address-cells = <3>;
370 ranges = <02000000 0 80000000
379 #interrupt-cells = <2>;
381 #address-cells = <2>;
382 reg = <f000 0 0 0 0>;
383 ranges = <1 0 01000000 0 0
385 interrupt-parent = <&i8259>;
387 i8259: interrupt-controller@20 {
391 interrupt-controller;
392 device_type = "interrupt-controller";
393 #address-cells = <0>;
394 #interrupt-cells = <2>;
395 compatible = "chrp,iic";
397 interrupt-parent = <&mpic>;
402 #address-cells = <1>;
403 reg = <1 60 1 1 64 1>;
404 interrupts = <1 3 c 3>;
410 compatible = "pnpPNP,303";
415 compatible = "pnpPNP,f03";
420 compatible = "pnpPNP,b00";
433 pci1: pcie@ffe09000 {
435 compatible = "fsl,mpc8548-pcie";
437 #interrupt-cells = <1>;
439 #address-cells = <3>;
440 reg = <ffe09000 1000>;
442 ranges = <02000000 0 a0000000 a0000000 0 20000000
443 01000000 0 00000000 ffc10000 0 00010000>;
444 clock-frequency = <1fca055>;
445 interrupt-parent = <&mpic>;
447 interrupt-map-mask = <f800 0 0 7>;
458 #address-cells = <3>;
460 ranges = <02000000 0 a0000000
470 pci2: pcie@ffe0a000 {
472 compatible = "fsl,mpc8548-pcie";
474 #interrupt-cells = <1>;
476 #address-cells = <3>;
477 reg = <ffe0a000 1000>;
479 ranges = <02000000 0 c0000000 c0000000 0 20000000
480 01000000 0 00000000 ffc20000 0 00010000>;
481 clock-frequency = <1fca055>;
482 interrupt-parent = <&mpic>;
484 interrupt-map-mask = <f800 0 0 7>;
495 #address-cells = <3>;
497 ranges = <02000000 0 c0000000