err.no Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23 /*
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26 */
  27                 serial0 = &serial0;
  28                 serial1 = &serial1;
  29                 pci0 = &pci0;
  30                 pci1 = &pci1;
  31                 pci2 = &pci2;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 PowerPC,8548@0 {
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41                         d-cache-line-size = <32>;       // 32 bytes
  42                         i-cache-line-size = <32>;       // 32 bytes
  43                         d-cache-size = <0x8000>;                // L1, 32K
  44                         i-cache-size = <0x8000>;                // L1, 32K
  45                         timebase-frequency = <0>;       //  33 MHz, from uboot
  46                         bus-frequency = <0>;    // 166 MHz
  47                         clock-frequency = <0>;  // 825 MHz, from uboot
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x8000000>;  // 128M at 0x0
  55         };
  56
  57         soc8548@e0000000 {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 device_type = "soc";
  61                 ranges = <0x0 0xe0000000 0x100000>;
  62                 reg = <0xe0000000 0x1000>;      // CCSRBAR
  63                 bus-frequency = <0>;
  64
  65                 memory-controller@2000 {
  66                         compatible = "fsl,8548-memory-controller";
  67                         reg = <0x2000 0x1000>;
  68                         interrupt-parent = <&mpic>;
  69                         interrupts = <18 2>;
  70                 };
  71
  72                 L2: l2-cache-controller@20000 {
  73                         compatible = "fsl,8548-l2-cache-controller";
  74                         reg = <0x20000 0x1000>;
  75                         cache-line-size = <32>; // 32 bytes
  76                         cache-size = <0x80000>; // L2, 512K
  77                         interrupt-parent = <&mpic>;
  78                         interrupts = <16 2>;
  79                 };
  80
  81                 i2c@3000 {
  82                         #address-cells = <1>;
  83                         #size-cells = <0>;
  84                         cell-index = <0>;
  85                         compatible = "fsl-i2c";
  86                         reg = <0x3000 0x100>;
  87                         interrupts = <43 2>;
  88                         interrupt-parent = <&mpic>;
  89                         dfsrr;
  90                 };
  91
  92                 i2c@3100 {
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         cell-index = <1>;
  96                         compatible = "fsl-i2c";
  97                         reg = <0x3100 0x100>;
  98                         interrupts = <43 2>;
  99                         interrupt-parent = <&mpic>;
 100                         dfsrr;
 101                 };
 102
 103                 dma@21300 {
 104                         #address-cells = <1>;
 105                         #size-cells = <1>;
 106                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 107                         reg = <0x21300 0x4>;
 108                         ranges = <0x0 0x21100 0x200>;
 109                         cell-index = <0>;
 110                         dma-channel@0 {
 111                                 compatible = "fsl,mpc8548-dma-channel",
 112                                                 "fsl,eloplus-dma-channel";
 113                                 reg = <0x0 0x80>;
 114                                 cell-index = <0>;
 115                                 interrupt-parent = <&mpic>;
 116                                 interrupts = <20 2>;
 117                         };
 118                         dma-channel@80 {
 119                                 compatible = "fsl,mpc8548-dma-channel",
 120                                                 "fsl,eloplus-dma-channel";
 121                                 reg = <0x80 0x80>;
 122                                 cell-index = <1>;
 123                                 interrupt-parent = <&mpic>;
 124                                 interrupts = <21 2>;
 125                         };
 126                         dma-channel@100 {
 127                                 compatible = "fsl,mpc8548-dma-channel",
 128                                                 "fsl,eloplus-dma-channel";
 129                                 reg = <0x100 0x80>;
 130                                 cell-index = <2>;
 131                                 interrupt-parent = <&mpic>;
 132                                 interrupts = <22 2>;
 133                         };
 134                         dma-channel@180 {
 135                                 compatible = "fsl,mpc8548-dma-channel",
 136                                                 "fsl,eloplus-dma-channel";
 137                                 reg = <0x180 0x80>;
 138                                 cell-index = <3>;
 139                                 interrupt-parent = <&mpic>;
 140                                 interrupts = <23 2>;
 141                         };
 142                 };
 143
 144                 mdio@24520 {
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         compatible = "fsl,gianfar-mdio";
 148                         reg = <0x24520 0x20>;
 149
 150                         phy0: ethernet-phy@0 {
 151                                 interrupt-parent = <&mpic>;
 152                                 interrupts = <5 1>;
 153                                 reg = <0x0>;
 154                                 device_type = "ethernet-phy";
 155                         };
 156                         phy1: ethernet-phy@1 {
 157                                 interrupt-parent = <&mpic>;
 158                                 interrupts = <5 1>;
 159                                 reg = <0x1>;
 160                                 device_type = "ethernet-phy";
 161                         };
 162                         phy2: ethernet-phy@2 {
 163                                 interrupt-parent = <&mpic>;
 164                                 interrupts = <5 1>;
 165                                 reg = <0x2>;
 166                                 device_type = "ethernet-phy";
 167                         };
 168                         phy3: ethernet-phy@3 {
 169                                 interrupt-parent = <&mpic>;
 170                                 interrupts = <5 1>;
 171                                 reg = <0x3>;
 172                                 device_type = "ethernet-phy";
 173                         };
 174                 };
 175
 176                 enet0: ethernet@24000 {
 177                         cell-index = <0>;
 178                         device_type = "network";
 179                         model = "eTSEC";
 180                         compatible = "gianfar";
 181                         reg = <0x24000 0x1000>;
 182                         local-mac-address = [ 00 00 00 00 00 00 ];
 183                         interrupts = <29 2 30 2 34 2>;
 184                         interrupt-parent = <&mpic>;
 185                         phy-handle = <&phy0>;
 186                 };
 187
 188                 enet1: ethernet@25000 {
 189                         cell-index = <1>;
 190                         device_type = "network";
 191                         model = "eTSEC";
 192                         compatible = "gianfar";
 193                         reg = <0x25000 0x1000>;
 194                         local-mac-address = [ 00 00 00 00 00 00 ];
 195                         interrupts = <35 2 36 2 40 2>;
 196                         interrupt-parent = <&mpic>;
 197                         phy-handle = <&phy1>;
 198                 };
 199
 200 /* eTSEC 3/4 are currently broken
 201                 enet2: ethernet@26000 {
 202                         cell-index = <2>;
 203                         device_type = "network";
 204                         model = "eTSEC";
 205                         compatible = "gianfar";
 206                         reg = <0x26000 0x1000>;
 207                         local-mac-address = [ 00 00 00 00 00 00 ];
 208                         interrupts = <31 2 32 2 33 2>;
 209                         interrupt-parent = <&mpic>;
 210                         phy-handle = <&phy2>;
 211                 };
 212
 213                 enet3: ethernet@27000 {
 214                         cell-index = <3>;
 215                         device_type = "network";
 216                         model = "eTSEC";
 217                         compatible = "gianfar";
 218                         reg = <0x27000 0x1000>;
 219                         local-mac-address = [ 00 00 00 00 00 00 ];
 220                         interrupts = <37 2 38 2 39 2>;
 221                         interrupt-parent = <&mpic>;
 222                         phy-handle = <&phy3>;
 223                 };
 224  */
 225
 226                 serial0: serial@4500 {
 227                         cell-index = <0>;
 228                         device_type = "serial";
 229                         compatible = "ns16550";
 230                         reg = <0x4500 0x100>;   // reg base, size
 231                         clock-frequency = <0>;  // should we fill in in uboot?
 232                         interrupts = <42 2>;
 233                         interrupt-parent = <&mpic>;
 234                 };
 235
 236                 serial1: serial@4600 {
 237                         cell-index = <1>;
 238                         device_type = "serial";
 239                         compatible = "ns16550";
 240                         reg = <0x4600 0x100>;   // reg base, size
 241                         clock-frequency = <0>;  // should we fill in in uboot?
 242                         interrupts = <42 2>;
 243                         interrupt-parent = <&mpic>;
 244                 };
 245
 246                 global-utilities@e0000 {        //global utilities reg
 247                         compatible = "fsl,mpc8548-guts";
 248                         reg = <0xe0000 0x1000>;
 249                         fsl,has-rstcr;
 250                 };
 251
 252                 mpic: pic@40000 {
 253                         interrupt-controller;
 254                         #address-cells = <0>;
 255                         #interrupt-cells = <2>;
 256                         reg = <0x40000 0x40000>;
 257                         compatible = "chrp,open-pic";
 258                         device_type = "open-pic";
 259                 };
 260         };
 261
 262         pci0: pci@e0008000 {
 263                 cell-index = <0>;
 264                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 265                 interrupt-map = <
 266                         /* IDSEL 0x4 (PCIX Slot 2) */
 267                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 268                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 269                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 270                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 271
 272                         /* IDSEL 0x5 (PCIX Slot 3) */
 273                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 274                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
 275                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
 276                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 277
 278                         /* IDSEL 0x6 (PCIX Slot 4) */
 279                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 280                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 281                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 282                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 283
 284                         /* IDSEL 0x8 (PCIX Slot 5) */
 285                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
 286                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
 287                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
 288                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 289
 290                         /* IDSEL 0xC (Tsi310 bridge) */
 291                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
 292                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
 293                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
 294                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 295
 296                         /* IDSEL 0x14 (Slot 2) */
 297                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
 298                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
 299                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
 300                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 301
 302                         /* IDSEL 0x15 (Slot 3) */
 303                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
 304                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
 305                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
 306                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 307
 308                         /* IDSEL 0x16 (Slot 4) */
 309                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
 310                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
 311                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
 312                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 313
 314                         /* IDSEL 0x18 (Slot 5) */
 315                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
 316                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
 317                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
 318                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 319
 320                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 321                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
 322                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
 323                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
 324                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 325
 326                 interrupt-parent = <&mpic>;
 327                 interrupts = <24 2>;
 328                 bus-range = <0 0>;
 329                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 330                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 331                 clock-frequency = <66666666>;
 332                 #interrupt-cells = <1>;
 333                 #size-cells = <2>;
 334                 #address-cells = <3>;
 335                 reg = <0xe0008000 0x1000>;
 336                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 337                 device_type = "pci";
 338
 339                 pci_bridge@1c {
 340                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 341                         interrupt-map = <
 342
 343                                 /* IDSEL 0x00 (PrPMC Site) */
 344                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
 345                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
 346                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
 347                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
 348
 349                                 /* IDSEL 0x04 (VIA chip) */
 350                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 351                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 352                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 353                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 354
 355                                 /* IDSEL 0x05 (8139) */
 356                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 357
 358                                 /* IDSEL 0x06 (Slot 6) */
 359                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 360                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 361                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 362                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 363
 364                                 /* IDESL 0x07 (Slot 7) */
 365                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
 366                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
 367                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
 368                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 369
 370                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 371                         #interrupt-cells = <1>;
 372                         #size-cells = <2>;
 373                         #address-cells = <3>;
 374                         ranges = <0x2000000 0x0 0x80000000
 375                                   0x2000000 0x0 0x80000000
 376                                   0x0 0x20000000
 377                                   0x1000000 0x0 0x0
 378                                   0x1000000 0x0 0x0
 379                                   0x0 0x80000>;
 380                         clock-frequency = <33333333>;
 381
 382                         isa@4 {
 383                                 device_type = "isa";
 384                                 #interrupt-cells = <2>;
 385                                 #size-cells = <1>;
 386                                 #address-cells = <2>;
 387                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 388                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 389                                 interrupt-parent = <&i8259>;
 390
 391                                 i8259: interrupt-controller@20 {
 392                                         interrupt-controller;
 393                                         device_type = "interrupt-controller";
 394                                         reg = <0x1 0x20 0x2
 395                                                0x1 0xa0 0x2
 396                                                0x1 0x4d0 0x2>;
 397                                         #address-cells = <0>;
 398                                         #interrupt-cells = <2>;
 399                                         compatible = "chrp,iic";
 400                                         interrupts = <0 1>;
 401                                         interrupt-parent = <&mpic>;
 402                                 };
 403
 404                                 rtc@70 {
 405                                         compatible = "pnpPNP,b00";
 406                                         reg = <0x1 0x70 0x2>;
 407                                 };
 408                         };
 409                 };
 410         };
 411
 412         pci1: pci@e0009000 {
 413                 cell-index = <1>;
 414                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 415                 interrupt-map = <
 416
 417                         /* IDSEL 0x15 */
 418                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 419                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
 420                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
 421                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 422
 423                 interrupt-parent = <&mpic>;
 424                 interrupts = <25 2>;
 425                 bus-range = <0 0>;
 426                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 427                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 428                 clock-frequency = <66666666>;
 429                 #interrupt-cells = <1>;
 430                 #size-cells = <2>;
 431                 #address-cells = <3>;
 432                 reg = <0xe0009000 0x1000>;
 433                 compatible = "fsl,mpc8540-pci";
 434                 device_type = "pci";
 435         };
 436
 437         pci2: pcie@e000a000 {
 438                 cell-index = <2>;
 439                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 440                 interrupt-map = <
 441
 442                         /* IDSEL 0x0 (PEX) */
 443                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 444                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 445                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 446                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 447
 448                 interrupt-parent = <&mpic>;
 449                 interrupts = <26 2>;
 450                 bus-range = <0 255>;
 451                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 452                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 453                 clock-frequency = <33333333>;
 454                 #interrupt-cells = <1>;
 455                 #size-cells = <2>;
 456                 #address-cells = <3>;
 457                 reg = <0xe000a000 0x1000>;
 458                 compatible = "fsl,mpc8548-pcie";
 459                 device_type = "pci";
 460                 pcie@0 {
 461                         reg = <0x0 0x0 0x0 0x0 0x0>;
 462                         #size-cells = <2>;
 463                         #address-cells = <3>;
 464                         device_type = "pci";
 465                         ranges = <0x2000000 0x0 0xa0000000
 466                                   0x2000000 0x0 0xa0000000
 467                                   0x0 0x20000000
 468
 469                                   0x1000000 0x0 0x0
 470                                   0x1000000 0x0 0x0
 471                                   0x0 0x100000>;
 472                 };
 473         };
 474 };