err.no Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8548CDS";
  15         compatible = "MPC8548CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8548@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 08000000>;      // 128M at 0x0
  40         };
  41
  42         soc8548@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  49                 bus-frequency = <0>;
  50
  51                 memory-controller@2000 {
  52                         compatible = "fsl,8548-memory-controller";
  53                         reg = <2000 1000>;
  54                         interrupt-parent = <&mpic>;
  55                         interrupts = <12 2>;
  56                 };
  57
  58                 l2-cache-controller@20000 {
  59                         compatible = "fsl,8548-l2-cache-controller";
  60                         reg = <20000 1000>;
  61                         cache-line-size = <20>; // 32 bytes
  62                         cache-size = <80000>;   // L2, 512K
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <10 2>;
  65                 };
  66
  67                 i2c@3000 {
  68                         device_type = "i2c";
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <2b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 mdio@24520 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         device_type = "mdio";
  80                         compatible = "gianfar";
  81                         reg = <24520 20>;
  82                         phy0: ethernet-phy@0 {
  83                                 interrupt-parent = <&mpic>;
  84                                 interrupts = <5 1>;
  85                                 reg = <0>;
  86                                 device_type = "ethernet-phy";
  87                         };
  88                         phy1: ethernet-phy@1 {
  89                                 interrupt-parent = <&mpic>;
  90                                 interrupts = <5 1>;
  91                                 reg = <1>;
  92                                 device_type = "ethernet-phy";
  93                         };
  94                         phy2: ethernet-phy@2 {
  95                                 interrupt-parent = <&mpic>;
  96                                 interrupts = <5 1>;
  97                                 reg = <2>;
  98                                 device_type = "ethernet-phy";
  99                         };
 100                         phy3: ethernet-phy@3 {
 101                                 interrupt-parent = <&mpic>;
 102                                 interrupts = <5 1>;
 103                                 reg = <3>;
 104                                 device_type = "ethernet-phy";
 105                         };
 106                 };
 107
 108                 ethernet@24000 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         device_type = "network";
 112                         model = "eTSEC";
 113                         compatible = "gianfar";
 114                         reg = <24000 1000>;
 115                         local-mac-address = [ 00 00 00 00 00 00 ];
 116                         interrupts = <1d 2 1e 2 22 2>;
 117                         interrupt-parent = <&mpic>;
 118                         phy-handle = <&phy0>;
 119                 };
 120
 121                 ethernet@25000 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         device_type = "network";
 125                         model = "eTSEC";
 126                         compatible = "gianfar";
 127                         reg = <25000 1000>;
 128                         local-mac-address = [ 00 00 00 00 00 00 ];
 129                         interrupts = <23 2 24 2 28 2>;
 130                         interrupt-parent = <&mpic>;
 131                         phy-handle = <&phy1>;
 132                 };
 133
 134 /* eTSEC 3/4 are currently broken
 135                 ethernet@26000 {
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138                         device_type = "network";
 139                         model = "eTSEC";
 140                         compatible = "gianfar";
 141                         reg = <26000 1000>;
 142                         local-mac-address = [ 00 00 00 00 00 00 ];
 143                         interrupts = <1f 2 20 2 21 2>;
 144                         interrupt-parent = <&mpic>;
 145                         phy-handle = <&phy2>;
 146                 };
 147
 148                 ethernet@27000 {
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         device_type = "network";
 152                         model = "eTSEC";
 153                         compatible = "gianfar";
 154                         reg = <27000 1000>;
 155                         local-mac-address = [ 00 00 00 00 00 00 ];
 156                         interrupts = <25 2 26 2 27 2>;
 157                         interrupt-parent = <&mpic>;
 158                         phy-handle = <&phy3>;
 159                 };
 160  */
 161
 162                 serial@4500 {
 163                         device_type = "serial";
 164                         compatible = "ns16550";
 165                         reg = <4500 100>;       // reg base, size
 166                         clock-frequency = <0>;  // should we fill in in uboot?
 167                         interrupts = <2a 2>;
 168                         interrupt-parent = <&mpic>;
 169                 };
 170
 171                 serial@4600 {
 172                         device_type = "serial";
 173                         compatible = "ns16550";
 174                         reg = <4600 100>;       // reg base, size
 175                         clock-frequency = <0>;  // should we fill in in uboot?
 176                         interrupts = <2a 2>;
 177                         interrupt-parent = <&mpic>;
 178                 };
 179
 180                 global-utilities@e0000 {        //global utilities reg
 181                         compatible = "fsl,mpc8548-guts";
 182                         reg = <e0000 1000>;
 183                         fsl,has-rstcr;
 184                 };
 185
 186                 pci1: pci@8000 {
 187                         interrupt-map-mask = <1f800 0 0 7>;
 188                         interrupt-map = <
 189                                 /* IDSEL 0x4 (PCIX Slot 2) */
 190                                 02000 0 0 1 &mpic 0 1
 191                                 02000 0 0 2 &mpic 1 1
 192                                 02000 0 0 3 &mpic 2 1
 193                                 02000 0 0 4 &mpic 3 1
 194
 195                                 /* IDSEL 0x5 (PCIX Slot 3) */
 196                                 02800 0 0 1 &mpic 1 1
 197                                 02800 0 0 2 &mpic 2 1
 198                                 02800 0 0 3 &mpic 3 1
 199                                 02800 0 0 4 &mpic 0 1
 200
 201                                 /* IDSEL 0x6 (PCIX Slot 4) */
 202                                 03000 0 0 1 &mpic 2 1
 203                                 03000 0 0 2 &mpic 3 1
 204                                 03000 0 0 3 &mpic 0 1
 205                                 03000 0 0 4 &mpic 1 1
 206
 207                                 /* IDSEL 0x8 (PCIX Slot 5) */
 208                                 04000 0 0 1 &mpic 0 1
 209                                 04000 0 0 2 &mpic 1 1
 210                                 04000 0 0 3 &mpic 2 1
 211                                 04000 0 0 4 &mpic 3 1
 212
 213                                 /* IDSEL 0xC (Tsi310 bridge) */
 214                                 06000 0 0 1 &mpic 0 1
 215                                 06000 0 0 2 &mpic 1 1
 216                                 06000 0 0 3 &mpic 2 1
 217                                 06000 0 0 4 &mpic 3 1
 218
 219                                 /* IDSEL 0x14 (Slot 2) */
 220                                 0a000 0 0 1 &mpic 0 1
 221                                 0a000 0 0 2 &mpic 1 1
 222                                 0a000 0 0 3 &mpic 2 1
 223                                 0a000 0 0 4 &mpic 3 1
 224
 225                                 /* IDSEL 0x15 (Slot 3) */
 226                                 0a800 0 0 1 &mpic 1 1
 227                                 0a800 0 0 2 &mpic 2 1
 228                                 0a800 0 0 3 &mpic 3 1
 229                                 0a800 0 0 4 &mpic 0 1
 230
 231                                 /* IDSEL 0x16 (Slot 4) */
 232                                 0b000 0 0 1 &mpic 2 1
 233                                 0b000 0 0 2 &mpic 3 1
 234                                 0b000 0 0 3 &mpic 0 1
 235                                 0b000 0 0 4 &mpic 1 1
 236
 237                                 /* IDSEL 0x18 (Slot 5) */
 238                                 0c000 0 0 1 &mpic 0 1
 239                                 0c000 0 0 2 &mpic 1 1
 240                                 0c000 0 0 3 &mpic 2 1
 241                                 0c000 0 0 4 &mpic 3 1
 242
 243                                 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 244                                 0E000 0 0 1 &mpic 0 1
 245                                 0E000 0 0 2 &mpic 1 1
 246                                 0E000 0 0 3 &mpic 2 1
 247                                 0E000 0 0 4 &mpic 3 1
 248
 249                                 /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
 250                                 11000 0 0 1 &mpic 2 1
 251                                 11000 0 0 2 &mpic 3 1
 252                                 11000 0 0 3 &mpic 0 1
 253                                 11000 0 0 4 &mpic 1 1
 254
 255                                 /* VIA chip */
 256                                 12000 0 0 1 &mpic 0 1
 257                                 12000 0 0 2 &mpic 1 1
 258                                 12000 0 0 3 &mpic 2 1
 259                                 12000 0 0 4 &mpic 3 1>;
 260
 261                         interrupt-parent = <&mpic>;
 262                         interrupts = <18 2>;
 263                         bus-range = <0 0>;
 264                         ranges = <02000000 0 80000000 80000000 0 10000000
 265                                   01000000 0 00000000 e2000000 0 00800000>;
 266                         clock-frequency = <3f940aa>;
 267                         #interrupt-cells = <1>;
 268                         #size-cells = <2>;
 269                         #address-cells = <3>;
 270                         reg = <8000 1000>;
 271                         compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 272                         device_type = "pci";
 273
 274                         i8259@4 {
 275                                 clock-frequency = <0>;
 276                                 interrupt-controller;
 277                                 device_type = "interrupt-controller";
 278                                 reg = <12000 0 0 0 1>;
 279                                 #address-cells = <0>;
 280                                 #interrupt-cells = <2>;
 281                                 built-in;
 282                                 compatible = "chrp,iic";
 283                                 big-endian;
 284                                 interrupts = <1>;
 285                                 interrupt-parent = <&pci1>;
 286                         };
 287                 };
 288
 289                 pci@9000 {
 290                         interrupt-map-mask = <f800 0 0 7>;
 291                         interrupt-map = <
 292
 293                                 /* IDSEL 0x15 */
 294                                 a800 0 0 1 &mpic b 1
 295                                 a800 0 0 2 &mpic b 1
 296                                 a800 0 0 3 &mpic b 1
 297                                 a800 0 0 4 &mpic b 1>;
 298
 299                         interrupt-parent = <&mpic>;
 300                         interrupts = <19 2>;
 301                         bus-range = <0 0>;
 302                         ranges = <02000000 0 90000000 90000000 0 10000000
 303                                   01000000 0 00000000 e2800000 0 00800000>;
 304                         clock-frequency = <3f940aa>;
 305                         #interrupt-cells = <1>;
 306                         #size-cells = <2>;
 307                         #address-cells = <3>;
 308                         reg = <9000 1000>;
 309                         compatible = "fsl,mpc8540-pci";
 310                         device_type = "pci";
 311                 };
 312                 /* PCI Express */
 313                 pcie@a000 {
 314                         interrupt-map-mask = <f800 0 0 7>;
 315                         interrupt-map = <
 316
 317                                 /* IDSEL 0x0 (PEX) */
 318                                 00000 0 0 1 &mpic 0 1
 319                                 00000 0 0 2 &mpic 1 1
 320                                 00000 0 0 3 &mpic 2 1
 321                                 00000 0 0 4 &mpic 3 1>;
 322
 323                         interrupt-parent = <&mpic>;
 324                         interrupts = <1a 2>;
 325                         bus-range = <0 ff>;
 326                         ranges = <02000000 0 a0000000 a0000000 0 20000000
 327                                   01000000 0 00000000 e3000000 0 08000000>;
 328                         clock-frequency = <1fca055>;
 329                         #interrupt-cells = <1>;
 330                         #size-cells = <2>;
 331                         #address-cells = <3>;
 332                         reg = <a000 1000>;
 333                         compatible = "fsl,mpc8548-pcie";
 334                         device_type = "pci";
 335                 };
 336
 337                 mpic: pic@40000 {
 338                         clock-frequency = <0>;
 339                         interrupt-controller;
 340                         #address-cells = <0>;
 341                         #interrupt-cells = <2>;
 342                         reg = <40000 40000>;
 343                         built-in;
 344                         compatible = "chrp,open-pic";
 345                         device_type = "open-pic";
 346                         big-endian;
 347                 };
 348         };
 349 };