2 * MPC8323E EMDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
14 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
16 * next to the serial ports.
17 * 3) Solder a wire from U61-22 to P19K-22.
19 * Note that there's a typo in the schematic. The board labels the last column
20 * of pins "P19K", but in the schematic, that column is called "P19J". So if
21 * you're going by the schematic, the pin is called "P19J-K22".
25 model = "MPC8323EMDS";
26 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
45 d-cache-line-size = <20>; // 32 bytes
46 i-cache-line-size = <20>; // 32 bytes
47 d-cache-size = <4000>; // L1, 16K
48 i-cache-size = <4000>; // L1, 16K
49 timebase-frequency = <0>;
51 clock-frequency = <0>;
56 device_type = "memory";
57 reg = <00000000 08000000>;
61 device_type = "board-control";
62 reg = <f8000000 8000>;
69 ranges = <0 e0000000 00100000>;
70 reg = <e0000000 00000200>;
71 bus-frequency = <7DE2900>;
74 device_type = "watchdog";
75 compatible = "mpc83xx_wdt";
83 compatible = "fsl-i2c";
86 interrupt-parent = < &ipic >;
90 compatible = "dallas,ds1374";
95 serial0: serial@4500 {
97 device_type = "serial";
98 compatible = "ns16550";
100 clock-frequency = <0>;
102 interrupt-parent = < &ipic >;
105 serial1: serial@4600 {
107 device_type = "serial";
108 compatible = "ns16550";
110 clock-frequency = <0>;
112 interrupt-parent = < &ipic >;
116 device_type = "crypto";
118 compatible = "talitos";
121 interrupt-parent = < &ipic >;
124 channel-fifo-len = <18>;
125 exec-units-mask = <0000004c>;
126 descriptor-types-mask = <0122003f>;
130 interrupt-controller;
131 #address-cells = <0>;
132 #interrupt-cells = <2>;
134 device_type = "ipic";
139 device_type = "par_io";
144 /* port pin dir open_drain assignment has_irq */
145 3 4 3 0 2 0 /* MDIO */
146 3 5 1 0 2 0 /* MDC */
147 0 d 2 0 1 0 /* RX_CLK (CLK9) */
148 3 18 2 0 1 0 /* TX_CLK (CLK10) */
149 1 0 1 0 1 0 /* TxD0 */
150 1 1 1 0 1 0 /* TxD1 */
151 1 2 1 0 1 0 /* TxD2 */
152 1 3 1 0 1 0 /* TxD3 */
153 1 4 2 0 1 0 /* RxD0 */
154 1 5 2 0 1 0 /* RxD1 */
155 1 6 2 0 1 0 /* RxD2 */
156 1 7 2 0 1 0 /* RxD3 */
157 1 8 2 0 1 0 /* RX_ER */
158 1 9 1 0 1 0 /* TX_ER */
159 1 a 2 0 1 0 /* RX_DV */
160 1 b 2 0 1 0 /* COL */
161 1 c 1 0 1 0 /* TX_EN */
162 1 d 2 0 1 0>;/* CRS */
166 /* port pin dir open_drain assignment has_irq */
167 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
168 3 6 2 0 1 0 /* TX_CLK (CLK8) */
169 1 12 1 0 1 0 /* TxD0 */
170 1 13 1 0 1 0 /* TxD1 */
171 1 14 1 0 1 0 /* TxD2 */
172 1 15 1 0 1 0 /* TxD3 */
173 1 16 2 0 1 0 /* RxD0 */
174 1 17 2 0 1 0 /* RxD1 */
175 1 18 2 0 1 0 /* RxD2 */
176 1 19 2 0 1 0 /* RxD3 */
177 1 1a 2 0 1 0 /* RX_ER */
178 1 1b 1 0 1 0 /* TX_ER */
179 1 1c 2 0 1 0 /* RX_DV */
180 1 1d 2 0 1 0 /* COL */
181 1 1e 1 0 1 0 /* TX_EN */
182 1 1f 2 0 1 0>;/* CRS */
188 * port pin dir drain sel irq
190 2 0 1 0 2 0 /* TxD5 */
191 2 8 2 0 2 0 /* RxD5 */
193 2 1d 2 0 0 0 /* CTS5 */
194 2 1f 1 0 2 0 /* RTS5 */
196 2 18 2 0 0 0 /* CD */
205 #address-cells = <1>;
208 compatible = "fsl,qe";
210 ranges = <0 e0100000 00100000>;
211 reg = <e0100000 480>;
213 bus-frequency = <BCD3D80>;
216 device_type = "muram";
217 ranges = <0 00010000 00004000>;
226 compatible = "fsl_spi";
229 interrupt-parent = < &qeic >;
235 compatible = "fsl_spi";
238 interrupt-parent = < &qeic >;
243 compatible = "qe_udc";
244 reg = <6c0 40 8B00 100>;
246 interrupt-parent = < &qeic >;
251 device_type = "network";
252 compatible = "ucc_geth";
258 interrupt-parent = < &qeic >;
259 local-mac-address = [ 00 00 00 00 00 00 ];
260 rx-clock-name = "clk9";
261 tx-clock-name = "clk10";
262 phy-handle = < &phy3 >;
263 pio-handle = < &pio3 >;
267 device_type = "network";
268 compatible = "ucc_geth";
274 interrupt-parent = < &qeic >;
275 local-mac-address = [ 00 00 00 00 00 00 ];
276 rx-clock-name = "clk7";
277 tx-clock-name = "clk8";
278 phy-handle = < &phy4 >;
279 pio-handle = < &pio4 >;
283 device_type = "serial";
284 compatible = "ucc_uart";
286 device-id = <5>; /* The UCC number, 1-7*/
287 port-number = <0>; /* Which ttyQEx device */
288 soft-uart; /* We need Soft-UART */
290 interrupts = <28>; /* From Table 18-12 */
291 interrupt-parent = < &qeic >;
293 * For Soft-UART, we need to set TX to 1X, which
294 * means specifying separate clock sources.
296 rx-clock-name = "brg5";
297 tx-clock-name = "brg6";
298 pio-handle = < &pio5 >;
303 #address-cells = <1>;
306 device_type = "mdio";
307 compatible = "ucc_geth_phy";
309 phy3: ethernet-phy@03 {
310 interrupt-parent = < &ipic >;
313 device_type = "ethernet-phy";
315 phy4: ethernet-phy@04 {
316 interrupt-parent = < &ipic >;
319 device_type = "ethernet-phy";
324 interrupt-controller;
325 device_type = "qeic";
326 #address-cells = <0>;
327 #interrupt-cells = <1>;
330 interrupts = <20 8 21 8>; //high:32 low:33
331 interrupt-parent = < &ipic >;
337 interrupt-map-mask = <f800 0 0 7>;
339 /* IDSEL 0x11 AD17 */
340 8800 0 0 1 &ipic 14 8
341 8800 0 0 2 &ipic 15 8
342 8800 0 0 3 &ipic 16 8
343 8800 0 0 4 &ipic 17 8
345 /* IDSEL 0x12 AD18 */
346 9000 0 0 1 &ipic 16 8
347 9000 0 0 2 &ipic 17 8
348 9000 0 0 3 &ipic 14 8
349 9000 0 0 4 &ipic 15 8
351 /* IDSEL 0x13 AD19 */
352 9800 0 0 1 &ipic 17 8
353 9800 0 0 2 &ipic 14 8
354 9800 0 0 3 &ipic 15 8
355 9800 0 0 4 &ipic 16 8
358 a800 0 0 1 &ipic 14 8
359 a800 0 0 2 &ipic 15 8
360 a800 0 0 3 &ipic 16 8
361 a800 0 0 4 &ipic 17 8
364 b000 0 0 1 &ipic 17 8
365 b000 0 0 2 &ipic 14 8
366 b000 0 0 3 &ipic 15 8
367 b000 0 0 4 &ipic 16 8
370 b800 0 0 1 &ipic 16 8
371 b800 0 0 2 &ipic 17 8
372 b800 0 0 3 &ipic 14 8
373 b800 0 0 4 &ipic 15 8
376 c000 0 0 1 &ipic 15 8
377 c000 0 0 2 &ipic 16 8
378 c000 0 0 3 &ipic 17 8
379 c000 0 0 4 &ipic 14 8>;
380 interrupt-parent = < &ipic >;
383 ranges = <02000000 0 90000000 90000000 0 10000000
384 42000000 0 80000000 80000000 0 10000000
385 01000000 0 00000000 d0000000 0 00100000>;
386 clock-frequency = <0>;
387 #interrupt-cells = <1>;
389 #address-cells = <3>;
390 reg = <e0008500 100>;
391 compatible = "fsl,mpc8349-pci";